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| user? manual pd784216a, 784218a, 784216ay, 784218ay subseries document no. u13570ej3v0ud00 (3rd edition) date published march 2003 n cp(k) 16-bit single-chip microcontrollers pd784214a pd784214ay pd784215a pd784215ay pd784216a pd784216ay pd784217a pd784217ay pd784218a pd784218ay pd78f4216a pd78f4216ay pd78f4218a pd78f4218ay hardware 1999, 2003 printed in japan
2 user s manual u13570ej3v0ud [memo] 3 user s manual u13570ej3v0ud fip, eeprom, and iebus are trademarks of nec electronics corporation. windows and windowsnt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation in the usa. sparcstation is a trademark of sparc international, inc. in the usa. solaris and sunos are trademarks of sun microsystems, inc. in the usa. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company in the usa. ethernet is a trademark of xerox corporation in the usa. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 user s manual u13570ej3v0ud purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of november, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": 5 user s manual u13570ej3v0ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v ? lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user s manual u13570ej3v0ud major revisions in this edition page description chapter 1 general p.33 update of 78k/iv product lineup chapter 4 clock generator p.108 modification of figure 4-4 clock status register (pcs) format chapter 23 interrupt functions p.406 modification of tmic00 bit name in figure 23-1 interrupt control register ( icn) chapter 25 standby function p.515 modification of figure 25-1 standby function state transitions p.533 modification of table 25-5 operating states in stop mode p.539 modification of description in 25.4.2 (3) releasing the stop mode by reset input p.546 modification of description in 25.5.2 (3) releasing the idle mode by reset input p.549 modification of description in 25.6 (5) a/d converter p.554 modification of description in 25.7.3 (1) (b) (iii) releasing the halt mode by reset input p.555 modification of description in 25.7.3 (2) (a) setting the idle mode and the operating states p.556 modification of description in 25.7.3 (2) (b) (iii) releasing the idle mode by reset input p.606 addition of chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) p.630 addition of chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) p.657 addition of chapter 32 package drawings p.659 addition of chapter 33 recommended soldering conditions modification of description in appendix b development tools pp.665, 666 addition of sp78k4 to b.1 language processing software , modification of description in remark p.667 addition and modification of description in b.3.1 hardware p.669 modification of description in remark in b.3.2 software p.670 addition of b.4 cautions on designing target system p.676 modification of description in appendix c embedded software the mark shows major revised points. 7 user s manual u13570ej3v0ud introduction readers this manual is intended for user engineers who wish to understand the functions of the pd784216a, 784218a, 784216ay, and 784218ay subseries and design its application systems. purpose this manual is intended to help users understand the hardware functions of the pd784216a, 784218a, 784216ay, and 784218ay subseries. organization the pd784216a, 784218a, 784216ay, and 784218ay subseries user? manuals consist of two volumes, hardware (this manual) and instruction. hardware instruction pin functions cpu functions internal block functions addressing interrupts instruction set other on-chip peripheral functions electrical specifications there are cautions associated with using this product. be sure to read the cautions in the text of each chapter and the summary at the end of each chapter. how to read this manual reading this manual requires general knowledge about electronics, logic circuits, and microcontrollers. if there are no particular differences in functions the pd784218a subseries is described as the representative subseries. the pd784218a of the pd784218a subseries is described as the representative mask rom product, and the pd78f4218a is described as the representative flash memory product. if there are differences in functions each product name is presented and described individually. since pd784216a, 784218a subseries products are described as the representative products even in this case, for information on the operation of pd784216ay, 784218ay subseries products, read the pd784214a, 784215a, 784216a, 784217a, 784218a, and 78f4218a as the pd784214ay, 784215ay, 784216ay, 784217ay, 784218ay, and 78f4218ay. to understand the overall functions read this manual in the order of the contents . for unusual operations when debugging see the applicable cautions listed at the end of each chapter. 8 user s manual u13570ej3v0ud to check the details of a register whose name is known see appendix d register index . to learn details of the instruction functions refer to the 78k/iv series user? manual ?instruction (u10905e) . to find out about the electrical specifications refer to the chapter of electrical specifications for application examples of the functions refer to the application notes (published separately). differences between the pd784216a subseries, pd784218a subseries, pd784216ay subseries, and pd784218ay subseries the only functional differences between the four subseries are the clocked serial interface, rom correction, and external access status functions. the four subseries otherwise share the same functions. caution the clocked serial interface is described in the following two chapters. ?chapter 18 3-wire serial i/o mode ?chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) for an overview of the serial interface, read chapter 16 altogether. legend data significance: the left side is the most significant digit. the right side is the least significant digit. active low notation: (overbar on pin or signal name) note : description of note in the text caution : information requiring particular attention remark : supplemental description of the text numerical notations: binary numbers .............. b or decimal numbers ........... hexadecimal numbers ... h 9 user s manual u13570ej3v0ud register notation never write a combination of codes that have ?etting prohibited?written in the register description in this manual. characters that are easily confused: 0 (zero), o (capital o) : 1 (one), l (letter l), i (capital i) b1 0 10 user s manual u13570ej3v0ud related documents the related documents in this publication may include preliminary versions. however, prelimi- nary versions are not marked as such. documents related to devices document name document no. documents related to development tools (user? manuals) document name document no. ra78k4 assembler package operation u15254e language u15255e structured assembler preprocessor u11743e cc78k4 c compiler operation u15557e language u15556e sm78k series ver. 2.30 or later system simulator operation (windows tm based) u15373e external part user open interface specification u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e rx78k4 real-time os fundamentals u10603e installation u10604e project manager ver 3.12 or later (windows based) u14610e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 11 user s manual u13570ej3v0ud documents related to development hardware tools (user? manuals) document name document no. ie-78k4-ns in-circuit emulator u13356e ie-784225-ns-em1 emulation board u13742e ie-784000-r in-circuit emulator u12903e ie-784218-r-em1 emulation board u12155e documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user's manual u13502e other related documents document name document no. semiconductor selection guide - products & packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 12 user s manual u13570ej3v0ud contents chapter 1 overview .......................................................................................................... ............. 31 1.1 features .................................................................................................................... .............. 34 1.2 ordering information ........................................................................................................ ..... 35 1.3 pin configuration (top view) ................................................................................................ 36 1.4 block diagram ............................................................................................................... ......... 40 1.5 function list ............................................................................................................... ............ 41 1.6 differences between models in pd784216a, 784216ay/784218a, 784218ay subseries ............................................................................................................. .43 chapter 2 pin functions .................................................................................................... .......... 44 2.1 pin function list ........................................................................................................... ......... 44 2.2 pin function description .................................................................................................... ... 49 2.3 pin i/o circuit and handling of unused pins ....................................................................... 57 chapter 3 cpu architecture ................................................................................................. .... 61 3.1 memory space ................................................................................................................ ........ 61 3.2 internal rom area ........................................................................................................... ....... 69 3.3 base area ................................................................................................................... ............. 70 3.3.1 vector table area ......................................................................................................... ............... 71 3.3.2 callt instruction table area .............................................................................................. ........ 72 3.3.3 callf instruction entry area .............................................................................................. ........ 72 3.4 internal data area .......................................................................................................... ......... 73 3.4.1 internal ram area ......................................................................................................... ............. 74 3.4.2 special function register (sfr) area ...................................................................................... .... 77 3.4.3 external sfr area ......................................................................................................... ............. 77 3.5 external memory space ....................................................................................................... .. 77 3.6 memory mapping of pd78f4216a and 78f4218a ............................................................. 78 3.7 control registers ........................................................................................................... ........ 80 3.7.1 program counter (pc) ...................................................................................................... .......... 80 3.7.2 program status word (psw) ................................................................................................. ...... 80 3.7.3 using rss bit ............................................................................................................. ................ 84 3.7.4 stack pointer (sp) ........................................................................................................ .............. 87 3.8 general-purpose registers ................................................................................................... 91 3.8.1 configuration ............................................................................................................. ................. 91 3.8.2 functions ................................................................................................................. ................... 93 3.9 special function registers (sfrs) ....................................................................................... 96 3.10 cautions ................................................................................................................... ............... 102 chapter 4 clock generator .................................................................................................. 103 4.1 functions ................................................................................................................... ............. 103 4.2 configuration ............................................................................................................... ........... 103 4.3 control registers ........................................................................................................... ........ 105 4.4 system clock oscillator ..................................................................................................... ... 110 4.4.1 main system clock oscillator .............................................................................................. ......... 110 4.4.2 subsystem clock oscillator ................................................................................................ ......... 110 4.4.3 frequency divider ......................................................................................................... .............. 113 4.4.4 when no subsystem clocks are used ......................................................................................... 113 13 user s manual u13570ej3v0ud 4.5 clock generator operations ................................................................................................. 1 14 4.5.1 main system clock operations .............................................................................................. ...... 115 4.5.2 subsystem clock operations ................................................................................................ ....... 116 4.6 changing system clock and cpu clock settings .............................................................. 117 chapter 5 port functions ................................................................................................... .... 118 5.1 digital input/output ports .................................................................................................. .... 118 5.2 port configuration .......................................................................................................... ........ 120 5.2.1 port 0 .................................................................................................................... ...................... 120 5.2.2 port 1 .................................................................................................................... ...................... 122 5.2.3 port 2 .................................................................................................................... ...................... 123 5.2.4 port 3 .................................................................................................................... ...................... 127 5.2.5 port 4 .................................................................................................................... ...................... 129 5.2.6 port 5 .................................................................................................................... ...................... 130 5.2.7 port 6 .................................................................................................................... ...................... 131 5.2.8 port 7 .................................................................................................................... ...................... 134 5.2.9 port 8 .................................................................................................................... ...................... 137 5.2.10 port 9 ................................................................................................................... ....................... 138 5.2.11 port 10 .................................................................................................................. ...................... 139 5.2.12 port 12 .................................................................................................................. ...................... 140 5.2.13 port 13 .................................................................................................................. ...................... 141 5.3 control registers ........................................................................................................... ........ 142 5.4 operations .................................................................................................................. ............ 148 5.4.1 writing to input/output port .............................................................................................. ........... 148 5.4.2 reading from input/output port ............................................................................................ ....... 148 5.4.3 operations on input/output port ........................................................................................... ....... 148 chapter 6 real-time output functions ............................................................................. 149 6.1 functions ................................................................................................................... ............. 149 6.2 configuration ............................................................................................................... ........... 149 6.3 control registers ........................................................................................................... ........ 152 6.4 operation ................................................................................................................... ............. 154 6.5 usage ....................................................................................................................... ................ 155 6.6 cautions .................................................................................................................... .............. 155 chapter 7 timer overview ................................................................................................... ..... 156 chapter 8 16-bit timer/event counter ................................................................................ 159 8.1 function .................................................................................................................... .............. 159 8.2 configuration ............................................................................................................... ........... 160 8.3 control registers ........................................................................................................... ........ 164 8.4 operation ................................................................................................................... ............. 170 8.4.1 operation as interval timer (16-bit operation) ............................................................................ . 170 8.4.2 operation as ppg output ................................................................................................... ........ 172 8.4.3 operation as pulse width measurement ..................................................................................... 1 73 8.4.4 operation as external event counter ....................................................................................... ... 180 8.4.5 operation as square wave output ........................................................................................... ... 182 8.4.6 operation as one-shot pulse output ........................................................................................ ... 184 8.5 cautions .................................................................................................................... .............. 189 14 user s manual u13570ej3v0ud chapter 9 8-bit timer/event counter 1, 2 ......................................................................... 192 9.1 functions ................................................................................................................... ............. 192 9.2 configuration ............................................................................................................... ........... 193 9.3 control registers ........................................................................................................... ........ 196 9.4 operation ................................................................................................................... ............. 201 9.4.1 operation as interval timer (8-bit operation) ............................................................................. .. 201 9.4.2 operation as external event counter ....................................................................................... ... 205 9.4.3 operation as square wave output (8-bit resolution) ................................................................... 206 9.4.4 operation as 8-bit pwm output ............................................................................................. ..... 207 9.4.5 operation as interval timer (16-bit operation) ............................................................................ . 210 9.5. cautions ................................................................................................................... ............... 211 chapter 10 8-bit timer/event counter 5, 6 ....................................................................... 213 10.1 functions .................................................................................................................. .............. 213 10.2 configuration .............................................................................................................. ............ 214 10.3 control registers .......................................................................................................... ......... 217 10.4 operation .................................................................................................................. .............. 222 10.4.1 operation as interval timer (8-bit operation) ............................................................................ ... 222 10.4.2 operation as external event counter ...................................................................................... .... 226 10.4.3 operation as square wave output (8-bit resolution) ................................................................... 227 10.4.4 operation as 8-bit pwm output ............................................................................................ ...... 228 10.4.5 operation as interval timer (16-bit operation) ........................................................................... .. 231 10.5 cautions ................................................................................................................... ............... 232 chapter 11 8-bit timer/event counter 7, 8 ....................................................................... 234 11.1 functions .................................................................................................................. .............. 234 11.2 configuration .............................................................................................................. ............ 235 11.3 control registers .......................................................................................................... ......... 238 11.4 operation .................................................................................................................. .............. 243 11.4.1 operation as interval timer (8-bit operation) ............................................................................ ... 243 11.4.2 operation as external event counter ...................................................................................... .... 247 11.4.3 operation as square wave output (8-bit resolution) ................................................................... 248 11.4.4 operation as 8-bit pwm output ............................................................................................ ...... 249 11.4.5 operation as interval timer (16-bit operation) ........................................................................... .. 252 11.5 cautions ................................................................................................................... ............... 253 chapter 12 watch timer ...................................................................................................... ........ 255 12.1 function ................................................................................................................... ............... 255 12.2 configuration .............................................................................................................. ............ 256 12.3 control register ........................................................................................................... .......... 257 12.4 operation .................................................................................................................. .............. 259 12.4.1 operation as watch timer ................................................................................................. .......... 259 12.4.2 operation as interval timer .............................................................................................. ........... 259 chapter 13 watchdog timer .................................................................................................. .. 261 13.1 configuration .............................................................................................................. ............ 261 13.2 control register ........................................................................................................... .......... 262 13.3 operations ................................................................................................................. ............. 264 13.3.1 count operation .......................................................................................................... ................ 264 13.3.2 interrupt priority order ................................................................................................. ................ 264 15 user s manual u13570ej3v0ud 13.4 cautions ................................................................................................................... ............... 265 13.4.1 general cautions when using watchdog timer ............................................................................ 265 13.4.2 cautions about pd784218a subseries watchdog timer ........................................................... 265 chapter 14 a/d converter ...................................................................................................... ..... 266 14.1 functions .................................................................................................................. .............. 266 14.2 configuration .............................................................................................................. ............ 266 14.3 control registers .......................................................................................................... ......... 269 14.4 operations ................................................................................................................. ............. 272 14.4.1 basic operations of a/d converter ........................................................................................ ...... 272 14.4.2 input voltage and conversion result ...................................................................................... ...... 274 14.4.3 operation mode of a/d converter .......................................................................................... ..... 275 14.5 cautions ................................................................................................................... ............... 277 chapter 15 d/a converter ................................................................................................... ..... 283 15.1 function ................................................................................................................... ............... 283 15.2 configuration .............................................................................................................. ............ 283 15.3 control registers .......................................................................................................... ......... 285 15.4 operation .................................................................................................................. .............. 286 15.5 cautions ................................................................................................................... ............... 286 chapter 16 serial interface overview .............................................................................. 288 chapter 17 asynchronous serial interface/3-wire serial i/o .............................. 290 17.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode ... 291 17.2 asynchronous serial interface mode ................................................................................... 293 17.2.1 configuration ............................................................................................................ .................. 293 17.2.2 control registers ........................................................................................................ ................. 296 17.3 operation .................................................................................................................. .............. 301 17.3.1 operation stop mode ...................................................................................................... ............ 301 17.3.2 asynchronous serial interface (uart) mode ............................................................................. 302 17.3.3 infrared data transfer mode .............................................................................................. .......... 313 17.3.4 standby mode operation ................................................................................................... ......... 316 17.4 3-wire serial i/o mode ..................................................................................................... ...... 317 17.4.1 configuration ............................................................................................................ .................. 317 17.4.2 control registers ........................................................................................................ ................. 319 17.4.3 operation ................................................................................................................ .................... 320 chapter 18 3-wire serial i/o mode ....................................................................................... 3 23 18.1 function ................................................................................................................... ............... 323 18.2 configuration .............................................................................................................. ............ 323 18.3 control registers .......................................................................................................... ......... 325 18.4 operation .................................................................................................................. .............. 327 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) .......................... 330 19.1 overview of function ....................................................................................................... ...... 330 19.2 configuration .............................................................................................................. ............ 331 19.3 control registers .......................................................................................................... ......... 334 19.4 i 2 c bus mode function .......................................................................................................... 34 5 19.4.1 pin configuration ........................................................................................................ ................ 345 16 user s manual u13570ej3v0ud 19.5 i 2 c bus definitions and control method .............................................................................. 346 19.5.1 start condition .......................................................................................................... .................. 346 19.5.2 address .................................................................................................................. .................... 347 19.5.3 transfer direction specification ......................................................................................... .......... 347 19.5.4 acknowledge signal (ack) ................................................................................................. ........ 355 19.5.5 stop condition ........................................................................................................... .................. 356 19.5.6 wait signal (wait) ....................................................................................................... ............... 350 19.5.7 i 2 c interrupt request (intiic0) .................................................................................................. .. 352 19.5.8 interrupt request (intiic0) generation timing and wait control .................................................. 370 19.5.9 address match detection .................................................................................................. .......... 371 19.5.10 error detection ......................................................................................................... ................... 371 19.5.11 extended codes .......................................................................................................... ................ 372 19.5.12 arbitration ............................................................................................................. ...................... 372 19.5.13 wake-up function ........................................................................................................ ................ 374 19.5.14 communication reservation ............................................................................................... ......... 375 19.5.15 additional cautions ..................................................................................................... ................ 378 19.5.16 communication operation ................................................................................................. ......... 379 19.6 timing charts .............................................................................................................. ........... 381 chapter 20 clock output function ..................................................................................... 388 20.1 functions .................................................................................................................. .............. 388 20.2 configuration .............................................................................................................. ............ 389 20.3 control registers .......................................................................................................... ......... 389 chapter 21 buzzer output functions ................................................................................ 392 21.1 function ................................................................................................................... ............... 392 21.2 configuration .............................................................................................................. ............ 392 21.3 control registers .......................................................................................................... ......... 393 chapter 22 edge detection function ................................................................................. 395 22.1 control registers .......................................................................................................... ......... 395 22.2 edge detection of p00 to p06 pins ....................................................................................... 396 chapter 23 interrupt functions .......................................................................................... 39 7 23.1 interrupt request sources .................................................................................................. .. 398 23.1.1 software interrupts ...................................................................................................... ............... 400 23.1.2 operand error interrupts ................................................................................................. ............ 400 23.1.3 non-maskable interrupts .................................................................................................. .......... 400 23.1.4 maskable interrupts ...................................................................................................... .............. 400 23.2 interrupt service modes .................................................................................................... .... 401 23.2.1 vectored interrupt service ............................................................................................... ............ 401 23.2.2 macro service ............................................................................................................ ................. 401 23.2.3 context switching ........................................................................................................ ............... 401 23.3 interrupt processing control registers ............................................................................... 402 23.3.1 interrupt control registers .............................................................................................. ............. 404 23.3.2 interrupt mask registers (mk0, mk1) ...................................................................................... ... 408 23.3.3 in-service priority register (ispr) ...................................................................................... ......... 410 23.3.4 interrupt mode control register (imc) .................................................................................... ..... 411 23.3.5 watchdog timer mode register (wdm) ....................................................................................... 412 17 user s manual u13570ej3v0ud 23.3.6 interrupt selection control register (snmi) .............................................................................. .... 413 23.3.7 program status word (psw) ................................................................................................ ....... 414 23.4 software interrupt acknowledgment operations ................................................................ 415 23.4.1 brk instruction software interrupt acknowledgement operation ................................................ 415 23.4.2 brkcs instruction software interrupt (software context switching) acknowledgement operation ...................................................................................................... 415 23.5 operand error interrupt acknowledge ................................................................................. 416 23.6 non-maskable interrupt acknowledge ................................................................................. 417 23.7 maskable interrupt acknowledge ......................................................................................... 421 23.7.1 vectored interrupt ....................................................................................................... ................ 423 23.7.2 context switching ........................................................................................................ ............... 423 23.7.3 maskable interrupt priority levels ....................................................................................... ......... 425 23.8 macro service function ..................................................................................................... .... 431 23.8.1 outline of macro service function ........................................................................................ ....... 431 23.8.2 types of macro service ................................................................................................... ........... 431 23.8.3 basic macro service operation ............................................................................................ ....... 434 23.8.4 operation at end of macro service ........................................................................................ ..... 435 23.8.5 macro service control registers .......................................................................................... ........ 438 23.8.6 macro service type a ..................................................................................................... ............. 442 23.8.7 macro service type b ..................................................................................................... ............. 447 23.8.8 macro service type c ..................................................................................................... ............. 452 23.8.9 counter mode ............................................................................................................. ................ 466 23.9 when interrupt requests and macro service are temporarily held pending ................. 468 23.10 instructions whose execution is temporarily suspended by interrupt or macro service ..................................................................................................... 469 23.11 interrupt and macro service operation timing ................................................................... 469 23.11.1 interrupt acknowledge processing time ................................................................................... ... 470 23.11.2 processing time of macro service ........................................................................................ ...... 471 23.12 restoring interrupt function to initial state ........................................................................ 472 23.13 cautions .................................................................................................................. ................ 473 chapter 24 local bus interface functions ................................................................... 475 24.1 external memory expansion function ................................................................................. 475 24.2 control registers .......................................................................................................... ......... 477 24.3 memory map for external memory expansion .................................................................... 480 24.4 timing of external memory expansion functions .............................................................. 491 24.4.1 multiplexed bus mode timing .............................................................................................. ........ 491 24.4.2 separate bus mode timing ................................................................................................. ........ 496 24.5 wait functions ............................................................................................................. ........... 501 24.5.1 address wait ............................................................................................................. .................. 501 24.5.2 access wait .............................................................................................................. .................. 504 24.6 external access status output function ( pd784218a, 784218ay subseries only) ..... 510 24.6.1 overview ................................................................................................................. ................... 510 24.6.2 configuration of external access status output function ............................................................. 510 24.6.3 external access status enable register ................................................................................... .... 511 24.6.4 external access status signal timing ..................................................................................... ..... 511 24.6.5 exa pin status during each mode .......................................................................................... .... 572 24.7 external memory connection example ................................................................................ 513 18 user s manual u13570ej3v0ud chapter 25 standby function ................................................................................................ . 514 25.1 configuration and function ................................................................................................. . 514 25.2 control registers .......................................................................................................... ......... 516 25.3 halt mode .................................................................................................................. ........... 522 25.3.1 settings and operating states of halt mode ............................................................................. 52 2 25.3.2 releasing halt mode ...................................................................................................... .......... 524 25.4 stop mode .................................................................................................................. ........... 532 25.4.1 settings and operating states of stop mode ............................................................................ 532 25.4.2 releasing stop mode ...................................................................................................... ......... 534 25.5 idle mode .................................................................................................................. ............. 540 25.5.1 settings and operating states of idle mode .............................................................................. 5 40 25.5.2 releasing idle mode ...................................................................................................... .......... 542 25.6 check items when using stop or idle mode ................................................................... 547 25.7 low power consumption mode ............................................................................................ 550 25.7.1 setting low power consumption mode ....................................................................................... . 550 25.7.2 returning to main system clock operation ................................................................................. 551 25.7.3 standby function in low power consumption mode .................................................................... 552 chapter 26 reset function .................................................................................................. .... 557 chapter 27 rom correction ( pd784218a, 784218ay subseries only) .................... 559 27.1 rom correction functions ................................................................................................... . 559 27.2 rom correction configuration ............................................................................................. 56 1 27.3 control register for rom correction ................................................................................... 563 27.4 usage of rom correction .................................................................................................... .. 565 27.5 conditions for executing rom correction .......................................................................... 566 chapter 28 flash memory programming ........................................................................... 567 28.1 selecting communication protocol ...................................................................................... 567 28.2 flash memory programming functions ............................................................................... 568 28.3 connecting flashpro iii .................................................................................................... ..... 569 chapter 29 instruction operation ....................................................................................... 571 29.1 examples ................................................................................................................... .............. 571 29.2 list of operations ......................................................................................................... .......... 575 29.3 lists of addressing instructions .......................................................................................... 6 00 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) ........................... 606 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) ................................................................................................................... 63 0 chapter 32 package drawings ............................................................................................... 6 57 chapter 33 recommended soldering conditions .......................................................... 659 appendix a major differences from pd78078y subseries ...................................... 661 appendix b development tools ............................................................................................. 66 2 b.1 language processing software ............................................................................................ 665 19 user s manual u13570ej3v0ud b.2 flash memory writing tools ................................................................................................. 6 66 b.3 debugging tools ............................................................................................................. ....... 667 b.3.1 hardware .................................................................................................................. .................. 667 b.3.2 software .................................................................................................................. ................... 669 b.4 cautions on designing target system ................................................................................ 670 b.5 conversion socket (ev-9200gf-100) and conversion adapter (tgc-100sdw) .............. 673 appendix c embedded software ............................................................................................ 676 appendix d register index .................................................................................................. ...... 677 d.1 register index (alphabetical order) ..................................................................................... 677 d.2 register index (alphabetical order) ..................................................................................... 681 appendix e revision history ................................................................................................ .... 685 20 user s manual u13570ej3v0ud list of figures (1/8) figure no. title page 2-1 pin i/o circuit ............................................................................................................. ............................. 59 3-1 pd784214a memory map ........................................................................................................... .......... 64 3-2 pd784215a memory map ........................................................................................................... .......... 65 3-3 pd784216a memory map ........................................................................................................... .......... 66 3-4 pd784217a memory map ........................................................................................................... .......... 67 3-5 pd784218a memory map ........................................................................................................... .......... 68 3-6 internal ram memory map ..................................................................................................... ................ 75 3-7 internal memory size switching register (ims) format ........................................................................ .78 3-8 program counter (pc) format ................................................................................................. ............... 80 3-9 program status word (psw) format ............................................................................................ ......... 81 3-10 stack pointer (sp) format .................................................................................................. .................... 87 3-11 data saved to stack ........................................................................................................ ....................... 88 3-12 data restored from stack ................................................................................................... .................... 89 3-13 general-purpose register format ............................................................................................ .............. 91 3-14 general-purpose register addresses ......................................................................................... ........... 92 4-1 block diagram of clock generator ............................................................................................ ............. 104 4-2 standby control register (stbc) format ...................................................................................... ........ 110 4-3 oscillation mode selection register (cc) format ............................................................................. ..... 107 4-4 clock status register (pcs) format .......................................................................................... ............ 108 4-5 oscillation stabilization time specification register (osts) format ..................................................... 109 4-6 external circuit of main system clock oscillator ............................................................................ ........ 110 4-7 external circuit of subsystem clock oscillator .............................................................................. ......... 110 4-8 examples of oscillator connected incorrectly ................................................................................ ........ 111 4-9 main system clock stop function ............................................................................................. ............. 115 4-10 system clock and cpu clock switching ....................................................................................... ......... 117 5-1 port configuration .......................................................................................................... ......................... 118 5-2 block diagram of p00 to p06 ................................................................................................. ................. 121 5-3 block diagram of p10 to p17 ................................................................................................. ................. 122 5-4 block diagram of p20 and p22 ................................................................................................ ............... 123 5-5 block diagram of p21, p23, p24, and p26 ..................................................................................... ........ 124 5-6 block diagram of p25 ........................................................................................................ ..................... 125 5-7 block diagram of p27 ........................................................................................................ ..................... 126 5-8 block diagram of p30 to p32 and p37 ......................................................................................... .......... 127 5-9 block diagram of p33 to p36 ................................................................................................. ................. 128 5-10 block diagram of p40 to p47 ................................................................................................ .................. 129 5-11 block diagram of p50 to p57 ................................................................................................ .................. 130 5-12 block diagram of p60 to p63 ................................................................................................ .................. 131 5-13 block diagram of p64, p65, and p67 ......................................................................................... ............ 132 5-14 block diagram of p66 ....................................................................................................... ...................... 133 5-15 block diagram of p70 ....................................................................................................... ...................... 134 21 user s manual u13570ej3v0ud list of figures (2/8) figure no. title page 5-16 block diagram of p71 ....................................................................................................... ...................... 135 5-17 block diagram of p72 ....................................................................................................... ...................... 136 5-18 block diagram of p80 to p87 ................................................................................................ .................. 137 5-19 block diagram of falling edge detection circuit ............................................................................ ........ 137 5-20 block diagram of p90 to p95 ................................................................................................ .................. 138 5-21 block diagram of p100 to p103 .............................................................................................. ................ 139 5-22 block diagram of p120 to p127 .............................................................................................. ................ 140 5-23 block diagram of p130 and p131 ............................................................................................. .............. 141 5-24 port mode register format .................................................................................................. ................... 144 5-25 pull-up resistor option register format .................................................................................... ............ 146 5-26 port function control register (pf2) format ................................................................................ ......... 147 6-1 block diagram of real-time output port ...................................................................................... .......... 150 6-2 real-time output buffer register configuration .............................................................................. ....... 151 6-3 real-time output port mode register (rtpm) format .......................................................................... 1 52 6-4 real-time output port control register (rtpc) format ........................................................................ 153 6-5 example of operation timing of real-time output port (extr = 0, byte = 0) .................................... 154 7-1 timer/counter block diagram ................................................................................................. ................ 157 8-1 block diagram of 16-bit timer/event counter ................................................................................. ....... 160 8-2 format of 16-bit timer mode control register (tmc0) ......................................................................... . 165 8-3 format of capture/compare control register 0 (crc0) ........................................................................ 1 67 8-4 format of 16-bit timer output control register (toc0) ....................................................................... . 168 8-5 format of prescaler mode register 0 (prm0) .................................................................................. ...... 169 8-6 control register settings during interval timer operation ................................................................... .. 170 8-7 configuration of interval timer ............................................................................................. ................... 171 8-8 timing of interval timer operation .......................................................................................... ................ 171 8-9 control register settings during ppg output operation ....................................................................... . 172 8-10 control register settings during pulse width measurement with free-running counter and one capture register ................................................................................. 1 73 8-11 configuration for pulse width measurement with free-running counter .............................................. 174 8-12 timing of pulse width measurement with free-running counter and one capture register (with both edges specified) .................................................................................................... ................ 174 8-13 control register settings during measurement of two pulse widths with free-running counter ........ 175 8-14 cr01 capture operation with rising edge specified .......................................................................... ... 176 8-15 timing of pulse width measurement with free-running counter (with both edges specified) ............. 176 8-16 control register settings during pulse width measurement with free-running counter and two capture registers ................................................................................ 1 77 8-17 timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) ............................................................................. 178 8-18 control register settings during pulse width measurement by restarting ........................................... 179 8-19 timing of pulse width measurement by restarting (with rising edge specified) .................................. 180 8-20 control register settings during external event counter mode ............................................................ 181 22 user s manual u13570ej3v0ud list of figures (3/8) figure no. title page 8-21 configuration of external event counter .................................................................................... ............ 181 8-22 timing of external event counter operation (with rising edge specified) ............................................ 182 8-23 control register settings during square wave output mode ................................................................ 183 8-24 timing of square wave output operation ..................................................................................... ......... 183 8-25 control register settings during one-shot pulse output with software trigger ................................... 185 8-26 timing of one-shot pulse output operation with software trigger ....................................................... 186 8-27 control register settings during one-shot pulse output with external trigger .................................... 187 8-28 timing of one-shot pulse output operation with external trigger (with rising edge specified) .......... 188 8-29 start timing of 16-bit timer register ...................................................................................... ................ 189 8-30 timing after changing value of compare register during timer count operation ............................... 189 8-31 data hold timing of capture register ....................................................................................... ............. 190 8-32 operation timing of ovf0 flag .............................................................................................. ................ 191 9-1 block diagram of 8-bit timer/event counter 1, 2 ............................................................................. ...... 193 9-2 format of 8-bit timer mode control register 1 (tmc1) ........................................................................ . 197 9-3 format of 8-bit timer mode control register 2 (tmc2) ........................................................................ . 198 9-4 format of prescaler mode register 1 (prm1) .................................................................................. ...... 199 9-5 format of prescaler mode register 2 (prm2) .................................................................................. ...... 200 9-6 timing of interval timer operation .......................................................................................... ................ 202 9-7 timing of external event counter operation (with rising edge specified) ............................................ 205 9-8 timing of pwm output ........................................................................................................ .................... 208 9-9 timing of operation based on crn0 transitions ............................................................................... ..... 209 9-10 cascade connection mode with 16-bit resolution ............................................................................. .... 211 9-11 start timing of 8-bit timer counter ........................................................................................ ................. 211 9-12 timing after compare register changes during timer counting .......................................................... 212 10-1 block diagram of 8-bit timer/event counter 5, 6 ............................................................................ ....... 214 10-2 format of 8-bit timer mode control register 5 (tmc5) ....................................................................... .. 218 10-3 format of 8-bit timer mode control register 6 (tmc6) ....................................................................... .. 219 10-4 format of prescaler mode register 5 (prm5) ................................................................................. ....... 220 10-5 format of prescaler mode register 6 (prm6) ................................................................................. ....... 221 10-6 timing of interval timer operation ......................................................................................... ................. 223 10-7 timing of external event counter operation (with rising edge specified) ............................................ 226 10-8 timing of pwm output ....................................................................................................... ..................... 229 10-9 timing of operation based on crn0 transitions .............................................................................. ...... 230 10-10 cascade connection mode with 16-bit resolution ............................................................................ ..... 232 10-11 start timing of 8-bit timer counter ....................................................................................... .................. 232 10-12 timing after compare register changes during timer counting .......................................................... 233 11-1 block diagram of 8-bit timer/event counter 7, 8 ............................................................................ ....... 235 11-2 format of 8-bit timer mode control register 7 (tmc7) ....................................................................... .. 239 11-3 format of 8-bit timer mode control register 8 (tmc8) ....................................................................... .. 240 11-4 format of prescaler mode register 7 (prm7) ................................................................................. ....... 241 23 user s manual u13570ej3v0ud list of figures (4/8) figure no. title page 11-5 format of prescaler mode register 8 (prm8) ................................................................................. ....... 242 11-6 timing of interval timer operation ......................................................................................... ................. 244 11-7 timing of external event counter operation (with rising edge specified) ............................................ 247 11-8 timing of pwm output ....................................................................................................... ..................... 250 11-9 timing of operation based on crn0 transitions .............................................................................. ...... 251 11-10 cascade connection mode with 16-bit resolution ............................................................................ ..... 253 11-11 start timing of 8-bit timer counter register .............................................................................. ............ 253 11-12 timing after compare register changes during timer counting .......................................................... 254 12-1 block diagram of watch timer ............................................................................................... ................ 256 12-2 format of watch timer mode control register (wtm) .......................................................................... . 258 12-3 operation timing of watch timer/interval timer ............................................................................. ........ 260 13-1 watchdog timer block diagram ............................................................................................... .............. 261 13-2 watchdog timer mode register (wdm) format .................................................................................. ... 263 14-1 a/d converter block diagram ................................................................................................ ................. 267 14-2 a/d converter mode register (adm) format ................................................................................... ...... 270 14-3 a/d converter input selection register (adis) format ....................................................................... ... 271 14-4 basic operations of a/d converter .......................................................................................... ............... 273 14-5 relationship between analog input voltage and a/d conversion result ............................................... 274 14-6 a/d conversion operation by hardware start (with falling edge specified) ......................................... 275 14-7 a/d conversion operation by software start ................................................................................. ........ 276 14-8 method to reduce current consumption in standby mode ................................................................... 277 14-9 handling of analog input pin ............................................................................................... .................... 278 14-10 a/d conversion end interrupt generation timing ............................................................................ ....... 279 14-11 conversion results immediately after a/d conversion is started .......................................................... 28 0 14-12 conversion result read timing (when conversion result is undefined) ............................................. 280 14-13 conversion result read timing (when conversion result is normal) .................................................. 281 14-14 handling of av dd pin ........................................................................................................................... .... 281 14-15 internal equivalence circuit of ani0 to ani7 pins ......................................................................... .......... 282 14-16 example of circuit when signal source impedance is high .................................................................. 2 82 15-1 d/a converter block diagram ................................................................................................ ................. 284 15-2 d/a converter mode registers 0, 1 (dam0, dam1) formats ................................................................. 285 15-3 buffer amp insertion example ............................................................................................... ................. 287 16-1 serial interface example ................................................................................................... ...................... 289 17-1 switching asynchronous serial interface mode and 3-wire serial i/o mode ......................................... 291 17-2 block diagram in asynchronous serial interface mode ........................................................................ .. 294 17-3 asynchronous serial interface mode registers 1, 2 (asim1, asim2) format ........................................ 297 17-4 asynchronous serial interface status registers 1, 2 (asis1, asis2) format ........................................ 298 24 user s manual u13570ej3v0ud list of figures (5/8) figure no. title page 17-5 baud rate generator control registers 1, 2 (brgc1, brgc2) format ............................................... 300 17-6 baud rate capacity error considering sampling errors (when k = 0) .................................................. 307 17-7 asynchronous serial interface transmit/receive data format .............................................................. 308 17-8 asynchronous serial interface transmit completion interrupt timing .................................................... 310 17-9 asynchronous serial interface receive completion interrupt timing ..................................................... 311 17-10 receive error timing ...................................................................................................... ........................ 312 17-11 comparison of infrared data transfer mode and uart mode data formats ........................................ 313 17-12 block diagram in 3-wire serial i/o mode ................................................................................... ............ 318 17-13 serial operation mode registers 1, 2 (csim1, csim2) format ............................................................. 319 17-14 serial operation mode registers 1, 2 (csim1, csim2) format ............................................................. 320 17-15 serial operation mode registers 1, 2 (csim1, csim2) format ............................................................. 321 17-16 3-wire serial i/o mode timing ............................................................................................. ................... 322 18-1 block diagram of clocked serial interface (in 3-wire serial i/o mode) ................................................. 324 18-2 serial operation mode register 0 (csim0) format ............................................................................ .... 325 18-3 serial operation mode register 0 (csim0) format ............................................................................ .... 327 18-4 serial operation mode register 0 (csim0) format ............................................................................ .... 328 18-5 3-wire serial i/o mode timing .............................................................................................. .................. 329 19-1 serial bus configuration example in i 2 c bus mode ............................................................................... 331 19-2 block diagram of clocked serial interface (i 2 c bus mode) .................................................................... 332 19-3 i 2 c bus control register (iicc0) format .......................................................................................... ...... 335 19-4 i 2 c bus status register (iics0) format ........................................................................................... ....... 339 19-5 format of prescaler mode register for serial clock (sprm0) ............................................................... 34 3 19-6 pin configuration .......................................................................................................... .......................... 345 19-7 serial data transfer timing of i 2 c bus ................................................................................................... 346 19-8 start condition ............................................................................................................ ............................ 346 19-9 address .................................................................................................................... ............................... 347 19-10 transfer direction specification .......................................................................................... .................... 347 19-11 acknowledge signal ........................................................................................................ ........................ 348 19-12 stop condition ............................................................................................................ ............................ 349 19-13 wait signal ............................................................................................................... ............................... 350 19-14 example of arbitration timing ............................................................................................. .................... 373 19-15 timing of communication reservation ....................................................................................... ............ 376 19-16 communication reservation acceptance timing ............................................................................... ..... 376 19-17 communication reservation procedure ....................................................................................... .......... 377 19-18 master operating procedure ................................................................................................ ................... 379 19-19 slave operating procedure ................................................................................................. .................... 380 19-20 master slave communication example (when master and slave select 9 clock waits) .................. 382 19-21 slave master communication example (when master and slave select 9 clock waits) .................. 385 20-1 remote control output application example .................................................................................. ........ 388 20-2 clock output function block diagram ........................................................................................ ............ 389 25 user s manual u13570ej3v0ud list of figures (6/8) figure no. title page 20-3 clock output control register (cks) format ................................................................................. ........ 390 20-4 port 2 mode register (pm2) format .......................................................................................... ............. 391 21-1 buzzer output function block diagram ....................................................................................... ........... 392 21-2 clock output control register (cks) format ................................................................................. ........ 393 21-3 port 2 mode register (pm2) format .......................................................................................... ............. 394 22-1 format of external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0) ........................................................................ 3 95 22-2 block diagram of p00 to p06 pins ........................................................................................... ............... 396 23-1 interrupt control register ( icn) ........................................................................................................... 405 23-2 format of interrupt mask registers (mk0, mk1) .............................................................................. ...... 409 23-3 format of in-service priority register (ispr) .............................................................................. ........... 410 23-4 format of interrupt mode control register (imc) ............................................................................ ....... 411 23-5 format of watchdog timer mode register (wdm) ............................................................................... .. 412 23-6 format of interrupt selection control register (snmi) ...................................................................... ..... 413 23-7 format of program status word (pswl) ....................................................................................... ........ 414 23-8 context switching operation by execution of brkcs instruction .......................................................... 415 23-9 return from brkcs instruction software interrupt (retcsb instruction operation) ............................ 416 23-10 non-maskable interrupt request acknowledgement operations ........................................................... 417 23-11 interrupt acknowledgement processing algorithm ............................................................................ ...... 422 23-12 context switching operation by generation of interrupt request .......................................................... 42 3 23-13 return from interrupt that uses context switching by means of retcs instruction ............................. 424 23-14 examples of servicing when another interrupt request is generated during interrupt service ........... 426 23-15 examples of servicing of simultaneously generated interrupts ............................................................. 4 29 23-16 differences in level 3 interrupt acknowledgement according to imc register setting .......................... 430 23-17 differences between vectored interrupt and macro service processing ............................................... 431 23-18 macro service processing sequence ......................................................................................... ............ 434 23-19 operation at end of macro service when vcie = 0 ........................................................................... .... 436 23-20 operation at end of macro service when vcie = 1 ........................................................................... .... 437 23-21 macro service control word format ......................................................................................... ............. 439 23-22 macro service mode register format ........................................................................................ ............ 440 23-23 macro service data transfer processing flow (type a) ...................................................................... .. 443 23-24 type a macro service channel .............................................................................................. ................. 445 23-25 asynchronous serial reception ............................................................................................. ................. 446 23-26 macro service data transfer processing flow (type b) ...................................................................... .. 448 23-27 type b macro service channel .............................................................................................. ................ 449 23-28 parallel data input synchronized with external interrupts ................................................................. ..... 450 23-29 parallel data input timing ................................................................................................ ....................... 451 23-30 macro service data transfer processing flow (type c) ...................................................................... .. 453 23-31 type c macro service channel .............................................................................................. ................ 456 23-32 stepping motor open loop control by real-time output port .............................................................. 458 23-33 data transfer control timing .............................................................................................. .................... 459 26 user s manual u13570ej3v0ud list of figures (7/8) figure no. title page 23-34 single-phase excitation of 4-phase stepping motor ......................................................................... ..... 461 23-35 1-2-phase excitation of 4-phase stepping motor ............................................................................ ....... 461 23-36 automatic addition control + ring control block diagram 1 (when output timing varies with 1-2-phase excitation) ........................................................................ 46 2 23-37 automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) ........................................................................ 46 3 23-38 automatic addition control + ring control block diagram 2 (1-2-phase excitation constant-velocity operation) ............................................................................. .. 464 23-39 automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant-velocity operation) ............................................................................. .. 465 23-40 macro service data transfer processing flow (counter mode) ............................................................. 466 23-41 counter mode .............................................................................................................. ........................... 467 23-42 counting number of edges .................................................................................................. ................... 467 23-43 interrupt request generation and acknowledgment (unit: clock = 1/f clk ) ............................................. 469 24-1 memory expansion mode register (mm) format ................................................................................. .. 477 24-2 external bus type selection register (ebts) format ......................................................................... .. 478 24-3 programmable wait control register (pwc1) format ........................................................................... 478 24-4 pd784214a memory map ........................................................................................................... .......... 481 24-5 pd784215a memory map ........................................................................................................... .......... 483 24-6 pd784216a memory map ........................................................................................................... .......... 485 24-7 pd784217a memory map ........................................................................................................... .......... 487 24-8 pd784218a memory map ........................................................................................................... .......... 489 24-9 instruction fetch from external memory in multiplexed bus mode ......................................................... 492 24-10 read timing for external memory in multiplexed bus mode .................................................................. 4 93 24-11 write timing for external memory in multiplexed bus mode .................................................................. 494 24-12 read modify write timing for external memory in multiplexed bus mode ............................................. 495 24-13 instruction fetch from external memory in separate bus mode ............................................................ 497 24-14 read timing for external memory in separate bus mode ...................................................................... 498 24-15 write timing for external memory in separate bus mode ..................................................................... . 499 24-16 read modify write timing for external memory in separate bus mode ................................................. 501 24-17 read/write timing by address wait function ................................................................................ ......... 502 24-18 read timing by access wait function ....................................................................................... ............. 505 24-19 write timing by access wait function ...................................................................................... .............. 507 24-20 timing by external wait signal ............................................................................................ ................... 509 24-21 configuration of external access status output function ................................................................... ... 510 24-22 external access status enable register (exae) format ...................................................................... .511 24-23 example of local bus interface ............................................................................................ .................. 513 25-1 standby function state transitions ......................................................................................... ............... 515 25-2 standby control register (stbc) format ..................................................................................... ......... 517 25-3 clock status register (pcs) format ......................................................................................... ............. 519 25-4 oscillation stabilization time specification register (osts) format ..................................................... 521 27 user s manual u13570ej3v0ud list of figures (8/8) figure no. title page 25-5 operation after halt mode release .......................................................................................... ............ 526 25-6 operation after stop mode release .......................................................................................... ........... 535 25-7 releasing stop mode by nmi input ........................................................................................... ........... 538 25-8 example of releasing stop mode by intp0 to intp6 inputs .............................................................. 539 25-9 operation after idle mode release .......................................................................................... ............. 543 25-10 example of handling address/data bus ...................................................................................... ........... 548 25-11 flow for setting subsystem clock operation ................................................................................ ......... 550 25-12 setting timing for subsystem clock operation .............................................................................. ........ 551 25-13 flow to restore main system clock operation ............................................................................... ....... 552 25-14 timing for restoring main system clock operation .......................................................................... ..... 552 26-1 oscillation of main system clock in reset period ........................................................................... ....... 557 26-2 accepting reset signal ..................................................................................................... ...................... 558 27-1 rom correction block diagram ............................................................................................... ............... 561 27-2 memory mapping example ( pd784218a) ............................................................................................ 562 27-3 rom correction address register (corah, coral) format .............................................................. 563 27-4 rom correction control register (corc) format .............................................................................. ... 564 28-1 communication protocol selection format .................................................................................... ......... 568 28-2 connection of flashpro iii in 3-wire serial i/o mode (when using 3-wire serial i/o) ........................... 569 28-3 connection of flashpro iii in 3-wire serial i/o mode (when using handshake) ................................... 569 28-4 connection of flashpro iii in uart mode (when using uart) ............................................................. 570 30-1 power supply voltage and clock cycle time (cpu clock frequency: f cpu ) .......................................... 607 31-1 power supply voltage and clock cycle time (cpu clock frequency: f cpu ) .......................................... 632 b-1 development tool configuration .............................................................................................. ............... 663 b-2 distance between ie system and conversion adapter .......................................................................... 6 70 b-3 connection conditions of target system (when np-100gc is used) ................................................... 671 b-4 connection conditions of target system (when np-h100gc-tq is used) .......................................... 671 b-5 connection conditions of target system (when np-100gf-tq is used) ............................................. 672 b-6 connection conditions of target system (when np-h100gf-tq is used) ........................................... 672 b-7 package drawing of ev-9200gf-100 (reference) ................................................................................ . 673 b-8 recommended footprint of ev-9200gf-100 (reference) ..................................................................... 674 b-9 package drawing of tgc-100sdw (reference) ................................................................................... . 675 28 user s manual u13570ej3v0ud list of tables (1/3) table no. title page 1-1 differences between models in pd784216a, 784216ay/784218a, 784218ay subseries .................. 43 2-1 i/o circuit type for each pin and handling unused pins ...................................................................... .57 3-1 vector table address ........................................................................................................ ...................... 71 3-2 internal ram area list ...................................................................................................... ...................... 74 3-3 setting value of internal memory size switching register (ims) ........................................................... 78 3-4 setting value of internal memory size switching register (ims) ........................................................... 79 3-5 register bank selection ..................................................................................................... ..................... 83 3-6 correspondence between function names and absolute names ......................................................... 95 3-7 special function register (sfr) list ........................................................................................ .............. 97 4-1 clock generator configuration ............................................................................................... ................ 103 5-1 port functions .............................................................................................................. ........................... 119 5-2 port configuration .......................................................................................................... ......................... 120 5-3 port mode register and output latch settings when using alternate functions .................................. 143 6-1 real-time output port configuration ......................................................................................... ............. 149 6-2 operations for manipulating real-time output buffer registers ............................................................ 151 6-3 operating modes and output triggers of real-time output port ........................................................... 153 7-1 timer/counter operation ..................................................................................................... ................... 156 8-1 16-bit timer/event counter configuration .................................................................................... ........... 160 8-2 valid edge of ti00 pin and capture trigger of cr00 .......................................................................... ... 162 8-3 valid edge of ti01 pin and capture trigger of cr00 .......................................................................... ... 162 8-4 valid edge of ti00 pin and capture trigger of cr01 .......................................................................... ... 163 9-1 8-bit timer/event counter 1, 2 configuration ................................................................................ ......... 193 10-1 8-bit timer/event counter 5, 6 configuration ............................................................................... .......... 214 11-1 8-bit timer/event counter 7, 8 configuration ............................................................................... .......... 235 12-1 interval time of interval timer ............................................................................................ ..................... 255 12-2 configuration of watch timer ............................................................................................... .................. 256 12-3 interval time of interval timer ............................................................................................ ..................... 259 14-1 a/d converter configuration ................................................................................................ ................... 266 14-2 resistance and capacitant values for equivalent circuits (reference values) ..................................... 282 15-1 d/a converter configuration ................................................................................................ ................... 283 29 user s manual u13570ej3v0ud list of tables (2/3) table no. title page 17-1 designation differences between uart1/ioe1 and uart2/ioe2 ........................................................ 290 17-2 serial interface operation mode settings ................................................................................... ............ 292 17-3 asynchronous serial interface configuration ................................................................................ .......... 293 17-4 relationship between main system clock and baud rate .................................................................... 307 17-5 receive error causes ....................................................................................................... ...................... 312 17-6 bit rate and pulse width values ............................................................................................ ................ 314 17-7 3-wire serial i/o configuration ............................................................................................ ................... 317 18-1 3-wire serial i/o configuration ............................................................................................ ................... 323 18-2 serial interface operation mode settings ................................................................................... ............ 325 19-1 i 2 c bus mode configuration ....................................................................................................... ............. 331 19-2 intiic0 generation timing and wait control ................................................................................. ........ 370 19-3 definitions of extended code bits .......................................................................................... ................ 372 19-4 arbitration generation states and interrupt request generation timing ............................................... 373 19-5 wait times ................................................................................................................. ............................. 375 20-1 clock output function configuration ........................................................................................ .............. 389 21-1 buzzer output function configuration ....................................................................................... ............. 392 23-1 interrupt request service modes ............................................................................................ ............... 397 23-2 interrupt request sources .................................................................................................. .................... 398 23-3 control registers .......................................................................................................... .......................... 402 23-4 flag list of interrupt control registers for interrupt requests ............................................................ ... 403 23-5 multiple interrupt servicing ............................................................................................... ...................... 405 23-6 interrupts for which macro service can be used ............................................................................. ...... 432 23-7 interrupt acknowledge processing time ...................................................................................... ........... 470 23-8 macro service processing time .............................................................................................. ............... 471 24-1 pin functions in multiplexed bus mode ...................................................................................... ............ 475 24-2 pin states in ports 4 to 6 in multiplexed bus mode ......................................................................... ....... 475 24-3 pin functions in separate bus mode ......................................................................................... ............. 476 24-4 pin states of ports 4, 5, 6, and 8 in separate bus mode .................................................................... .... 476 24-5 p37/exa pin status during each mode ........................................................................................ ......... 512 25-1 standby function modes ..................................................................................................... ................... 514 25-2 operating states in halt mode .............................................................................................. ............... 523 25-3 releasing halt mode and operation after release ............................................................................ .. 525 25-4 releasing halt mode by maskable interrupt request .......................................................................... 531 25-5 operating states in stop mode .............................................................................................. .............. 533 25-6 releasing stop mode and operation after release ............................................................................ . 534 25-7 operating states in idle mode .............................................................................................. ................ 541 30 user s manual u13570ej3v0ud list of tables (3/3) table no. title page 25-8 releasing idle mode and operation after release ............................................................................ ... 542 25-9 operating states in halt mode .............................................................................................. ............... 553 25-10 operating states in idle mode ............................................................................................. ................. 555 26-1 state after reset for all hardware resets .................................................................................. ............ 558 27-1 differences between 78k/iv rom correction and 78k/0 rom correction ............................................ 560 27-2 rom correction configuration ............................................................................................... ................. 561 28-1 communication protocols .................................................................................................... ................... 567 28-2 major functions in flash memory programming ................................................................................ .... 568 29-1 8-bit addressing instructions .............................................................................................. .................... 600 29-2 16-bit addressing instructions ............................................................................................. ................... 602 29-3 24-bit addressing instructions ............................................................................................. ................... 604 29-4 bit manipulation instruction addressing instructions ....................................................................... ........ 604 29-5 call return instructions and branch instruction addressing instructions ............................................... 605 33-1 surface mounting type soldering conditions ................................................................................. ........ 659 b-1 distance between ie system and conversion adapter .......................................................................... 6 70 31 user s manual u13570ej3v0ud chapter 1 overview the pd784218a subseries is a member of the 78k/iv series and consists of 100-pin products intended for general-purpose applications. the 78k/iv series has 16-bit single-chip microcontrollers and provides a high- performance cpu with functions such as access to a 1 mb memory space. the pd784218a has a 256 kb mask rom and a 12,800-byte ram on chip. in addition, it incorporates a high- performance timer/counter, an 8-bit a/d converter, an 8-bit d/a converter, and an independent 2-channel serial interface. the pd784217a is a product with the mask rom capacity of the pd784218a changed to 192 kb. the pd784216a is based on the pd784218a with 128 kb of mask rom and 8,192 bytes of ram. the pd784215a is based on the pd784218a with 128 kb of mask rom and 5,120 bytes of ram. the pd784214a is based on the pd784218a with 128 kb of mask rom and 3,584 bytes of ram. the pd78f4216a and 78f4218a are products with the mask rom of the pd784216a and 784218a replaced by a flash memory. the pd784216ay and 784218ay subseries adds an i 2 c bus control function to the pd784216a and 784218a subseries. the relationships among these products are shown below. 32 chapter 1 overview user s manual u13570ej3v0ud these products can be applied in the following areas. cellular phones, phs, cordless phones, cd-roms, av equipment, etc. pd78f4218ay pd78f4218a pd784218ay pd784218a pd784217ay pd784217a flash memory 256 k ram 12,800 rom 256 k ram 12,800 rom 192 k ram 12,800 pd78f4216ay pd78f4216a pd784216ay pd784216a pd784215ay pd784215a flash memory 128 k ram 8,192 rom 128 k ram 8,192 rom 128 k ram 5,120 pd784214ay pd784214a rom 96 k ram 3,584 on-chip flash memory product mask rom product 33 chapter 1 overview user s manual u13570ej3v0ud 78k/iv series product development diagram remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. assp development pd784915 multi-master i 2 c bus compatible on-chip iebus tm controller software servo control on-chip analog circuit for vcr timer enhanced function of the pd784915 enhanced pd784928y pd784928 pd784908 for dc inverter control on-chip vfd controller/driver pd784976a function of the pd784908 enhanced internal memory capacity enhanced rom correction added pd784938a pd784956a pd784026 a/d, 16-bit timer, and power management enhanced standard product development pd784038y i 2 c bus compatible pd784038 pd784225y multi-master i 2 c bus compatible multi-master i 2 c bus compatible multi-master i 2 c bus compatible internal memory capacity enhanced pin-compatible with the pd784026 internal memory capacity enhanced rom correction added 100 pins i/o and internal memory capacity enhanced on-chip 10-bit a/d 80 pins rom correction added pd784225 pd784216ay pd784216a pd784218ay pd784218a pd784054 pd784046 : in mass production 34 chapter 1 overview user s manual u13570ej3v0ud 1.1 features on-chip rom correction ( inherits the peripheral functions of the minimum instruction execution time 160 ns (main system clock: f xx = 12.5 mhz operation) 61 instruction set suited for control applications interrupt controller (4-level priority) vectored interrupt servicing, macro service, and context switching standby function halt, stop, and idle modes in the low power consumption mode: halt and idle modes (subsystem clock operation) on-chip memory: mask rom 256 kb ( i/o pins: 86 software programmable pull-up resistors: 70 inputs led direct drive possible: 22 outputs transistor direct drive possible: 6 outputs timer/counter: 16-bit timer/counter watch timer: 1 channel watchdog timer: 1 channel serial interfaces uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, multimaster compatible i 2 c bus note ): 1 channel a/d converter: 8-bit resolution d/a converter: 8-bit resolution real-time output port (by combining with the timer/counter, two stepping motors can be independently controlled) clock frequency function clock output function: select from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , and f xt buzzer output function: select from f xx /2 10 , f xx /2 11 , f xx /2 12 , and f xx /2 13 power supply voltage: v dd = 1.8 to 5.5 v (mask rom version) v dd = 1.9 to 5.5 v (flash memory version) note only in the 35 chapter 1 overview user s manual u13570ej3v0ud 1.2 ordering information (1) pd784216a, 784218a subseries part number package on-chip rom remark (2) pd784216ay, 784218ay subseries part number package on-chip rom remark 36 chapter 1 overview user s manual u13570ej3v0ud 1.3 pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) notes 1. the sda0 and scl0 pins are provided only for the 2. the v pp pin is provided only for the 3. the exa pin is provided only for the 37 chapter 1 overview user s manual u13570ej3v0ud 100-pin plastic qfp (14 38 chapter 1 overview user s manual u13570ej3v0ud cautions 1. connect the test pin directly to v ss or pull down. for the pull-down connection, use of a resistor with a resistance between 470 ? ? ? ? 39 chapter 1 overview user s manual u13570ej3v0ud a0 to a19: address bus p120 to p127: port 12 ad0 to ad7: address/data bus p130, p131: port 13 ani0 to ani7: analog input pcl: programmable clock ano0, ano1: analog output rd: read strobe asck1, asck2: asynchronous serial clock reset: reset astb: address strobe rtp0 to rtp7: real-time output port av dd : analog power supply rxd1, rxd2: receive data av ref0 , av ref1 : analog reference voltage sck0 to sck2: serial clock av ss : analog ground scl0 note 1 : serial clock buz: buzzer clock sda0 note 1 : serial data exa note 3 : external access status output si0 to si2: serial input intp0 to intp6: interrupt from peripherals so0 to so2: serial output nmi: non-maskable interrupt test: test p00 to p06: port 0 ti00, ti01, p10 to p17: port 1 ti1, ti2, ti5 to ti8: timer input p20 to p27: port 2 to0 to to2, to5 to to8: timer output p30 to p37: port 3 txd1, txd2: transmit data p40 to p47: port 4 v dd : power supply p50 to p57: port 5 v pp note 2 : programming power supply p60 to p67: port 6 v ss : ground p70 to p72: port 7 wait: wait p80 to p87: port 8 wr: write strobe p90 to p95: port 9 x1, x2: crystal (main system clock) p100 to p103: port 10 xt1, xt2: crystal (subsystem clock) notes 1. the sda0 and scl0 pins are provided only for the 40 chapter 1 overview user s manual u13570ej3v0ud 1.4 block diagram notes 1. the sda0 and scl0 pins are provided only for the 41 chapter 1 overview user s manual u13570ej3v0ud 1.5 function list (1/2) product name 160 ns (12.5 mhz operation with main system clock) 61 ppg output square wave output one-shot pulse output timer/event counter 1: timer counter pwm output square wave output timer/event counter 2: timer counter pwm output square wave output timer/event counter 5: timer counter pwm output square wave output timer/event counter 6: timer counter pwm output square wave output timer/event counter 7: timer counter pwm output square wave output timer/event counter 8: timer counter pwm output square wave output note the pins with added functions are included in the i/o pins. 42 chapter 1 overview user s manual u13570ej3v0ud (2/2) product name uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, multimaster compatible i 2 c bus note ): 1 channel a/d converter 8-bit resolution halt, stop, and idle modes in the low power consumption mode (cpu operation with subsystem clock): halt and idle modes interrupts hardware source 29 (internal: 20, external: 9) software source brk instruction, brkcs instruction, and operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 8 4-level programmable priority three processing formats: vectored interrupt, macro service, and context switching power supply voltage v dd = 1.8 to 5.5 v v dd = 1.9 v dd = 1.8 to 5.5 v v dd = 1.9 to 5.5 v to 5.5 v package 100-pin plastic lqfp (fine pitch) (14 100-pin plastic qfp (14 43 chapter 1 overview user s manual u13570ej3v0ud 1.6 differences between models in pd784216a, 784216ay/784218a, 784218ay subseries the only difference between the pd784214a, 784215a, 784216a, 784217a, and 784218a line is the internal memory capacity. the pd784214ay, 784215ay, 784216ay, 784217ay, and 784218ay are models with the addition of an i 2 c bus control function. the pd78f4216a, 78f4216ay, 78f4218a, and 78f4218ay are provided with a 128 kb/256 kb flash memory instead of the mask rom of the above models. these differences are summarized in table 1-1. table 1-1. differences between models in pd784216a, 784216ay/784218a, 784218ay subseries part number pd784214a, pd784215a, pd784216a, pd784217a, pd784218a, pd78f4216a, pd78f4218a, item pd784214ay pd784215ay pd784216ay pd784217ay pd784218ay pd78f4216ay pd78f4218ay internal rom 96 kb 128 kb (mask rom) 192 kb 256 kb 128 kb 256 kb (mask (mask (mask (flash (flash rom) rom) rom) memory) memory) internal ram 3,584 bytes 5,120 bytes 8,192 bytes 12,800 bytes 8,192 bytes 12,800 bytes internal memory not provided provided note size switching register (ims) rom correction not provided provided not provided provided external access not provided provided not provided status function provided supply voltage v dd = 1.8 to 5.5 v v dd = 1.9 to 5.5 v electrical refer to the chapters of electrical specifications and recommended soldering conditions. specifications recommended soldering conditions exa pin not provided provided not provided provided test pin provided not provided v pp pin not provided provided note the internal flash memory capacity and internal ram capacity can be changed using the internal memory size switching register (ims). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask rom version. 44 user s manual u13570ej3v0ud chapter 2 pin functions 2.1 pin function list (1) port pins (1/3) pin symbol p00 p01 p02 p03 p04 p05 p06 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 i/o i/o input i/o i/o i/o alternate function intp0 intp1 intp2/nmi intp3 intp4 intp5 intp6 ani0 to ani7 rxd1/si1 txd1/so1 asck1/sck1 pcl buz si0/sda0 note 1 so0 sck0/scl0 note 1 to0 to1 to2 ti1 ti2 ti00 ti01 exa note 2 ad0 to ad7 function port 0 (p0): 7-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units port 1 (p1): 8-bit dedicated input port port 2 (p2): 8-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units port 3 (p3): 8-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units port 4 (p4): 8-bit i/o port input/output can be specified in 1-bit units for input mode pins, on-chip pull-up resistor connection can be specified for all bits at once by the setting of software led can be driven directly notes 1. the sda0 and scl0 pins are provided only for the pd784216ay, 784218ay subseries. 2. the exa pin is provided only for the pd784218a, 784218ay subseries. 45 chapter 2 pin functions user s manual u13570ej3v0ud (1) port pins (2/3) pin symbol p50 to p57 p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p80 to p87 p90 to p95 p100 p101 p102 p103 i/o i/o i/o i/o i/o i/o i/o alternate function a8 to a15 a16 a17 a18 a19 rd wr wait astb rxd2/si2 txd2/so2 asck2/sck2 a0 to a7 ti5/to5 ti6/to6 ti7/to7 ti8/to8 function port 5 (p5): 8-bit i/o port input/output can be specified in 1-bit units for input mode pins, on-chip pull-up resistor connection can be specified for all bits at once by the setting of software led can be driven directly port 6 (p6): 8-bit i/o port input/output can be specified in 1-bit units for input mode pins, on-chip pull-up resistor connection can be specified for all bits at once by the setting of software port 7 (p7): 3-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units port 8 (p8): 8-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units interrupt control flag (krif) is set to 1 by detecting the falling edge port 9 (p9): n-channel open drain medium voltage i/o port 6-bit i/o port input/output can be specified in 1-bit units led can be driven directly port 10 (p10): 4-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units 46 chapter 2 pin functions user s manual u13570ej3v0ud (1) port pins (3/3) pin symbol p120 to p127 p130, p131 i/o i/o i/o alternate function rtp0 to rtp7 ano0, ano1 function port 12 (p12): 8-bit i/o port input/output can be specified in 1-bit units regardless of whether the input or output mode is specified, on-chip pull-up resistor connection can be specified by the setting of software in 1-bit units port 13 (p13): 2-bit i/o port input/output can be specified in 1-bit units 47 chapter 2 pin functions user s manual u13570ej3v0ud (2) non-port pins (1/2) pin symbol i/o alternate function function ti00 input p35 external count clock input to 16-bit timer counter ti01 p36 capture trigger signal input to capture/compare register 00 ti1 p33 external count clock input to 8-bit timer counter 1 ti2 p34 external count clock input to 8-bit timer counter 2 ti5 p100/to5 external count clock input to 8-bit timer counter 5 ti6 p101/to6 external count clock input to 8-bit timer counter 6 ti7 p102/to7 external count clock input to 8-bit timer counter 7 ti8 p103/to8 external count clock input to 8-bit timer counter 8 to0 output p30 16-bit timer output (shared with 14-bit pwm output) to1 p31 8-bit timer output (shared with 8-bit pwm output) to2 p32 to5 p100/ti5 to6 p101/ti6 to7 p102/ti7 to8 p103/ti8 rxd1 input p20/si1 serial data input (uart1) rxd2 p70/si2 serial data input (uart2) txd1 output p21/so1 serial data output (uart1) txd2 p71/so2 serial data output (uart2) asck1 input p22/sck1 baud rate clock input (uart1) asck2 p72/sck2 baud rate clock input (uart2) si0 input p25/sda0 note serial data input (3-wire serial i/o0) si1 p20/rxd1 serial data input (3-wire serial i/o1) si2 p70/rxd2 serial data input (3-wire serial i/o2) so0 output p26 serial data output (3-wire serial i/o0) so1 p21/txd1 serial data output (3-wire serial i/o1) so2 p71/txd2 serial data output (3-wire serial i/o2) sda0 note i/o p25/si0 serial data i/o (i 2 c bus) sck0 p27/scl0 note serial clock i/o (3-wire serial i/o0) sck1 p22/asck1 serial clock i/o (3-wire serial i/o1) sck2 p72/asck2 serial clock i/o (3-wire serial i/o2) scl0 note p27/sck0 serial clock i/o (i 2 c bus) note the sda0 and scl0 pins are provided only for the pd784216ay, 784218ay subseries. 48 chapter 2 pin functions user s manual u13570ej3v0ud (2) non-port pins (2/2) pin symbol i/o alternate function function nmi input p02/intp2 non-maskable interrupt request input intp0 p00 external interrupt request input intp1 p01 intp2 p02/nmi intp3 p03 intp4 p04 intp5 p05 intp6 p06 pcl output p23 clock output (for trimming main system clock and subsystem clock) buz p24 buzzer output rtp0 to rtp7 p120 to p127 real-time output port that outputs data synchronized with the trigger ad0 to ad7 i/o p40 to p47 low-order address/data bus when the memory is externally expanded a0 to a7 output p80 to p87 low-order address bus when the memory is externally expanded a8 to a15 p50 to p57 middle-order address bus when the memory is externally expanded a16 to a19 p60 to p63 high-order address bus when the memory is externally expanded rd p64 strobe signal output for external memory read operation wr p65 strobe signal output for external memory write operation wait input p66 wait insertion during external memory access astb output p67 strobe output that externally latches the address information that is output to ports 4 to 6, and port 8 in order to access external memory exa note 1 p37 status signal output during external memory access reset input system reset input x1 crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation xt2 ani0 to ani7 input p10 to p17 analog voltage input to a/d converter ano0, ano1 output p130, p131 analog voltage output to d/a converter av ref0 reference voltage applied to a/d converter av ref1 reference voltage applied to d/a converter av dd positive power supply to a/d converter. connect to v dd . av ss ground for a/d converter and d/a converter. connect to v ss . v dd positive power supply v ss gnd test v pp note 2 connect directly to v ss or via a pull-down resistor. for the pull-down connection, use of a resistor with a resistance between 470 ? and 10 k ? is recommended. v pp note 2 test flash memory programming mode setting high voltage application pin during program write/verify notes 1. the exa pin is provided only for the pd784218a, 784218ay subseries. 2. the v pp pin is provided only for the pd78f4216a, 784218a, 78f4216ay, and 78f4218ay. 49 chapter 2 pin functions user s manual u13570ej3v0ud 2.2 pin function description (1) p00 to p06 (port 0) this port is a 7-bit i/o port. in addition to being an i/o port, this port has an external interrupt request input function. the following operating modes are selectable in 1-bit units. (a) port mode this port functions as a 7-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 0 mode register. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 0. (b) control mode the port functions as an external interrupt request input. (i) intp0 to intp6 intp0 to intp6 are external interrupt request input pins that can select the valid edge (rising edge, falling edge, or both rising and falling edges). the valid edge can be specified by the external interrupt rising edge enable register and the external interrupt falling edge enable register. intp2 also becomes the external trigger signal input pin of the real-time output port by the valid edge input. (ii) nmi this is the external non-maskable interrupt request input pin. the valid edge can be specified by the external interrupt rising edge enable register and the external interrupt falling edge enable register. 50 chapter 2 pin functions user s manual u13570ej3v0ud (2) p10 to p17 (port 1) this port is an 8-bit dedicated input port. in addition to being a general-purpose input port, this port functions as the analog input for the a/d converter. it does not have on-chip pull-up resistors. (a) port mode the port functions as an 8-bit dedicated input port. (b) control mode the port functions as the analog input pins (ani0 to ani7) of the a/d converter. the values are undefined when the pins specified for analog input are read. (3) p20 to p27 (port 2) this port is an 8-bit i/o port. in addition to being an i/o port, this port has the data i/o function, clock i/o function, clock output function, and output buzzer function of the serial interface. the following operating modes are selectable in 1-bit units. (a) port mode this port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 2 mode register. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 2. (b) control mode this port functions as the data i/o pins, clock i/o pins, clock output pins, and buzzer output pins of the serial interface. pins p25 and p27 can be specified in the n-channel open drain by the port function control register (pf2) (only in the pd784216ay, 784218ay subseries). (i) si0, si1, so0, so1, sda0 these pins are the i/o pins for serial data in the serial interface. the sda0 pin is provided only for the pd784216ay, 784218ay subseries. (ii) sck0, sck1, scl0 these pins are the i/o pins for the serial clock of the serial interface. the scl0 pin is provided only for the pd784216ay, 784218ay subseries. (iii) rxd1, txd1 these pins are the i/o pins for serial data in the asynchronous serial interface. (iv) asck1 this is the i/o pin for the baud rate clock of the asynchronous serial interface. (v) pcl this is the clock output pin. (vi) buz this is the buzzer output pin. 51 chapter 2 pin functions user s manual u13570ej3v0ud (4) p30 to p37 (port 3) this port is an 8-bit i/o port. in addition to being an i/o port, this port has the timer i/o function and the external access status output function. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 3 mode register. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 3. (b) control mode the port functions as timer i/o and external access status output. (i) ti00 this is the external clock input pin to the 16-bit timer/counter. (ii) ti01 this is the capture trigger signal input pin to capture/compare register 00. (iii) ti1, ti2 these are the external clock input pins to the 8-bit timer/counter. (iv) to0 to to2 these are timer output pins. (v) exa this is the external access status output pin. the exa pin is provided only for the pd784218a, 784218ay subseries. (5) p40 to p47 (port 4) this is an 8-bit i/o port. in addition to being an i/o port, this port has the address/data bus function. led can be driven directly. the following operating modes are selectable in 1-bit units. (a) port mode this port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 4 mode register. when used as an input port, pull-up resistors can be connected in 8-bit units with bit 4 of the pull-up resistor option register (puo4). (b) control mode the port functions as the low-order address/data bus pins (ad0 to ad7) when in the external memory expansion mode. if puo4 = 1, pull-up resistors can be connected. 52 chapter 2 pin functions user s manual u13570ej3v0ud (6) p50 to p57 (port 5) this port is an 8-bit i/o port. in addition to being an i/o port, it has the address bus function. led can be driven directly. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 5 mode register. when used as an input port, pull-up resistors can be connected in 8-bit units with bit 5 of the pull-up resistor option register (puo5). (b) control mode the port functions as the middle-order address bus pins (a8 to a15) when in the external memory expansion mode. if puo5 = 1, pull-up resistors can be connected. (7) p60 to p67 (port 6) this port is an 8-bit i/o port. in addition to being an i/o port, this port has the address bus function and control function when in the external memory expansion mode. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 6 mode register. when used as an input port, pull-up resistors can be connected in 8-bit units with bit 6 of the pull-up resistor option register (puo6). (b) control mode p60 to p63 function as the high-order address bus pins (a16 to a19) in the external memory expansion mode. p64 to p67 function as the control signal output pins (rd, wr, wait, astb) in the external memory expansion mode. if puo6 = 1 in the external memory expansion mode, the pull-up resistors can be connected. caution when external waits are not used during the external memory expansion mode, p66 can be used as an i/o port. 53 chapter 2 pin functions user s manual u13570ej3v0ud (8) p70 to p72 (port 7) this is a 3-bit i/o port. in addition to being an i/o port, this port has the data i/o and clock i/o functions of the serial interface. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as a 3-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 7 mode register. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 7. (b) control mode the port functions as data i/o and clock i/o of the serial interface. (i) si2, so2 these are the i/o pins for serial data of the serial interface. (ii) sck2 this is the i/o pin for the serial clock in the serial interface. (iii) rxd2, txd2 these are the serial data i/o pins of the asynchronous serial interface. (iv) asck2 this is baud rate clock input pin of the asynchronous serial interface. (9) p80 to p87 (port 8) this port is an 8-bit i/o port. in addition to being an i/o port, this port has the address bus function. by detecting the falling edge, the interrupt control flag (krif) can be set to 1. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 8 mode register. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 8. (b) control mode the port functions as the low-order address bus pins (a0 to a7) when in the external memory expansion mode. if pu8n = 1 (n = 0 to 7), pull-up resistors can be connected. 54 chapter 2 pin functions user s manual u13570ej3v0ud (10) p90 to p95 (port 9) this port is a 6-bit i/o port. led can be driven directly. it can be specified as input port or output port in 1-bit units using the port 9 mode register. this is the n-channel open drain medium voltage i/o port. it does not have on-chip pull-up resistors. (11) p100 to p103 (port 10) this port is a 4-bit i/o port. in addition to being an i/o port, this port has the timer i/o function. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as a 4-bit i/o port. it can be specified as input port or output port in 1-bit units. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 10. (b) control mode the port functions as the timer i/o port. (i) ti5 to ti8 these are the external clock input pins for the 8-bit timer/counter. (ii) to5 to to8 these are the timer output pins. (12) p120 to p127 (port 12) this port is an 8-bit i/o port. in addition to being an i/o port, this port has the real-time output port function. the following operating modes are selectable in 1-bit units. (a) port mode the port functions as an 8-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 12 mode register. regardless of whether input or output mode is specified, pull-up resistors can be connected in 1-bit units using pull-up resistor option register 12. (b) control mode the port functions as a real-time output port (rtp0 to rtp7) that outputs data synchronized with a trigger. the pins specified as the real-time output port are read as 0. 55 chapter 2 pin functions user s manual u13570ej3v0ud (13) p130, p131 (port 13) this port is a 2-bit i/o port. in addition to being an i/o port, this port has the analog output function for the d/a converter. the following operating modes can be specified in 2-bit units. (a) port mode the port functions as a 2-bit i/o port. it can be specified as input port or output port in 1-bit units using the port 13 mode register. it does not have on-chip pull-up resistors. (b) control mode the port functions as the analog outputs (ano0, ano1) for the d/a converter. the values are undefined when the pins specified as analog output are read. caution if only one channel is used to the d/a converter when av ref1 < v dd , either of the following should be implemented for the pins that are not used as the analog output. set 1 (input mode) for the port mode register (pm13 ) and connect to v ss . set 0 (output mode) for the port mode register (pm13 ). set the output latch to 0 and output a low level. (14) av ref0 this is the reference voltage input pin for the a/d converter. if the a/d converter is not used, connect to v ss . (15) av ref1 this is the reference voltage input pin for the d/a converter. if the d/a converter is not used, connect to v dd . (16) av dd this is the analog voltage supply pin for the a/d converter. even if the a/d converter is not used, always use this pin at the same potential as v dd pin. (17) av ss this is the ground potential pin for the a/d converter. even if the a/d converter is not used, always use this pin at the same potential as v ss pin. (18) reset this is the active low system reset input pin. (19) x1, x2 these are the crystal oscillator connection pins for main system clock oscillation. when an external clock is supplied, input this clock signal to x1, and its inverted signal to x2. (20) xt1, xt2 these are the crystal oscillator connection pins for subsystem clock oscillation. when an external clock is supplied, input this clock signal to xt1, and its inverted signal to xt2. 56 chapter 2 pin functions user s manual u13570ej3v0ud (21) v dd this is the positive voltage supply pin. (22) v ss this is the ground potential pin. (23) v pp ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay only) this is the high-voltage application pin when setting the flash memory programming mode and writing or verifying the program. in the normal operating mode, connect directly to v ss or via a pull-down resistor. connect a pull-down resistor to the v pp pin in a system where the internal flash memory is rewritten on board. for the pull-down connection, use of a resistor with a resistance between 470 ? and 10 k ? is recommended. (24) test connect directly to v ss or via a pull-down resistor. for the pull-down connection, use of a resistor with a resistance between 470 ? and 10 k ? is recommended. 57 chapter 2 pin functions user s manual u13570ej3v0ud 2.3 pin i/o circuit and handling of unused pins table 2-1 shows the i/o circuit type for the pins and how to handle unused pins. see figure 2-1 for each type of i/o circuit. table 2-1. i/o circuit type for each pin and handling unused pins (1/2) pin symbol i/o circuit type i/o recommended connection when unused p00/intp0 8-n i/o input: connect to v ss individually via a resistor. p01/intp1 output: leave open. p02/intp2/nmi p03/intp3 to p06/intp6 p10/ani0 to p17/ani7 9 input connect to v ss or v dd . p20/rxd1/si1 10-k i/o input: connect to v ss individually via a resistor. p21/txd1/so1 10-l output: leave open. p22/asck1/sck1 10-k p23/pcl 10-l p24/buz p25/sda0 note /si0 10-k p26/so0 10-l p27/scl0 note /sck0 10-k p30/to0 to p32/to2 12-e p33/ti1, p34/ti2 8-n p35/ti00, p36/ti01 10-m p37/exa 12-e p40/ad0 to p47/ad7 5-a p50/a8 to p57/a15 p60/a16 to p63/a19 p64/rd p64/wr p66/wait p67/astb p70/rxd2/si2 8-n p71/txd2/so2 10-m p72/asck2/sck2 8-n p80/a0 to p87/a7 12-e p90 to p95 13-d note the sda0 and scl0 pins are provided only for the pd784216ay, 784218ay subseries. 58 chapter 2 pin functions user s manual u13570ej3v0ud table 2-1. i/o circuit type for each pin and handling unused pins (2/2) pin symbol i/o circuit type i/o recommended connection when unused p100/ti5/to5 8-n i/o input: connect to v ss individually via a resistor. p101/ti6/to6 output: leave open. p102/ti7/to7 p103/ti8/to8 p120/rtp0 to p127/rtp7 12-e p130/ano0, p131/ano1 12-f reset 12-g input xt1 16 connect to v ss . xt2 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . test/v pp note connect directly to v ss or via a pull-down resistor. for the pull- down connection, use of a resistor with a resistance between 470 ? and 10 k ? is recommended. note the v pp pin is provided only for the pd78f4216a, 78f4218a, 78f4216ay, and 78f4218ay. remark the type numbers are unified among the 78k series, so they are not always serial within each product (there are some circuits that are not incorporated). 59 chapter 2 pin functions user s manual u13570ej3v0ud figure 2-1. pin i/o circuit (1/2) type 2-g in schmitt-triggered input with hysteresis characteristics type 5-a pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch type 8-n pullup enable data output disable v dd p-ch v dd p-ch in/out n-ch type 9 pullup enable data open drain output disable v dd p-ch v dd p-ch in/out n-ch type 10-k pullup enable data open drain output disable output disable v dd p-ch v dd p-ch in/out n-ch type 10-l pullup enable data v dd p-ch v dd p-ch in/out n-ch type 10-m type 12-e pullup enable data output disable input enable analog output voltage v dd p-ch v dd p-ch in/out n-ch p-ch n-ch in comparator + ? 60 chapter 2 pin functions user s manual u13570ej3v0ud figure 2-1. pin i/o circuit (2/2) type 12-f type 13-d type 16 data output disable in/out n-ch middle-voltage input buffer p-ch v dd rd data output disable p-ch in/out v dd n-ch input enable p-ch n-ch analog output voltage p-ch feedback cut-off xt1 xt2 61 user s manual u13570ej3v0ud chapter 3 cpu architecture 3.1 memory space the pd784218a can access a 1 mb space. the mapping of the internal data area (special function register and internal ram) differs depending on the location instruction. the location instruction must always be executed after releasing a reset and cannot be used more than once. the program after releasing a reset must be as follows. rstvct cseg at 0 dw rststrt initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn 62 chapter 3 cpu architecture user s manual u13570ej3v0ud (1) when location 0h instruction is executed ? ? ? ? ? internal memory the internal data area and internal rom area are mapped as follows. part number internal data area internal rom area pd784214a, 0f100h to 0ffffh 00000h to 0f0ffh pd784214ay 10000h to 17fffh pd784215a, 0eb00h to 0ffffh 00000h to 0eaffh pd784215ay 10000h to 1ffffh pd784216a, 0df00h to 0ffffh 00000h to 0deffh pd784216ay 10000h to 1ffffh pd784217a, 0cd00h to 0ffffh 00000h to 0ccffh pd784217ay 10000h to 2ffffh pd784218a, 00000h to 0ccffh pd784218ay 10000h to 3ffffh caution the following areas that overlap the internal data area of the internal rom cannot be used when the location 0h instruction is executed. part number internal data area pd784214a, 0f100h to 0ffffh (3,840 bytes) pd784214ay pd784215a, 0eb00h to 0ffffh (5,376 bytes) pd784215ay pd784216a, 0df00h to 0ffffh (8,448 bytes) pd784216ay pd784217a, 0cd00h to 0ffffh (13,056 bytes) pd784217ay pd784218a, pd784218ay ? ? ? ? ? external memory the external memory is accessed in external memory expansion mode. 63 chapter 3 cpu architecture user s manual u13570ej3v0ud (2) when location 0fh instruction is executed ? ? ? ? ? internal memory the internal data area and internal rom area are mapped as follows. part number internal data area internal rom area pd784214a, ff100h to fffffh 00000h to 17fffh pd784214ay pd784215a, feb00h to fffffh 00000h to 1ffffh pd784215ay pd784216a, fdf00h to fffffh 00000h to 1ffffh pd784216ay pd784217a, fcd00h to fffffh 00000h to 2ffffh pd784217ay pd784218a, 00000h to 3ffffh pd784218ay ? ? ? ? ? external memory the external memory is accessed in external memory expansion mode. 64 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-1. pd784214a memory map notes 1. access in the external memory expansion mode. 2. the 3,840 bytes in this area can be used as the internal rom only when the location 0fh instruction is executed. 3. location 0h instruction execution: 94,464 bytes, location 0fh instruction execution: 98,304 bytes 4. this is the base area and the entry area on resets or interrupts. however, the internal ram is excluded on reset. internal rom (61,696 bytes) (256 bytes) special function register (sfr) internal ram (3,584 bytes) external memory note 1 (928 kb) note 1 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (3,072 bytes) callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (3,584 bytes) external memory note 1 (980,736 bytes) (256 bytes) internal rom (96 kb) location 0h instruction execution special function register (sfr) note 1 location 0fh instruction execution h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 1 f 0 h f f 0 f 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h b 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 1 f 0 h f f f 7 1 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h b 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 1 f f h 0 0 0 0 0 h f f f 7 1 h 0 0 0 8 1 h f f 0 f f h 0 0 1 f f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 note 2 h f f f 7 1 h 0 0 0 8 1 h f f f 7 1 internal rom (32,768 bytes) h f f 0 f 0 h 0 0 0 0 1 65 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-2. pd784215a memory map notes 1. access in the external memory expansion mode. 2. the 5,376 bytes in this area can be used as the internal rom only when the location 0fh instruction is executed. 3. location 0h instruction execution: 125,696 bytes, location 0fh instruction execution: 131,072 bytes 4. this is the base area and the entry area on resets or interrupts. however, the internal ram is excluded on reset. internal rom (60,160 bytes) (256 bytes) special function register (sfr) internal ram (5,120 bytes) external memory note 1 (896 kb) note 1 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (4,608 bytes) callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (5,120 bytes) external memory note 1 (912,128 bytes) (256 bytes) internal rom (128 kb) location 0h instruction execution special function register (sfr) note 1 location 0fh instruction execution h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 b e 0 h f f a e 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h b 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 b e 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h b 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 b e f h 0 0 0 0 0 h f f f f 1 h 0 0 0 0 2 h f f a e f h 0 0 b e f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 h f f f f 1 internal rom (65,536 bytes) h 0 0 0 0 2 h f f f f 1 h f f f f 1 note 2 h f f a e 0 h 0 0 0 0 1 66 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-3. pd784216a memory map notes 1. access in the external memory expansion mode. 2. the 8,448 bytes in this area can be used as the internal rom only when the location 0fh instruction is executed. 3. location 0h instruction execution: 122,624 bytes, location 0fh instruction execution: 131,072 bytes 4. this is the base area and the entry area on resets or interrupts. however, the internal ram is excluded on reset. internal rom (57,088 bytes) (256 bytes) special function register (sfr) internal ram (8,192 bytes) external memory note 1 (896 kb) note 1 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (7,680 bytes) callf entry area (2 kb) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (8,192 bytes) external memory note 1 (909,056 bytes) (256 bytes) internal rom (128 kb) location 0h instruction execution special function register (sfr) note 1 location 0fh instruction execution h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 f d 0 h f f e d 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h b 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 f d 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h b 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 f d f h 0 0 0 0 0 h f f f f 1 h 0 0 0 0 2 h f f e d f h 0 0 f d f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 h 0 0 0 0 2 h f f f f 1 h f f f f 1 internal rom (65,536 bytes) h f f f f 1 note 2 h f f e d 0 h 0 0 0 0 1 67 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-4. pd784217a memory map notes 1. access in the external memory expansion mode. 2. the 13,056 bytes in this area can be used as the internal rom only when the location 0fh instruction is executed. 3. location 0h instruction execution: 183,552 bytes; location 0fh instruction execution: 196,608 bytes 4. this is the base area and the entry area upon reset or interrupt. however, the internal ram is excluded for reset. (256 bytes) special function register (sfr) internal rom (52,480 bytes) internal ram (12,800 bytes) note 1 note 4 note 2 note 4 note 1 note 3 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (12,288 bytes) callf entry area (2 kb) program/data area callt table area (64 bytes) vector table area (64 bytes) internal ram (12,800 bytes) external memory note 1 (838,912 bytes) (256 bytes) internal rom (192 kb) location 0h instruction execution special function register (sfr) location 0fh instruction execution fffffh internal rom (131,072 bytes) external memory note 1 (832 kb) 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 30000h 2ffffh 0feffh ffeffh ffe80h ffe7fh 0fe3bh 0fe06h 0cd00h 0ccffh 00000h 00000h 0fe80h 0fe7fh 0fd00h 0fcffh ffe3bh ffe06h fcd00h ffd00h ffcffh 01000h 00fffh 00800h 007ffh 00080h 0007fh 00040h 0003fh 2ffffh 10000h 2ffffh 30000h 2ffffh 0cd00h 0ccffh 00000h fffffh fffdfh fffd0h fff00h ffeffh fcd00h fccffh 68 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-5. pd784218a memory map notes 1. access in the external memory expansion mode. 2. the 13,056 bytes in this area can be used as the internal rom only when the location 0fh instruction is executed. 3. location 0h instruction execution: 249,088 bytes; location 0fh instruction execution: 262,144 bytes 4. this is the base area and the entry area upon reset or interrupt. however, the internal ram is excluded for reset. (256 bytes) special function register (sfr) internal rom (52,480 bytes) internal ram (12,800 bytes) note 1 note 4 note 2 note 4 note 1 note 3 general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (12,288 bytes) callf entry area (2 kb) program/data area callt table area (64 bytes) vectored-table area (64 bytes) internal ram (12,800 bytes) external memory note 1 (773,376 bytes) (256 bytes) internal rom (256 kb) location 0h instruction execution special function register (sfr) location 0fh instruction execution fffffh internal rom (196,608 bytes) external memory note 1 (768 kb) 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 40000h 3ffffh 0feffh ffeffh ffe80h ffe7fh 0fe3bh 0fe06h 0cd00h 0ccffh 00000h 00000h 0fe80h 0fe7fh 0fd00h 0fcffh ffe3bh ffe06h fcd00h ffd00h ffcffh 01000h 00fffh 00800h 007ffh 00080h 0007fh 00040h 0003fh 3ffffh 10000h 3ffffh 40000h 3ffffh 0cd00h 0ccffh 00000h fffffh fffdfh fffd0h fff00h ffeffh fcd00h fccffh 69 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.2 internal rom area the following versions in the 70 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.3 base area the area from 0 to ffffh becomes the base area. the base area is the target in the following uses. reset entry address interrupt entry address entry address for callt instruction 16-bit immediate addressing mode (instruction address addressing) 16-bit direct addressing mode 16-bit register addressing mode (instruction address addressing) 16-bit register indirect addressing mode short direct 16-bit memory indirect addressing mode the vector table area, callt instruction table area, and callf instruction entry area are allocated in the base area. when the location 0h instruction is executed, the internal data area is placed in the base area. be aware that the program cannot be fetched from the internal high-speed ram area and special function register (sfr) area in the internal data area. also, use the data in the internal ram area after initialization. 71 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.3.1 vector table area the 64-byte area from 00000h to 0003fh is reserved as the vector table area. the program start addresses for branching by interrupt requests and reset input are stored in the vector table area. if context switching is used by each interrupt, the register bank number of the switch destination is stored. the portion that is not used as the vector table can be used as program memory or data memory. the values that can be written in the vector table are a 16-bit values. therefore, branching can only be to the base area. table 3-1. vector table address interrupt source vector table address interrupt source vector table address brk instruction 003eh intst1 001ch trap0 (operand error) 003ch intser2 001eh nmi 0002h insr2 0020h intwdt (non-maskable) 0004h intcsi2 intwdt (maskable) 0006h intst2 0022h intp0 0008h inttm3 0024h intp1 000ah inttm00 0026h intp2 000ch inttm01 0028h intp3 000eh inttm1 002ah intp4 0010h inttm2 002ch intp5 0012h intad 002eh intp6 0014h inttm5 0030h intiic0 note 0016h inttm6 0032h intcsi0 inttm7 0034h intser1 0018h inttm8 0036h intsr1 001ah intwt 0038h intcsi1 intkr 003ah note only in 72 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.3.2 callt instruction table area the 64 kb area from 00040h to 0007fh can store the subroutine entry addresses for the 1-byte call instruction (callt). in a callt instruction, this table is referenced and the base area address written in the table is branched to as the subroutine. since a callt instruction is a 1-byte instruction, many subroutine call descriptions in the program can be callt instructions, so the object size of the program can be reduced. since a maximum of 32 subroutine entry addresses can be described in the table, they should be registered in order from the most frequently described. when not used as the callt instruction table, the area can be used as normal program memory or data memory. 3.3.3 callf instruction entry area the area from 00800h to 00fffh can be called directly by subroutine via the 2-byte call instruction (callf). since a callf instruction is a 2-byte call instruction, compared to using the call instruction (3-byte or 4-byte) of a subroutine call directly, the object size can be reduced. when higher speed is required, describing subroutines directly in this area is effective. if decreasing the object size is required, this can be done by describing an unconditional branch (br) in this area and placing the actual subroutine outside this area. when a subroutine is called from five or more locations, reducing the object size is attempted. in this case, since only a 4-byte location for the br instruction is occupied in the callf entry area, the object size of many subroutines can be reduced. 73 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.4 internal data area the internal data area consists of the internal ram area and the special function register area (see figures 3- 1 and 3-2 ). for the final address of the internal data area, either 0ffffh (when executing the location 0h instruction) or fffffh (when executing the location 0fh instruction) can be selected by the location instruction. the address selection of the internal data area by this location 0h must be executed once immediately after a reset is released. once either of them is selected, the other cannot be selected. the program after a reset is released must be as shown in the example. if the internal data area and another area are allocated to the same address, the internal data area becomes the access target, and the other area cannot be accessed. example rstvct cseg at 0 dw rststrt initseg cseg base rststrt: location 0h ; or location 0fh movg sp, #stkbgn caution when the location 0h instruction is executed, the program after releasing the reset must not overlap the internal data area. in addition, make sure the entry address of the servicing routine for a non-maskable interrupt such as nmi does not overlap the internal data area. the entry area for a maskable interrupt must be initialized before referencing the internal data area. 74 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.4.1 internal ram area the table 3-2. internal ram area list internal ram internal ram area product name peripheral ram: pram internal high-speed ram: iram remark the addresses in the table are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h is added to the above values. 75 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-6 is the internal ram memory map. figure 3-6. internal ram memory map general-purpose register area macro service control word area available range for short direct addressing 1 available range for short direct addressing 2 internal high-speed ram peripheral ram 00feffh 00fe80h 00fe3bh 00fe06h 00fe00h 00fdffh 00fd20h 00fd1fh 00fd00h 00fcffh 00cd00h remark the addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h is added to the above values. 76 chapter 3 cpu architecture user s manual u13570ej3v0ud (1) internal high-speed ram (iram) the internal high-speed ram can be accessed at high speed. the short direct addressing mode can be used for high-speed access to fd20h to feffh. the two short direct addressing modes, short direct addressing 1 and short direct addressing 2, are available depending on the address of the target. both addressing modes have the same function. in some instructions, short direct addressing 2 has a shorter word length than short direct addressing 1. for details, refer to 78k/iv series user? manual ?instruction (u10905e) . a program cannot be fetched from iram. if a program is fetched from an address that is mapped for iram, cpu runaway occurs. the following areas are reserved for iram. general-purpose register area: fe80h to feffh macro service control word area: fe06h to fe3bh macro service channel area: fe00h to feffh (the address is set by a macro service control word.) when these areas do not use the reserved functions, they can be used as normal data memory. remark the addresses in this text are the addresses when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h is added to the values in this text. (2) peripheral ram (pram) the peripheral ram (pram) is used as normal program memory or data memory. when used as the program memory, the program must be written beforehand in the peripheral ram by a program. a program fetch from the peripheral ram is high speed because it can be executed in two clocks in 2-byte units. 77 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.4.2 special function register (sfr) area the special function register (sfr) of the on-chip peripheral hardware is mapped to the area from 0ff00h to 0ffffh (refer to figures 3-1 and 3-2 ). the area from 0ffd0h to 0ffdfh is mapped as the external sfr area. peripheral i/o externally connected can be accessed in the external memory expansion mode (set by the memory expansion mode register (mm)). caution in this area, do not access an address that is not mapped in sfr. if such an address is mistakenly accessed, the cpu may enter the deadlock state. the deadlock state is released only by reset input. remark the addresses in this text are the addresses only when the location 0h instruction is executed. if the location 0fh instruction is executed, 0f0000h is added to the values in the text. 3.4.3 external sfr area in the products of the 3.5 external memory space the external memory space is the memory space that can be accessed by setting the memory expansion mode register (mm). the program and table data can be stored and peripheral i/o devices can be assigned. 78 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.6 memory mapping of pd78f4216a and 78f4218a ims is a register that is set by software and is used to specify a part of the internal memory that is not to be used. by setting this register, the internal memory can be mapped identically to that of a mask rom version with a different internal memory (rom and ram) capacity. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to ffh. (1) pd78f4216a, 78f4216ay figure 3-7. internal memory size switching register (ims) format (1/2) address: 0fffch after reset: ffh w symbol 76543210 ims 1 1 rom1 rom0 1 1 ram1 ram0 rom1 rom0 internal rom capacity selections 0 0 48 kb 0 1 64 kb 1 0 96 kb 1 1 128 kb ram1 ram0 peripheral ram capacity selections 0 0 3,072 bytes 0 1 4,608 bytes 1 0 6,114 bytes 1 1 7,680 bytes cautions 1. ims is not provided in the mask rom versions ( pd784214a, 784215a, 784216a, 784214ay, 784215ay, and 784216ay). even if a write instruction is executed to ims in a mask rom version, the instruction will be invalid. 2. if the pd78f4216a or 78f4216ay is selected as the emulation cpu for an in-circuit emulator, the memory size is always the same as that of the pd784216a, ?fh? even if an instruction that writes an address of ims other than ffh is executed. table 3-3 shows the ims setting values to make the memory mapping the same as that of the mask rom versions. table 3-3. setting value of internal memory size switching register (ims) target mask rom version ims setting value 79 chapter 3 cpu architecture user s manual u13570ej3v0ud (2) pd78f4218a, 78f4218ay figure 3-7. internal memory size switching register (ims) format (2/2) address: 0fffch after reset: ffh w symbol 76543210 ims 1 1 rom1 rom0 1 1 ram1 ram0 rom1 rom0 internal rom capacity selections 0 0 64 kb 0 1 128 kb 1 0 192 kb 1 1 256 kb ram1 ram0 peripheral ram capacity selections 0 0 3,072 bytes 0 1 6,656 bytes 1 0 7,168 bytes 1 1 12,288 bytes cautions 1. ims is not provided in the mask rom versions ( pd784217a, 784218a, 784217ay, and 784218ay). even if a write instruction is executed to ims in a mask rom version, the instruction will be invalid. 2. if the pd78f4218a or 78f4218ay is selected as the emulation cpu for an in-circuit emulator, the memory size is always the same as that of the pd784218a, ?fh? even if an instruction that writes an address of ims other than ffh is executed. table 3-4 shows the ims setting values to make the memory mapping the same as that of the mask rom versions. table 3-4. setting value of internal memory size switching register (ims) target mask rom version ims setting value 80 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.7 control registers the control registers are the program counter (pc), program status word (psw), and stack pointer (sp). 3.7.1 program counter (pc) this is a 20-bit binary counter that holds the address information about the program to be executed next (see figure 3-8 ). usually, this counter is automatically incremented based on the number of bytes of the instruction to be fetched. when the instruction with branching is executed, the immediate data or register contents are set. reset input sets the 16-bit data at addresses 0 and 1 to the lower 16 bits of the pc, and 0000 to the higher four bits of the pc. figure 3-8. program counter (pc) format 19 0 pc 3.7.2 program status word (psw) the program status word (psw) is a 16-bit register that consists of various flags that are set and reset based on the result of the instruction execution. a read or write access is performed in higher 8-bit (pswh) and the lower 8-bit (pswl) units. in addition, bit manipulation instructions can manipulate each flag. the contents of the psw are automatically saved on the stack when a vectored interrupt request is accepted and when a brk instruction is executed, and are automatically restored when a reti or retb instruction is executed. when context switching is used, the contents are automatically saved to rp3, and automatically restored when a retcs or retcsb instruction is executed. reset input resets all of the bits to 0. be sure to write 0 in the bits indicated as 0 in figure 3-9. the contents of bits indicated as are undefined when read. 81 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-9. program status word (psw) format symbol 76543210 pswh uf rbs2 rbs1 rbs0 76543210 pswl s z rss ac ie p/v 0 cy each flag is described below. (1) carry flag (cy) this is the flag that stores the carry or borrow of an operation result. when a shift rotate instruction is executed, the value shifted out is stored. when a bit manipulation instruction is executed, this flag functions as the bit accumulator. the state of the cy flag can be tested by a conditional branch instruction. (2) parity/overflow flag (p/v) the p/v flag has the following two actions in accordance with the execution of the operation instruction. the state of the p/v flag can be tested by a conditional branch instruction. parity flag action if the results of executing the logical instructions, shift rotate instructions, and chkl and chkla instructions set the even number of bits to 1, the flag is set to 1. if the number of bits set to 1 is odd, the flag is reset to 0. however, for 16-bit shift instructions, only the lower 8 bits of the operation result are valid for the parity flag. overflow flag action the result of executing an arithmetic operation instruction sets the flag to 1 only if the result exceeds the numerical range expressed in two s complement. otherwise, the flag is reset to 0. specifically, the result of the exclusive or of the carry from the msb and the carry to the msb becomes the flag contents. for example, in 8-bit arithmetic operations, the two s complement range is from 80h ( 128) to 7fh (+127). if the operation result is out of this range, the flag is set to 1. if within this range, it is reset to 0. 82 chapter 3 cpu architecture user s manual u13570ej3v0ud example the action of the overflow flag when an 8-bit addition instruction is executed is described next. when 78h (+120) and 69h (+105) are added, the operation result becomes e1h (+225). since the upper limit of two s complement is exceeded, the p/v flag is set to 1. in a two s complement expression, e1h becomes 31. 78h (+120) = 0111 1000 +) 69h (+105) = +) 0110 1001 0 1110 0001 = 31 p/v = 1 s complement range, the p/v flag is reset to 0. fbh ( 5) = 1111 1011 +) f0h ( 16) = +) 1111 0000 1 1110 1011 = 21 p/v = 0 (3) interrupt request enable flag (ie) this flag controls the cpu interrupt request acceptance. if ie is 0, interrupts are disabled, and only non-maskable interrupts and unmasked macro services can be accepted. otherwise, everything is disabled. if ie is 1, the interrupt enable state is entered. enabling the acceptance of interrupt requests is controlled by the interrupt mask flags that correspond to each interrupt request and the priority of each interrupt. this flag is set to 1 by executing the ei instruction and is reset to 0 by executing the di instruction or accepting an interrupt. (4) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set to 1. otherwise, the flag is reset to 0. this flag is used when the adjba and adjbs instructions are executing. 83 chapter 3 cpu architecture user s manual u13570ej3v0ud (5) register set selection flag (rss) this flag sets the general-purpose registers that function as x, a, c, and b and the general-purpose register pairs (16 bits) that function as ax and bc. this flag is used to maintain compatibility with the 78k/iii series. always set this flag to 0 except when using a 78k/iii series program. (6) zero flag (z) this flag indicates that the operation result is 0. if the operation result is 0, this flag is set to 1. otherwise, it is reset to 0. the state of the z flag can be tested by conditional branch instructions. (7) sign flag (s) this flag indicates that the msb in the operation result is 1. the flag is set to 1 when the msb of the operation result is 1. if 0, the flag is reset to 0. the s flag state can be tested by the conditional branch instructions. (8) register bank selection flags (rbs0 to rbs2) this is the 3-bit flag that selects one of the eight register banks (register banks 0 to 7). (refer to table 3-5 .) three bit information that indicates the register bank selected by executing the sel rbn instruction is stored. table 3-5. register bank selection rbs2 rbs1 rbs0 set register bank 0 0 0 register bank 0 0 0 1 register bank 1 0 1 0 register bank 2 0 1 1 register bank 3 1 0 0 register bank 4 1 0 1 register bank 5 1 1 0 register bank 6 1 1 1 register bank 7 (9) user flag (uf) this flag is set and reset by a user program and can be used in program control. 84 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.7.3 using rss bit basically, always use with the rss bit fixed at 0. the following descriptions discuss using a 78k/iii series program and a program that sets the rss bit to 1. reading is not necessary if the rss bit is fixed at 0. the rss bit enables the functions in a (r1), x (r0), b (r3), c (r2), ax (rp0), and bc (rp1) to also be used in registers r4 to r7 (rp2, rp3). when this bit is effectively used, efficient programs in terms of program size and program execution can be written. sometimes, however, unexpected problems arise if used carelessly. consequently, always set the rss bit to 0. use with the rss bit set to 1 only when 78k/iii series programs will be used. by setting the rss bit to 0 in all programs, writing and debugging programs become more efficient. even if a program where the rss bit is set to 1 is used, when possible, it is recommended to use the program after modifying the program so that the rss bit is not set to 1. (1) using the rss bit registers used in instructions where the a, x, b, c, and ax registers are directly described in the operand column of the operation list (see 29.2 ) registers that are implicitly specified in instructions that use the a, ax, b, and c registers by implied addressing registers that are used in addressing in instructions that use the a, b, and c registers in indexed addressing and based indexed addressing the registers used in these cases are switched in the following ways by the rss bit. when rss = 0 a when rss = 1 a 85 chapter 3 cpu architecture user s manual u13570ej3v0ud the registers used in other cases always become the same registers regardless of the contents of the rss bit. for registers a, x, b, c, ax, and bc in nec electronics assembler ra78k4, instruction code is generated for any register described by name or for registers set by an rss pseudo instruction in the assembler. when the rss bit is set or reset, always specify an rss pseudo instruction immediately before (or immediately after) that instruction (see the following examples). 86 chapter 3 cpu architecture user s manual u13570ej3v0ud if a, x, b, c, ax, or bc is described in an instruction that specifies r, r , rp, or rp in the operand column, the a, x, b, c, ax, or bc instruction code generates the instruction code that specifies the following registers based on the operand of the rss pseudo instruction in ra78k4. register rss = 0 rss = 1 ar1r5 xr0r4 br3r7 cr2r6 ax rp0 rp2 bc rp1 rp3 if r0 to r7 and rp0 to rp4 are specified in r, r , rp, and rp in the operand column, an instruction code that conforms to the specification is output (instruction code that directly describes a or ax in the operand column is not output). the a, b, and c registers that are used in indexed addressing and based indexed addressing cannot be described as r1, r3, r2, or r5, r7, r6. (3) usage cautions switching the rss bit obtains the same effect as holding two register sets. however, be careful and write the program so that implicit descriptions in the program and dynamically changing the rss bit during program execution always agree. also, since a program with rss = 1 cannot be used in a program that uses context switching, the portability of the program becomes poor. furthermore, since different registers having the same name are used, the readability of the program worsens, and debugging becomes difficult. therefore, when rss = 1 must be used, write the program while taking these problems into consideration. a register that does not have the rss bit set can be accessed by specifying the absolute name. 87 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.7.4 stack pointer (sp) the 24-bit register saves the starting address of the stack (lifo: 00000h to ffffffh) (refer to figure 3-10 ). the stack is used for addressing during subroutine processing or interrupt servicing. always set the most-significant four bits to zero. the contents of the sp are decremented before writing to the stack area and incremented after reading from the stack (refer to figures 3-11 and 3-12 ). sp is accessed by special instructions. since the sp contents become undefined when reset is input, always initialize the sp from the initialization program immediately after clearing the reset (before accepting a subroutine call or interrupt). example initializing sp movg sp, #0fee0h ; sp figure 3-10. stack pointer (sp) format 23 0 sp 88 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-11. data saved to stack r7 r6 r5 r4 a x sp 1 2 3 4 5 6 sp 6 rp3 rp2 ax pswl pc15 to pc8 pc7 to pc0 sp 1 2 3 4 sp 4 pswh 7 to pswh 4 pc19 to pc16 pc15 to pc8 pc7 to pc0 sp 1 2 3 sp 3 sp 1 2 3 sp 3 sp 1 2 sp 2 sp 1 2 sp 2 sp 1 sp 1 pc19 to pc16 high byte pswl undefined undefined pswh 7 to pswh 4 high byte low byte middle byte low byte push sfr instruction stack push sfrp instruction stack push psw instruction stack call, callf, callt instructions stack vectored interrupt stack push post, pushu post instructions (for push ax, rp2, rp3) stack push rg instruction stack 89 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-12. data restored from stack note this 4-bit data is ignored. r7 r6 r5 r4 a x rp3 rp2 ax pswl pc15 to pc8 pc7 to pc0 pswh 7 to pswh 4 pc19 to pc16 pc15 to pc8 pc7 to pc0 pc19 to pc16 pswl pswh 7 to pswh 4 sp note pop psw instruction stack pop rg instruction stack ret instruction stack reti, retb instructions stack pop post, popu post instructions (for pop ax, rp2, rp3) stack high byte low byte high byte middle byte low byte sp note 90 chapter 3 cpu architecture user s manual u13570ej3v0ud cautions 1. in stack addressing, the entire 1 mb space can be accessed, but the stack cannot be guaranteed in the sfr area and internal rom area. 2. the stack pointer (sp) becomes undefined when reset is input. in addition, even when sp is in the undefined state, non-maskable interrupts can be accepted. therefore, when the sp is in the undefined state immediately after the reset is cleared and a request for a non- maskable interrupt is generated, unexpected actions sometimes occur. to avoid this danger, always specify the following in the program after clearing a reset. rstvct cseg at 0 dw rststrt initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn 91 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.8 general-purpose registers 3.8.1 configuration there are sixteen 8-bit general-purpose registers. in addition, two 8-bit general-purpose registers can be combined and used as a 16-bit general-purpose register. furthermore, four of the 16-bit general-purpose registers are combined with an 8-bit register for address expansion and used as a 24-bit address specification register. the general-purpose registers except for the v, u, t, and w registers for address expansion are mapped to the internal ram. these register sets provide eight banks and can be switched by the software or context switching. reset input selects register bank 0. in addition, the register banks that are used in an executing program can be verified by reading the register bank selection flags (rbs0, rbs1, rbs2) in the psw. figure 3-13. general-purpose register format 7070 a (r1) x (r0) ax(rp0) b (r3) c (r2) bc (rp1) r5 r4 rp2 r7 r6 rp3 r9 r8 vp (rp4) v vvp (rg4) r11 r10 up (rp5) u uup (rg5) d (r13) e (r12) de (rp6) t tde (rg6) h (r15) l (r14) hl (rp7) w whl (rg7) 0 23 15 8 banks remark the parentheses enclose the absolute names. 92 chapter 3 cpu architecture user s manual u13570ej3v0ud figure 3-14. general-purpose register addresses operation in register bank 2 operation in original register bank ? ? ? ? ? 93 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.8.2 functions in addition to being manipulatable in 8-bit units, general-purpose registers can be a pair of two 8-bit registers and be manipulated in 16-bit units. also four of the 16-bit registers can be combined with the 8-bit register for address expansion and manipulated in 24-bit units. each register can generally be used as the temporary storage for the operation result or the operand of the operation instruction between registers. the area from 0fe80h to 0feffh (during location 0h instruction execution, or the 0ffe80h to 0ffeffh during location 0fh instruction execution) can be accessed by specifying an address as normal data memory whether or not it is used as the general-purpose register area. since there are eight register banks in the 78k/iv series, efficient programs can be written by suitably using the register banks in normal processing or interrupt processing. each register has the unique functions shown below. a (r1): this register is primarily for 8-bit data transfers and operation processing. it can be combined with all of the addressing modes for 8-bit data. this register can be used to store bit data. this register can be used as a register that stores the offset value during indexed addressing or based indexed addressing. x (r0): this register can store bit data. ax (rp0): this register is primarily for 16-bit data transfers and operation results. it can be combined with all of the addressing modes for 16-bit data. axde: when a divux, macw, or macsw instruction is executed, this register can be used to store 32-bit data. b (r3): this register functions as a loop counter and can be used by the dbnz instruction. this register can store the offset in indexed addressing and based indexed addressing. this register is used as the data pointer in a macw or macsw instruction. c (r2): this register functions as a loop counter and can be used by the dbnz instruction. this register can store the offset in based indexed addressing. this register is used as the counter in string and sacw instructions. this register is used as the data pointer in a macw or macsw instruction. rp2: when context switching is used, this register saves the low-order 16 bits of the program counter (pc). rp3: when context switching is used, this register saves the most significant 4 bits of the program counter (pc) and the program status word (psw) (except bits 0 to 3 in pswh). 94 chapter 3 cpu architecture user s manual u13570ej3v0ud vvp (rg4): this register functions as a pointer and specifies the base address in register indirect addressing, based addressing, and based indexed addressing. uup (rg5): this register functions as a user stack pointer and implements another stack separate from the system stack by the pushu and popu instructions. this register functions as a pointer and specifies the base address in register indirect addressing and based addressing. de (rp6), hl (rp7): this register stores the offset during indexed addressing and based indexed addressing. tde (rg6): this register functions as a pointer and specifies the base address in register indirect addressing and based addressing. this register functions as a pointer in string and sacw instructions. whl (rg7): this register primarily performs 24-bit data transfers and operation processing. this register functions as a pointer and specifies the base address in register indirect addressing and based addressing. this functions as a pointer in string and sacw instructions. 95 chapter 3 cpu architecture user s manual u13570ej3v0ud in addition to its function name (x, a, c, b, e, d, l, h, ax, bc, vp, up, de, hl, vvp, uup, tde, whl) that emphasizes its unique function, each register can be described by its absolute name (r0 to r15, rp0 to rp7, rg4 to rg7). for the correspondence, refer to table 3-6 . table 3-6. correspondence between function names and absolute names (a) 8-bit registers absolute name function name rss = 0 rss = 1 note r0 x r1 a r2 c r3 b r4 x r5 a r6 c r7 b r8 r9 r10 r11 r12 e e r13 d d r14 l l r15 h h note use rss = 1 only when a 78k/iii series program is used. remark r8 to r11 do not have function names. (b) 16-bit registers absolute name function name rss = 0 rss = 1 note rp0 ax rp1 bc rp2 ax rp3 bc rp4 vp vp rp5 up up rp6 de de rp7 hl hl (c) 24-bit registers absolute name function name rg4 vvp rg5 uup rg6 tde rg7 whl 96 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.9 special function registers (sfrs) these registers are assigned special functions such as the mode register and control register of the on-chip peripheral hardware and are mapped to the 256-byte area from 0ff00h to 0ffffh note . note these are the addresses when the location 0h instruction is executed. they are fff00h to fffffh when the location 0fh instruction is executed. caution in this area, do not access an address that is not allocated by an sfr. if erroneously accessed, the symbol this symbol indicates the on-chip sfr. in nec electronics assembler ra78k4, this is a reserved word. in c compiler cc78k4, it can be used as an sfr variable by a #pragma sfr directive. r/w indicates whether the corresponding sfr can be read or written. r/w: can read/write r: read only w: write only bit manipulation unit when the corresponding sfr is manipulated, the appropriate bit manipulation unit is indicated. an sfr that can manipulate 16 bits can be described in the sfrp operand. if specified by an address, an even address is described. an sfr that can manipulate one bit can be described in bit manipulation instructions. after reset indicates the state of each register when reset is input. 97 chapter 3 cpu architecture user s manual u13570ej3v0ud table 3-7. special function register (sfr) list (1/5) address name of special function register (sfr) symbol r/w bit manipulation unit after reset note 1 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w 00h note 2 0ff01h port 1 p1 r 0ff02h port 2 p2 r/w 0ff03h port 3 p3 0ff04h port 4 p4 0ff05h port 5 p5 0ff06h port 6 p6 0ff07h port 7 p7 0ff08h port 8 p8 0ff09h port 9 p9 0ff0ah port 10 p10 0ff0ch port 12 p12 0ff0dh port 13 p13 0ff10h 16-bit timer counter tm0 r 0000h 0ff11h 0ff12h 16-bit capture/compare register 00 cr00 r/w 0ff13h (16-bit timer/event counter) 0ff14h 16-bit capture/compare register 01 cr01 0ff15h (16-bit timer/event counter) 0ff16h capture/compare control register 0 crc0 00h 0ff18h 16-bit timer mode control register tmc0 0ff1ah 16-bit timer output control register toc0 0ff1ch prescaler mode register 0 prm0 0ff20h port 0 mode register pm0 ffh 0ff22h port 2 mode register pm2 0ff23h port 3 mode register pm3 0ff24h port 4 mode register pm4 0ff25h port 5 mode register pm5 0ff26h port 6 mode register pm6 0ff27h port 7 mode register pm7 0ff28h port 8 mode register pm8 0ff29h port 9 mode register pm9 0ff2ah port 10 mode register pm10 notes 1. these values are when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to these values. 2. since each port is initialized in the input mode by a reset, in fact, 00h is not read out. the output latch is initialized to 0. 98 chapter 3 cpu architecture user s manual u13570ej3v0ud table 3-7. special function register (sfr) list (2/5) address name of special function register (sfr) symbol r/w bit manipulation unit after reset note 1 1 bit 8 bits 16 bits 0ff2ch port 12 mode register pm12 r/w ffh 0ff2dh port 13 mode register pm13 0ff30h pull-up resistor option register 0 pu0 00h 0ff32h pull-up resistor option register 2 pu2 0ff33h pull-up resistor option register 3 pu3 0ff37h pull-up resistor option register 7 pu7 0ff38h pull-up resistor option register 8 pu8 0ff3ah pull-up resistor option register 10 pu10 0ff3ch pull-up resistor option register 12 pu12 0ff40h clock output control register cks 0ff42h port function control register note 2 pf2 0ff4eh pull-up resistor option register puo 0ff50h 8-bit timer counter 1 tm1 tw1w r 0000h 0ff51h 8-bit timer counter 2 tm2 0ff52h compare register 10 (8-bit timer/event counter 1) cr10 cr1w r/w 0ff53h compare register 20 (8-bit timer/event counter 2) cr20 0ff54h 8-bit timer mode control register 1 tmc1 tmc1w 0ff55h 8-bit timer mode control register 2 tmc2 0ff56h prescaler mode register 1 prm1 prm1w 0ff57h prescaler mode register 2 prm2 0ff60h 8-bit timer counter 5 tm5 tm5w r 0ff61h 8-bit timer counter 6 tm6 0ff62h 8-bit timer counter 7 tm7 tm7w 0ff63h 8-bit timer counter 8 tm8 0ff64h compare register 50 (8-bit timer/event counter 5) cr50 cr5w r/w 0ff65h compare register 60 (8-bit timer/event counter 6) cr60 0ff66h compare register 70 (8-bit timer/event counter 7) cr70 cr7w 0ff67h compare register 80 (8-bit timer/event counter 8) cr80 0ff68h 8-bit timer mode control register 5 tmc5 tmc5w 0ff69h 8-bit timer mode control register 6 tmc6 0ff6ah 8-bit timer mode control register 7 tmc7 tmc7w 0ff6bh 8-bit timer mode control register 8 tmc8 0ff6ch prescaler mode register 5 prm5 prm5w 0ff6dh prescaler mode register 6 prm6 notes 1. these values are when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to these values. 2. only in the 99 chapter 3 cpu architecture user s manual u13570ej3v0ud table 3-7. special function register (sfr) list (3/5) address name of special function register (sfr) symbol r/w bit manipulation unit after reset note 1 1 bit 8 bits 16 bits 0ff6eh prescaler mode register 7 prm7 prm7w r/w 0000h 0ff6fh prescaler mode register 8 prm8 0ff70h asynchronous serial interface mode register 1 asim1 00h 0ff71h asynchronous serial interface mode register 2 asim2 0ff72h asynchronous serial interface status register 1 asis1 r 0ff73h asynchronous serial interface status register 2 asis2 0ff74h transmission shift register 1 txs1 w ffh reception buffer register 1 rxb1 r 0ff75h transmission shift register 2 txs2 w reception buffer register 2 rxb2 r 0ff76h baud rate generator control register 1 brgc1 r/w 00h 0ff77h baud rate generator control register 2 brgc2 0ff7ah oscillation mode selection register cc 0ff80h a/d converter mode register adm 0ff81h a/d converter input selection register adis 0ff83h a/d conversion result register adcr r undefined 0ff84h d/a conversion value setting register 0 dacs0 r/w 00h 0ff85h d/a conversion value setting register 1 dacs1 0ff86h d/a converter mode register 0 dam0 0ff87h d/a converter mode register 1 dam1 0ff88h rom correction control register corc 0ff89h rom correction address pointer h corah 0ff8ah rom correction address pointer l coral 0000h 0ff8bh 0ff8ch external bus type selection register ebts 00h 0ff8dh external access status enable register exae 0ff90h serial operating mode register 0 csim0 0ff91h serial operating mode register 1 csim1 0ff92h serial operating mode register 2 csim2 0ff94h serial i/o shift register 0 sio0 0ff95h serial i/o shift register 1 sio1 0ff96h serial i/o shift register 2 sio2 0ff98h real-time output buffer register l rtbl 0ff99h real-time output buffer register h rtbh note these values are when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to these values. 100 chapter 3 cpu architecture user s manual u13570ej3v0ud table 3-7. special function register (sfr) list (4/5) address name of special function register (sfr) symbol r/w bit manipulation unit after reset note 1 1 bit 8 bits 16 bits 0ff9ah real-time output port mode register rtpm r/w 00h 0ff9bh real-time output port control register rtpc 0ff9ch watch timer mode control register wtm 0ffa0h external interrupt rising edge enable register egp0 0ffa2h external interrupt falling edge enable register egn0 0ffa8h in-service priority register ispr r 0ffa9h interrupt selection control register snmi r/w 0ffaah interrupt mode control register imc 80h 0ffach interrupt mask flag register 0l mk0l mk0 ffffh 0ffadh interrupt mask flag register 0h mk0h 0ffaeh interrupt mask flag register 1l mk1l mk1 0ffafh interrupt mask flag register 1h mk1h 0ffb0h i 2 c bus control register note 2 iicc0 00h 0ffb2h serial clock prescaler mode register note 2 sprm0 0ffb4h slave address register note 2 sva0 0ffb6h i 2 c bus status register note 2 iics0 r 0ffb8h serial shift register note 2 iic0 r/w 0ffc0h standby control register stbc 30h 0ffc2h watchdog timer mode register wdm 00h 0ffc4h memory expansion mode register mm 20h 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 w aaaah 0ffceh clock status register pcs r 32h 0ffcfh oscillation stabilization time specification register osts r/w 00h 0ffd0h to external sfr area 0ffdfh 0ffe0h interrupt control register (intwdtm) wdtic 43h 0ffe1h interrupt control register (intp0) pic0 0ffe2h interrupt control register (intp1) pic1 0ffe3h interrupt control register (intp2) pic2 0ffe4h interrupt control register (intp3) pic3 0ffe5h interrupt control register (intp4) pic4 0ffe6h interrupt control register (intp5) pic5 0ffe7h interrupt control register (intp6) pic6 0ffe8h interrupt control register (intiic0 note 2 /intcsi0) csiic0 notes 1. these values are when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to these values. 2. only in the 101 chapter 3 cpu architecture user s manual u13570ej3v0ud table 3-7. special function register (sfr) list (5/5) address name of special function register (sfr) symbol r/w bit manipulation unit after reset note 1 1 bit 8 bits 16 bits 0ffe9h interrupt control register (intser1) seric1 r/w 43h 0ffeah interrupt control register (intsr1/intcsi1) sric1 0ffebh interrupt control register (intst1) stic1 0ffech interrupt control register (intser2) seric2 0ffedh interrupt control register (intsr2/intcsi2) sric2 0ffeeh interrupt control register (intst2) stic2 0ffefh interrupt control register (inttm3) tmic3 0fff0h interrupt control register (inttm00) tmic00 0fff1h interrupt control register (inttm01) tmic01 0fff2h interrupt control register (inttm1) tmic1 0fff3h interrupt control register (inttm2) tmic2 0fff4h interrupt control register (intad) adic 0fff5h interrupt control register (inttm5) tmic5 0fff6h interrupt control register (inttm6) tmic6 0fff7h interrupt control register (inttm7) tmic7 0fff8h interrupt control register (inttm8) tmic8 0fff9h interrupt control register (intwt) wtic 0fffah interrupt control register (intkr) kric 0fffch internal memory size switching register note 2 ims w ffh notes 1. these values are when the location 0h instruction is executed. when the location 0fh instruction is executed, f0000h is added to these values. 2. only in the 102 chapter 3 cpu architecture user s manual u13570ej3v0ud 3.10 cautions (1) program fetches are not possible from the internal high-speed ram area (when executing the location 0h instruction: 0fd00h to 0feffh, when executing the location 0fh instruction: ffd00h to ffeffh) (2) special function register (sfr) do not access an address that is allocated to an sfr in the area from 0ff00h to 0ffffh note . if mistakenly accessed, the 103 user s manual u13570ej3v0ud chapter 4 clock generator 4.1 functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at a frequency of 2 to 12.5 mhz. oscillation can be stopped by setting the standby control register (stbc) to stop mode (bit 1 (stp) = 1, bit 0 (hlt) = 0) or by stopping the main system clock (bit 2 of stbc (mck) = 1) after switching to the subsystem clock. (2) subsystem clock oscillator this circuit oscillates at the frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, not using the internal feedback resistance can be set by stbc. this enables the power consumption to be decreased in the stop mode. 4.2 configuration the clock generator consists of the following hardware. table 4-1. clock generator configuration item configuration control register standby control register (stbc) oscillation mode selection register (cc) clock status register (pcs) oscillation stabilization time specification register (osts) oscillator main system clock oscillator subsystem clock oscillator 104 chapter 4 clock generator user s manual u13570ej3v0ud figure 4-1. block diagram of clock generator xt2 xt1 x1 x2 stop and bit 2 (mck) of stbc = 1 when the subsystem clock is selected as cpu clock main system clock oscillator subsystem clock oscillator f xt watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) internal system clock (f clk ) divider selector prescaler prescaler selector stop idle controller note idle controller halt controller f x f x 2 f xx 2 f xx 2 2 f xx 2 3 f xx note the oscillation stabilization time is secured after stop mode is released. 105 chapter 4 clock generator user s manual u13570ej3v0ud 4.3 control registers (1) standby control register (stbc) this register is used to set the standby mode and select internal system clock. for the details of the standby mode, refer to chapter 25 standby function . the write operation can be performed only using dedicated instructions to avoid entering into the standby mode due to an inadvertent program loop. this dedicated instruction, mov stbc, #byte, has a special code structure (4 bytes). the write operation is performed only when the op code of the 3rd byte and 4th byte are mutual 1 s complements. when the 3rd byte and 4th byte are not mutual 1 s complements, the write operation is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area indicates the address of the instruction that caused an error. therefore, the address that caused an error can be determined from the return address that is saved in the stack area. if a return from an operand error is performed simply with the retb instruction, an infinite loop will be caused. because the operand error interrupt occurs only in the case of an inadvertent program loop (if mov stbc, #byte is described, only the correct dedicated instruction is generated in nec electronics ra78k4 assembler), initialize the system for the program that processes an operand error interrupt. other write instructions such as mov stbc, a; and stbc, #byte; and set1 stbc.7 are ignored and no operation is performed. in other words, neither is a write operation to stbc performed nor is an interrupt such as an operand error interrupt generated. stbc can be read out any time by means of a data transfer instruction. reset input sets stbc to 30h. figure 4-2 shows the format of stbc. 106 chapter 4 clock generator user s manual u13570ej3v0ud figure 4-2. standby control register (stbc) format address: 0ffc0h after reset: 30h r/w symbol 76543210 stbc sbk ck2 ck1 ck0 0 mck stp hlt sbk subsystem clock oscillation control 0 use oscillator (internal feedback resistor is used.) 1 stop oscillator (internal feedback resistor is not used.) ck2 ck1 ck0 cpu clock selection 000f xx 001f xx /2 010f xx /4 011f xx /8 111f xt (recommended) 1 f xt mck main system clock oscillation control 0 use oscillator (internal feedback resistor is used.) 1 stop oscillator (internal feedback resistor is not used.) stp hlt operation specification flag 0 0 normal operation mode 0 1 halt mode (automatically cleared upon cancellation of halt mode) 1 0 stop mode (automatically cleared upon cancellation of stop mode) 1 1 idle mode (automatically cleared upon cancellation of idle mode) cautions 1. when using the stop mode during external clock input, make sure to set to 1 the extc bit of the oscillation stabilization time specification register (osts) before setting the stop mode. if the stop mode is used during external clock input when the extc bit of osts has been cleared, the pd784218a may be damaged or its reliability may be impaired. when setting to 1 the extc bit of osts, the clock with the opposite phase of the clock input to the x1 pin must be input to the x2 pin. 2. perform the nop instruction three times after a standby instruction (after standby release). otherwise if contention arises between a standby instruction execution and an interrupt request, the standby instruction is not performed and the interrupt request is accepted after the execution of several instructions. the instructions executed before the interrupt request is accepted are instructions whose execution is started within 6 clocks maximum following execution of the standby instruction. 107 chapter 4 clock generator user s manual u13570ej3v0ud example mov stbc, #byte nop nop nop 3. when ck2 = 0, the oscillation of the main system clock does not stop even if mck is set to 1 (refer to 4.5.1 main system clock operations). remarks 1. f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 2. : don t care (2) oscillation mode selection register (cc) this register specifies whether clock output from the main system clock oscillator with the same frequency as the external clock is used to operate the internal circuit (through rate clock mode), or whether clock output that is half of the original frequency is used to operate the internal circuit. cc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets cc to 00h. figure 4-3. oscillation mode selection register (cc) format address: 0ff7ah after reset: 00h r/w symbol 76543210 cc enmp 0000000 enmp main system clock selection 0 half of original oscillation frequency 1 through rate clock mode cautions 1. if the subsystem clock is selected via the standby control register (stbc), the enmp bit specification becomes invalid. 2. the enmp bit cannot be reset by software. this bit is reset performing the system reset. 108 chapter 4 clock generator user s manual u13570ej3v0ud (3) clock status register (pcs) this register is a read-only 8-bit register that indicates the cpu clock operation status. by reading bit 2 and bits 4 to 7 of pcs, the relevant bit of the standby control register (stbc) can be read. pcs is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pcs to 32h. figure 4-4. clock status register (pcs) format address: 0ffceh after reset: 32h r symbol 76543210 pcs sbk ck2 ck1 ck0 0 mck 1 cst sbk feedback resistor status of subsystem clock 0 internal feedback resistor is used. 1 internal feedback resistor is not used. ck2 ck1 ck0 cpu clock operating frequency 000f xx 001f xx /2 010f xx /4 011f xx /8 111f xt (recommended) 1 f xt mck oscillation status of main system clock 0 use oscillator 1 stop oscillator cst cpu clock status 0 main system clock operation 1 subsystem clock operation caution [timing at which bit 0 (cst) changes] the cpu clock does not switch from the main system clock to the subsystem clock immediately after the standby control register (stbc) is set, but switches after synchroni- zation of both clocks (main and subsystem) has been detected. consequently, cst changes after synchronization detection. this is the same as when switching from the subsystem clock to the main system clock. remarks 1. f xx : main system clock frequency f xt : subsystem clock oscillation frequency 2. : don t care 109 chapter 4 clock generator user s manual u13570ej3v0ud (4) oscillation stabilization time specification register (osts) this register specifies the operation of the oscillator. either a crystal/ceramic resonator or external clock is set to the extc bit in osts as the clock used. the stop mode can be set even during external clock input only when the extc bit is set 1. osts is set by a 1-bit or 8-bit transfer instruction. reset input sets osts to 00h. figure 4-5. oscillation stabilization time specification register (osts) format address: 0ffcfh after reset: 00h r/w symbol 76543210 osts extc 0000 osts2 osts1 osts0 extc external clock selection 0 crystal/ceramic resonator is used 1 external clock is used extc osts2 osts1 osts0 oscillation stabilization time selection 00002 19 /f xx (42.0 ms) 00012 18 /f xx (21.0 ms) 00102 17 /f xx (10.5 ms) 00112 16 /f xx (5.3 ms) 01002 15 /f xx (2.6 ms) 01012 14 /f xx (1.3 ms) 01102 13 /f xx (0.7 ms) 01112 12 /f xx (0.4 ms) 1 512/f xx (41.0 s) cautions 1. when a crystal/ceramic resonator is used, make sure to clear the extc bit to 0. if the extc bit is set to 1, oscillation stops. 2. when using the stop mode during external clock input, make sure to set the extc bit to 1 before setting the stop mode. if the stop mode is used during external clock input when the extc bit of osts has been cleared, the pd784218a may be damaged or its reliability may be impaired. 3. if the extc bit is set to 1 during external clock input, the opposite phase of the clock input to the x1 pin must be input to the x2 pin. if the extc bit is set to 1, the pd784218a operates only with the clock input to the x2 pin. remarks 1. figures in parentheses apply to operation with f xx = 12.5 mhz. 2. : don t care 110 chapter 4 clock generator user s manual u13570ej3v0ud 4.4 system clock oscillator 4.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 12.5 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an antiphase clock signal to the x2 pin. figure 4-6 shows an external circuit of the main system clock oscillator. figure 4-6. external circuit of main system clock oscillator (a) crystal or ceramic oscillation (b) external clock crystal or ceramic resonator v ss x1 x2 x1 x2 external clock 4.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the xt1 pin and an antiphase clock signal to the xt2 pin. figure 4-7 shows an external circuit of the subsystem clock oscillator. figure 4-7. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock external clock xt2 xt1 xt2 xt1 32.768 khz v ss 111 chapter 4 clock generator user s manual u13570ej3v0ud cautions 1. when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in figures 4-6 and 4-7 to prevent any effects from wiring capacities. minimize the wiring length. do not allow wiring to intersect with other signal conductors. do not allow wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 4-8 shows examples of oscillators that are connected incorrectly. figure 4-8. examples of oscillator connected incorrectly (1/2) (a) wiring of connection (b) signal conductors intersect circuits is too long each other remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. v ss x1 x2 x1 x2 portn (n = 0 to 10, 12, 13) v ss 112 chapter 4 clock generator user s manual u13570ej3v0ud figure 4-8. examples of oscillator connected incorrectly (2/2) (c) changing high current is too near a (d) current flows through the ground line signal conductor of the oscillator (potential at points a, b, and c fluctuate) (e) signals are fetched remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when xt2 and x1 are wired in parallel, the cross-talk noise of x1 may increase with xt2, resulting in malfunctioning. to prevent this from occurring, it is recommended not to wire x1 and xt2 in parallel. v ss x1 x2 v ss x1 x2 high current v ss x1 c b a pnm v dd high current x2 113 chapter 4 clock generator user s manual u13570ej3v0ud 4.4.3 frequency divider the frequency divider divides the main system clock oscillator output (f xx ) and generates various clocks. 4.4.4 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the xt1 and xt2 pins as follows. xt1: connect to v ss xt2: leave open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, set bit 7 (sbk) of the standby control register (stbc) to 1. in this case also, connect the xt1 and xt2 pins as described above. 114 chapter 4 clock generator user s manual u13570ej3v0ud 4.5 clock generator operations the clock generator generates the following types of clocks and controls the cpu operating mode including the standby mode. main system clock (f xx ) subsystem clock (f xt ) cpu clock (f cpu ) clock to peripheral hardware the following clock generator functions and operations are determined with the standby control register (stbc) and the oscillation mode selection register (cc). (a) upon generation of the reset signal, the lowest speed mode of the main system clock (1,280 ns when operated at 12.5 mhz) is selected (stbc = 30h, cc = 00h). main system clock oscillation stops while low level is applied to the reset pin. (b) with the main system clock selected, one of the five cpu clock types (80 ns, 160 ns, 320 ns, 640 ns, 1,280 ns when operated at 12.5 mhz) can be selected by setting the stbc and cc. (c) with the main system clock selected, two standby modes, the stop mode and the halt mode, are available. to decrease current consumption in the stop mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock with bit 7 (sbk) of stbc, when the system does not use a subsystem clock. (d) stbc can be used to select the subsystem clock and to operate the system with low current consumption (30.5 s when operated at 32.768 khz). (e) with the subsystem clock selected, main system clock oscillation can be stopped with stbc. the halt mode can be used. however, the stop mode cannot be used (subsystem clock oscillation cannot be stopped). (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to the 16-bit timer/counter, the watch timer, and clock output functions only. thus, the 16-bit timer/counter (when watch timer output is selected for count clock during operation with a subsystem clock), the watch function, and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware (except external input clock operation) also stops if the main system clock is stopped. 115 chapter 4 clock generator user s manual u13570ej3v0ud 4.5.1 main system clock operations during operation with the main system clock (with bit 6 (ck2) of the standby control register (stbc) set to 0), the following operations are carried out. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by setting bits 4 to 6 (ck0 to ck2) of the stbc. (b) if bit 2 (mck) of the stbc is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. when bit 6 (ck2) of the stbc is set to 1 and the operation is switched to subsystem clock operation (cst = 1) after that, the main system clock oscillation stops (refer to figure 4-9 ). figure 4-9. main system clock stop function (1/2) (a) operation when mck is set after setting ck2 during main system clock operation (b) operation when mck is set during main system clock operation mck ck2 cst main system clock oscillation subsystem clock oscillation cpu clock mck ck2 cst main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop. 116 chapter 4 clock generator user s manual u13570ej3v0ud figure 4-9. main system clock stop function (2/2) (c) operation when ck2 is set after setting mck during main system clock operation 4.5.2 subsystem clock operations when operated with the subsystem clock (with bit 6 (ck2) of the standby control register (stbc) set to 1), the following operations are carried out. (a) the instruction execution time remains constant (minimum instruction execution time: 61 s when operated at 32.768 khz) irrespective of the setting of bits 4 and 5 (ck0 and ck1) of the stbc. (b) watchdog timer continues opeating. caution do not set the stop mode while the subsystem clock is operating. mck ck2 cst main system clock oscillation subsystem clock oscillation cpu clock 117 chapter 4 clock generator user s manual u13570ej3v0ud 4.6 changing system clock and cpu clock settings the system clock and cpu clock can be switched by means of bits 4 to 6 (ck0 to ck2) of the standby control register (stbc). whether the system is operating on the main system clock or the subsystem clock can be determined by the value of bit 0 (cst) of the clock status register (pcs). this section describes the switching procedure between the system clock and the cpu clock. figure 4-10. system clock and cpu clock switching (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, the main system clock starts oscillating. at this time, the oscillation stabilization time (2 20 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (1,280 ns when operated at 12.5 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speed, the stbc and cc are rewritten and maximum-speed operation is carried out. (3) upon detection of a decrease in the v dd voltage due to an interrupt, the main system clock is switched to the subsystem clock (which must be in a stable oscillation state). (4) upon detection of v dd voltage reset due to an interrupt, 0 is set to stbc bit 2 (mck) and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, stbc is rewritten and maximum-speed operation is resumed. caution when a subsystem clock is being operated while the main system clock is stopped, if switching back to the main system clock, be sure to switch after securing the oscillation stabilization time by program. v dd reset interrupt request signal system clock cpu clock wait (@84.0-ms : 12.5-mhz operation) internal reset operation minimum speed operation maximum speed operation subsystem clock operation f xx f xx f xt f xx maximum speed operation 118 user s manual u13570ej3v0ud chapter 5 port functions 5.1 digital input/output ports the ports shown in figure 5-1, which enable a variety of controls, are provided. the function of each port is described in table 5-1. on-chip pull-up resistors can be specified for ports 0, 2 to 8, 10, and 12 by software during input. figure 5-1. port configuration port 9 port 0 port 7 port 4 port 2 p00 p90 p95 p70 p72 p40 p06 p47 p20 p27 port 13 port 3 p120 p127 p130 port 12 p131 p30 p37 8 port 1 p10 to p17 port 8 p80 p87 port 10 p100 p103 port 5 p50 p57 port 6 p60 p67 119 chapter 5 port functions user s manual u13570ej3v0ud table 5-1. port functions port pin name function specification of software pull-up resistor port 0 p00 to p06 can be specified for input or output in 1-bit units specifiable in 1-bit units port 1 p10 to p17 input port port 2 p20 to p27 can be specified for input or output in 1-bit units specifiable in 1-bit units port 3 p30 to p37 can be specified for input or output in 1-bit units specifiable in 1-bit units port 4 p40 to p47 can be specified for input or output in 1-bit units specifiable individually for each port can drive led directly port 5 p50 to p57 can be specified for input or output in 1-bit units specifiable individually for each port can drive led directly port 6 p60 to p67 can be specified for input or output in 1-bit units specifiable individually for each port port 7 p70 to p72 can be specified for input or output in 1-bit units specifiable in 1-bit units port 8 p80 to p87 can be specified for input or output in 1-bit units specifiable in 1-bit units port 9 p90 to p95 n-ch open drain i/o port can be specified for input or output in 1-bit units can drive led directly port 10 p100 to p103 can be specified for input or output in 1-bit units specifiable in 1-bit units port 12 p120 to p127 can be specified for input or output in 1-bit units specifiable in 1-bit units port 13 p130, p131 can be specified for input or output in 1-bit units 120 chapter 5 port functions user s manual u13570ej3v0ud 5.2 port configuration ports consist of the following hardware: table 5-2. port configuration item configuration control register port mode register (pmm: m = 0, 2 to 10, 12, 13) pull-up resistor option register (puo, pum: m = 0, 2, 3, 7, 8, 10, 12) port total: 86 ports (8 inputs, 78 inputs/outputs) pull-up resistor total: 70 (software control) 5.2.1 port 0 port 0 is a 7-bit input/output port with output latch. the p00 to p06 pins can specify the input mode/output mode in 1-bit units with the port 0 mode register. a pull-up resistor can be connected to the p00 to p06 pins via pull-up resistor option register 0, regardless of whether the input mode or output mode is specified. port 0 also supports external interrupt request input as an alternate function. reset input sets port 0 to the input mode. figure 5-2 shows the block diagram of port 0. caution even though port 0 is also used as an external interrupt input, when port 0 is not used as an interrupt input pin, be sure to set interrupt disabled by using the external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0) or setting the interrupt enable flag (pmkn: n = 0 to 5) to 1. otherwise, the interrupt request flag is set and unintentional interrupt servicing may be executed when specifying ports in output mode and thus changing the output level. 121 chapter 5 port functions user s manual u13570ej3v0ud figure 5-2. block diagram of p00 to p06 pu: pull-up resistor option register pm: port mode register rd: port 0 read signal wr: port 0 write signal p-ch wr pm wr port rd wr pu v dd p00/intp0, p01/intp1, p02/intp2/nmi to p06/intp6 selector pu00 to pu06 output latch (p00 to p06) pm00 to pm06 internal bus alternate function 122 chapter 5 port functions user s manual u13570ej3v0ud 5.2.2 port 1 this is an 8-bit input-only port with no on-chip pull-up resistor. port 1 supports a/d converter analog input as an alternate function. figure 5-3 shows a block diagram of port 1. figure 5-3. block diagram of p10 to p17 rd: port 1 read signal p10/ani0 to p17/ani7 rd internal bus alternate function 123 chapter 5 port functions user s manual u13570ej3v0ud 5.2.3 port 2 port 2 is an 8-bit input/output port with output latch. p20 to p27 pins can specify the input mode/output mode in 1-bit units with the port 2 mode register. a pull-up resistor can be connected to the p20 to p27 pins via pull-up resistor option register 2, regardless of whether the input mode or output mode is specified. the p25 and p27 pins can be specified as n-ch open-drain with a port function control register (only pd784216ay, 784218ay subseries). port 2 supports serial interface data input/output, clock input/output, clock output, and buzzer output as alternate functions. reset input sets port 2 to the input mode. figures 5-4 to 5-7 show block diagrams of port 2. figure 5-4. block diagram of p20 and p22 pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr port rd wr pu v dd selector pu20, pu22 output latch (p20, p22) pm20, pm22 internal bus p20/si1/rxd1, p22/sck1/asck1 alternate function 124 chapter 5 port functions user s manual u13570ej3v0ud figure 5-5. block diagram of p21, p23, p24, and p26 pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr port rd wr pu v dd selector output latch (p21, p23, p24, p26) pm21, pm23, pm24, pm26 pu21, pu23, pu24, pu26 internal bus alternate function p21/so1/t x d1, p23/pcl, p24/buz, p26/so0 125 chapter 5 port functions user s manual u13570ej3v0ud figure 5-6. block diagram of p25 note the sda0 pin applies only to the pd784216ay, 784218ay subseries. pu: pull-up resistor option register pf: port function control register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch p-ch n-ch wr pm wr pf rd wr pu v dd v dd selector pu25 pf25 pm25 internal bus p25/si0/sda0 note wr port output latch (p25) alternate function 126 chapter 5 port functions user s manual u13570ej3v0ud figure 5-7. block diagram of p27 note the scl0 pin applies only to the pd784216ay, 784218ay subseries. pu: pull-up resistor option register pf: port function control register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr pf wr port rd wr pu v dd v dd selector pf27 pm27 pu27 p-ch n-ch internal bus output latch (p27) alternate function p27/sck0/scl0 note alternate function 127 chapter 5 port functions user s manual u13570ej3v0ud 5.2.4 port 3 port 3 is an 8-bit input/output port with output latch. the p30 to p37 pins can specify the input mode/output mode in 1-bit units with the port 3 mode register. a pull-up resistor can be connected to the p30 to p37 pins via pull-up resistor option register 3, regardless of whether the input mode or output mode is specified. port 3 supports timer input/output and external access status output as alternate functions. reset input sets port 3 to the input mode. figures 5-8 and 5-9 show block diagrams of port 3. figure 5-8. block diagram of p30 to p32 and p37 pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal p-ch wr pm wr port rd wr pu v dd selector output latch (p30 to p32, p37) pm30 to pm32, pm37 pu30 to pu32, pu37 internal bus alternate function p30/to0 to p32/to2, p37/exa 128 chapter 5 port functions user s manual u13570ej3v0ud figure 5-9. block diagram of p33 to p36 pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal p-ch wr pm wr port rd wr pu v dd selector alternate function pu33 to pu36 output latch (p33 to p36) pm33 to pm36 internal bus p33/ti1, p34/ti2, p35/ti00, p36/ti01 129 chapter 5 port functions user s manual u13570ej3v0ud 5.2.5 port 4 port 4 is an 8-bit input/output port with output latch. the p40 to p47 pins can specify the input mode/output mode in 1-bit units with the port 4 mode register. when the p40 to p47 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with bit 4 (puo4) of the pull-up resistor option register. port 4 can drive led directly. port 4 supports the address/data bus function in the external memory expansion mode as an alternate function. reset input sets port 4 to the input mode. figure 5-10 shows a block diagram of port 4. figure 5-10. block diagram of p40 to p47 puo: pull-up resistor option register pm: port mode register rd: port 4 read signal wr: port 4 write signal wr pu puo4 wr pu pm40 to p47 output latch (p40 to p47) wr pu wr pu rd p4 internal data bus wr pu p40/ad0 to p47/ad7 v dd mm0 to mm3 external access data internal address bus i/o controller 130 chapter 5 port functions user s manual u13570ej3v0ud 5.2.6 port 5 port 5 is an 8-bit input/output port with output latch. the p50 to p57 pins can specify the input mode/output mode in 1-bit units with the port 5 mode register. when the p50 to p57 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with bit 5 (puo5) of the pull-up resistor option register. port 5 can drive leds directly. port 5 supports the address bus function in the external memory expansion mode as an alternate function. reset input sets port 5 to the input mode. figure 5-11 shows a block diagram of port 5. figure 5-11. block diagram of p50 to p57 puo: pull-up resistor option register pm: port mode register rd: port 5 read signal wr: port 5 write signal mm0 to mm3: bits 0 to 3 of the memory expansion mode register (mm) wr pu0 puo5 mm0 to mm3 wr pm5 pm50 to pm75 rd pu0 wr p5 rd p5 output latch (p50 to p57) rd pm5 v dd0 p50/a8 to p57/a15 internal data bus internal address bus i/o controller 131 chapter 5 port functions user s manual u13570ej3v0ud 5.2.7 port 6 port 6 is an 8-bit input/output port with output latch. the p60 to p67 pins can specify the input mode/output mode in 1-bit units with the port 6 mode register. when pins p60 to p67 are used as input ports, a pull-up resistor can be connected to them in 8-bit units with bit 6 (puo6) of the pull-up resistor option register. port 6 supports the address bus function and the control signal output function in external memory expansion mode as alternate functions. reset input sets port 6 to the input mode. figures 5-12 to 5-14 show block diagrams of port 6. figure 5-12. block diagram of p60 to p63 wr pu0 puo6 wr pm6 pm60 to pm63 rd pu0 wr p6 rd p6 output latch (p60 to p63) rd pm6 v dd p60/a16 to p63/a19 internal address bus internal data bus i/o controller mm0 to mm3 puo: pull-up resistor option register pm: port mode register rd: port 5 read signal wr: port 5 write signal mm0 to mm3: bits 0 to 3 of the memory expansion mode register (mm) 132 chapter 5 port functions user s manual u13570ej3v0ud figure 5-13. block diagram of p64, p65, and p67 wr pu0 rd pu0 wr pm6 wr p6 rd p6 rd pm6 puo6 v dd internal bus output latch (p64, p65, p67) selector pm64, pm65, pm67 p64/rd, p65/wr, p67/astb external expansion mode timing signal for external expansion puo: pull-up resistor option register pm: port mode register rd: port 6 read signal wr: port 6 write signal 133 chapter 5 port functions user s manual u13570ej3v0ud figure 5-14. block diagram of p66 puo: pull-up resistor option register pm: port mode register rd: port 6 read signal wr: port 6 write signal wr pu0 rd pu0 wr pm6 wr p6 rd p6 rd pm6 puo6 v dd p66/wait internal bus pm66 external wait mode output latch (p66) wait input 134 chapter 5 port functions user s manual u13570ej3v0ud 5.2.8 port 7 this is a 3-bit input/output port with output latch. input mode/output mode can be specified in 1-bit units with the port 7 mode register. a pull-up resistor can be connected to the p70 to p72 pins via pull-up resistor option register 7, regardless of whether the input mode or output mode is specified. port 7 supports serial interface data input/output and clock input/output as alternate functions. reset input sets port 7 to the input mode. figures 5-15 to 5-17 show block diagrams of port 7. figure 5-15. block diagram of p70 pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal p-ch wr pm wr port rd wr pu v dd selector pu70 output latch (p70) pm70 internal bus p70/si2/r x d2 alternate function 135 chapter 5 port functions user s manual u13570ej3v0ud figure 5-16. block diagram of p71 pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal p-ch wr pm wr port rd wr pu v dd selector pu71 output latch (p71) pm71 internal bus alternate function p71/so2/t x d2 136 chapter 5 port functions user s manual u13570ej3v0ud figure 5-17. block diagram of p72 pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal p-ch wr pm wr port rd wr pu v dd selector alternate function pu72 output latch (p72) pm72 internal bus p72/sck2/ asck2 137 chapter 5 port functions user s manual u13570ej3v0ud 5.2.9 port 8 this is an 8-bit input/output port with output latch. the p80 to p87 pins can be specified to input mode/output mode in 1-bit units with the port 8 mode register. a pull-up resistor can be connected to the p80 to p87 pins via pull- up resistor option register 8, regardless of whether the input mode or output mode is specified. interrupt control flag (krif) can be set to 1 with falling edge detection (key return interrupt). port 8 supports the address bus function in external memory expansion mode as an alternate function. reset input sets port 8 to the input mode. figure 5-18 shows a block diagram of port 8. figure 5-18. block diagram of p80 to p87 p-ch wr pm wr port rd wr pu v dd selector pu80 to pu87 output latch (p80 to p87) pm80 to pm87 internal bus p80/a0 to p87/a7 pu: pull-up resistor option register pm: port mode register rd: port 8 read signal wr: port 8 write signal figure 5-19. block diagram of falling edge detection circuit p80 p81 p82 p83 p84 p85 p86 p87 falling edge detector krmk krif set signal standby release signal 138 chapter 5 port functions user s manual u13570ej3v0ud 5.2.10 port 9 this is a 6-bit input/output port with output latch. the input/output mode can be specified for the p90 to p95 pins in 1-bit units with the port 9 mode register. port 9 is a n-ch open drain medium-voltage i/o port. port 9 does not include a pull-up resistor. port 9 can drive leds directly. reset input sets port 9 to the input mode. figure 5-20 shows a block diagram of port 9. figure 5-20. block diagram of p90 to p95 pm: port mode register rd: port 9 read signal wr: port 9 write signal wr pm wr port rd selector output latch (p90 to p95) pm90 to pm95 internal bus p90 to p95 139 chapter 5 port functions user s manual u13570ej3v0ud 5.2.11 port 10 this is a 4-bit input/output port with output latch. the input mode/output mode can be specified in 1-bit units for the p100 to p103 pins with the port 10 mode register. a pull-up resistor can be connected to the p100 to p103 pins via pull-up resistor option register 10, regardless of whether the input mode or output mode is specified. port 10 supports timer input/output as an alternate function. reset input sets port 10 to the input mode. figure 5-21 shows a block diagram of port 10. figure 5-21. block diagram of p100 to p103 pu: pull-up resistor option register pm: port mode register rd: port 10 read signal wr: port 10 write signal p-ch wr pm wr port rd wr pu v dd selector output latch (p100 to p103) pm100 to pm103 pu100 to pu103 internal bus alternate function p100/ti5/to5 to p103/ti8/to8 140 chapter 5 port functions user s manual u13570ej3v0ud 5.2.12 port 12 this is an 8-bit input/output port with output latch. input mode/output mode can be specified in 1-bit units with the port 12 mode register. a pull-up resistor can be connected to the p120 to p127 pins via pull-up resistor option register 12, regardless of whether the input mode or output mode is specified. port 12 supports the real-time output function as an alternate function. reset input sets port 12 to the input mode. figure 5-22 shows a block diagram of port 12. figure 5-22. block diagram of p120 to p127 pu: pull-up resistor option register pm: port mode register rd: port 12 read signal wr: port 12 write signal internal bus wr pu rd wr port wr pm pu120 to pu127 output latch (p120 to p127) pm120 to pm127 selector v dd p-ch p120/rtp0 to p127/rtp7 alternate function 141 chapter 5 port functions user s manual u13570ej3v0ud 5.2.13 port 13 this is a 2-bit input/output port with output latch. the input mode/output mode can be specified in 1-bit units with the port 13 mode register. port 13 does not include a pull-up resistor. port 13 supports d/a converter analog output as an alternate function. reset input sets port 13 to the input mode. figure 5-23 shows a block diagram of port 13. caution when only either one of the d/a converter channels is used with av ref1 < v dd , the other pins that are not used as analog outputs must be set as follows: set the port mode register (pm13 ) to 1 (input mode) and connect the pin to v ss . set the port mode register (pm13 ) to 0 (output mode) and the output latch to 0 to output low level from the pin. figure 5-23. block diagram of p130 and p131 pm: port mode register rd: port 13 read signal wr: port 13 write signal wr pm wr port rd selector output latch (p130 and p131) pm130, pm131 internal bus p130/ano0, p131/ano1 alternate function 142 chapter 5 port functions user s manual u13570ej3v0ud 5.3 control registers the following three types of registers control the ports. port mode registers (pm0, pm2 to pm10, pm12, pm13) pull-up resistor option registers (pu0, pu2, pu3, pu7, pu8, pu10, pu12, puo) port function control register (pf2) note note applies only to the pd784216ay, 784218ay subseries. (1) port mode registers (pm0, pm2 to pm10, pm12, pm13) these registers are used to set port input/output in 1-bit units. pm0, pm2 to pm10, pm12, and pm13 are set with a 1-bit or 8-bit memory manipulation instruction, respectively. reset input sets port mode registers to ffh. when port pins are used as alternate function pins, set the port mode registers and output latches according to table 5-3. caution even though port 0 is also used as an external interrupt input, when port 0 is not used as an interrupt input pin, be sure to set interrupt disabled by using the external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0) or setting the interrupt enable flag (pmkn: n = 0 to 5) to 1. otherwise, the interrupt request flag is set and unintentional interrupt servicing may be executed when specifying ports in output mode and thus changing the output level. 143 chapter 5 port functions user s manual u13570ej3v0ud table 5-3. port mode register and output latch settings when using alternate functions pin name alternate function pm p pin name alternate function pm p name i/o name i/o p00, p01 intp0, intp1 input 1 p35, p36 ti00, ti01 input 1 p02 intp2/nmi input 1 p37 exa output 0 0 p03 to p06 intp3 to intp6 input 1 p40 to p47 ad0 to ad7 i/o note 2 p10 to p17 note 1 ani0 to ani7 input p50 to p57 a8 to a15 output note 2 p20 rxd1/si1 input 1 p60 to p63 a16 to a19 output note 2 p21 txd1/so1 output 0 0 p64 rd output note 2 p22 asck1 input 1 p65 wr output note 2 sck1 input 1 p66 wait input note 2 output 0 0 p67 astb output note 2 p23 pcl output 0 0 p70 rxd2/si2 input 1 p24 buz output 0 0 p71 txd2/so2 output 0 0 p25 si0 input 1 p72 asck2 input 1 sda0 note 4 i/o 0 0 sck2 input 1 p26 so0 output 0 0 output 0 0 p27 sck0 input 1 p80 to p87 a0 to a7 output note 3 output 0 0 p100 to p103 ti5 to ti8 input 1 scl0 note 4 i/o 0 0 to5 to to8 output 0 0 p30 to 32 to0 to to2 output 0 0 p120 to p127 rtp0 to rtp7 output 0 0 p33, p34 ti1, ti2 input 1 p130, p131 note 1 ano0, ano1 output 1 notes 1. if these ports are read out when these pins are used in the alternate function mode, undefined values are read. 2. when the p40 to p47 pins, p50 to p57 pins, and p60 to p67 pins are used for an alternate function, set the function with the memory expansion mode register. 3. when the p80 to p87 pins are used for an alternate function, set the function with the external bus type selection register. 4. the sda0 and scl0 pins are provided only for the pd784216ay, 784218ay subseries. cautions 1. when not using external wait in the external memory expansion mode, the p66 pin can be used as an i/o port. 2. when using the i 2 c bus mode, specify n-ch open-drain for the scl0/p27 and sda0/p25 pins by setting the port function control register (pf2). remark : don t care (not necessary to set) : not available for the port mode register and output latch pm : port mode register p : port output latch 144 chapter 5 port functions user s manual u13570ej3v0ud figure 5-24. port mode register format address: 0ff20h, 0ff22h to 0ff2ah, 0ff2ch, 0ff2dh after reset: ffh r/w symbol 76543210 pm0 1 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm6 pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pm7 11111 pm72 pm71 pm70 pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pm9 1 1 pm95 pm94 pm93 pm92 pm91 pm90 pm10 1111 pm103 pm102 pm101 pm100 pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 pm13 111111 pm131 pm130 pmxn pxn pin i/o mode specification x = 0: n = 0 to 6 x = 2 to 6, 8, 12: n = 0 to 7 x = 7: n = 0 to 2 x = 9: n = 0 to 5 x = 10: n = 0 to 3 x = 13: n = 0, 1 0 output mode (output buffer on) 1 input mode (output buffer off) 145 chapter 5 port functions user s manual u13570ej3v0ud (2) pull-up resistor option registers (pu0, pu2, pu3, pu7, pu8, pu10, pu12, puo) these registers are used to set whether to use an internal pull-up resistor at each port or not in 1-bit or 8-bit units. pun (n = 0, 2, 3, 7, 8, 10, 12) can specify the pull-up resistor connection of each port pin. puo can specify the pull-up resistor connection of ports 4, 5, and 6. pull-up resistors are connected irrespective of whether an alternate function is used. these registers are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. cautions 1. ports 1, 9, and 13 do not incorporate a pull-up resistor. 2. ports 4, 5, 6, and 8 can connect a pull-up resistor during external memory expansion mode. 3. the pull-up resistor of ports 0, 2, 3, 7, 8, 10, and 12 is not disconnected even if these ports are set in the output mode. to use these ports in the output mode, it is recommended to clear the corresponding pull-up resistor option register to 0. 146 chapter 5 port functions user s manual u13570ej3v0ud figure 5-25. pull-up resistor option register format address: 0ff30h, 0ff32h, 0ff33h, 0ff37h, 0ff38h, 0ff3ah, 0ff3ch after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pu0 0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 pu2 pu27 pu26 pu25 pu24 pu23 pu22 pu21 pu20 pu3 pu37 pu36 pu35 pu34 pu33 pu32 pu31 pu30 pu7 00000 pu72 pu71 pu70 pu8 pu87 pu86 pu85 pu84 pu83 pu82 pu81 pu80 pu10 0000 pu103 pu102 pu101 pu100 pu12 pu127 pu126 pu125 pu124 pu123 pu122 pu121 pu120 puxn pxn pin pull-up resistor specification x = 0: n = 0 to 6 x = 2, 3, 8, 12: n = 0 to 7 x = 7: n = 0 to 2 x = 10: n = 0 to 3 0 no pull-up resistor connection 1 pull-up resistor connection address: 0ff4eh after reset: 00h r/w symbol 7 <6> <5> <4> 3210 puo 0 puo6 puo5 puo4 0000 puon port n pull-up resistor specification (n = 4 to 6) 0 no pull-up resistor connection 1 pull-up resistor connection caution connecting pull-up resistors unnecessarily may increase the current consumption or latch up other devices, so specify a mode whereby pull-up resistors are only connected to the required parts. if required and not-required parts exist together, externally connect pull- up resistors to the required parts and set to the mode that specifies not to connect on-chip pull-up resistors. 147 chapter 5 port functions user s manual u13570ej3v0ud (3) port function control register (pf2) this register specifies n-ch open-drain for pins p25 and p27. pf2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pf2 to 00h. caution only the pd784216ay, 784218ay subseries incorporates pf2. when using the i 2 c bus mode (serial interface), make sure to specify n-ch open-drain for the p25 and p27 pins. figure 5-26. port function control register (pf2) format address: 0ff42h after reset: 00h r/w symbol 76543210 pf2 pf27 0 pf25 00000 pf2n p2n pin n-ch open-drain specification (n = 5, 7) 0 don t set n-ch open-drain 1 set n-ch open-drain 148 chapter 5 port functions user s manual u13570ej3v0ud 5.4 operations port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instructions, although a single bit is manipulated, the port is accessed in 8-bit units. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 5.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 5.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instructions, although a single bit is manipulated, the port is accessed in 8-bit units. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, except for the manipulated bit. 149 user s manual u13570ej3v0ud chapter 6 real-time output functions 6.1 functions the real-time output function transfers preset data in the real-time output buffer register to the output latch by hardware synchronized to the generation of a timer interrupt or an external interrupt and outputs it off the chip. also, the pins for output off the chip are called the real-time output port. since jitter-free signals can be output by using the real-time output port, the operation is optimized for the control of stepping motors, for example. the port mode or real-time output mode is bit selectable. 6.2 configuration the real-time output port consists of the following hardware. table 6-1. real-time output port configuration item configuration register real-time output buffer registers (rtbl, rtbh) control register real-time output port mode register (rtpm) real-time output port control register (rtpc) 150 chapter 6 real-time output functions user s manual u13570ej3v0ud figure 6-1. block diagram of real-time output port internal bus rtpoe byte extr output trigger control circuit real-time output port control register (rtpc) real-time output port mode register (rtpm) real-time output port output latch rtp7 rtp0 higher 4 bits of real- time output buffer register (rtbh) lower 4 bits of real- time output buffer register (rtbl) intp2 inttm1 inttm2 port 12 output latch p127 p120 p12n/rtpn pin output (n = 0 to 7) p127/ p120/ rtp7 rtp0 rtpoe bit 151 chapter 6 real-time output functions user s manual u13570ej3v0ud real-time output buffer registers (rtbl, rtbh) these 4-bit registers save the output data beforehand. rtbl and rtbh are mapped to independent addresses in the special function register (sfr) as shown in figure 6-2. when the 4 bits 2 channels operating mode is specified, rtbl and rtbh can be independently set with data. in addition, if the address of either rtbl or rtbh is specified, the data in both registers can be read in a batch. when the 8 bits 1 channel operating mode is specified, writing 8-bit data to either rtbl or rtbh can set data in each register. in addition, if the address of either rtbl or rtbh is specified, the data in both registers can be read in a batch. table 6-2 lists the operations for manipulating rtbl and rtbh. figure 6-2. real-time output buffer register configuration higher 4 bits lower 4 bits 0ff98h rtbl 0ff99h rtbh table 6-2. operations for manipulating real-time output buffer registers operating mode manipulated register reading note 1 writing note 2 higher 4 bits lower 4 bits higher 4 bits lower 4 bits 4 bits 2 channels rtbl rtbh rtbl invalid rtbl rtbh rtbh rtbl rtbh invalid 8 bits 1 channel rtbl rtbh rtbl rtbh rtbl rtbh rtbh rtbl rtbh rtbl notes 1. only the bits specified in the real-time output port mode can be read. when the bits set in the port mode are read, zeros are read. 2. after setting the real-time output port, set the output data in rtbl and rtbh until the real-time output trigger is generated. 152 chapter 6 real-time output functions user s manual u13570ej3v0ud 6.3 control registers the real-time output port is controlled by the following two registers. real-time output port mode register (rtpm) real-time output port control register (rtpc) (1) real-time output port mode register (rtpm) this register sets the real-time output port mode and port mode selections in 1-bit units. rtpm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets rtpm to 00h. figure 6-3. real-time output port mode register (rtpm) format address: 0ff9ah after reset: 00h r/w symbol 76543210 rtpm rtpm7 rtpm6 rtpm5 rtpm4 rtpm3 rtpm2 rtpm1 rtpm0 rtpmm real-time output port selection (m = 0 to 7) 0 port mode 1 real-time output port mode caution when used as a real-time output port, set the port for real-time output in the output mode. 153 chapter 6 real-time output functions user s manual u13570ej3v0ud (2) real-time output port control register (rtpc) this register sets the operating mode and output trigger of the real-time output port. table 6-3 shows the relationships between the operating modes and output triggers of the real-time output port. rtpc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets rtpc to 00h. figure 6-4. real-time output port control register (rtpc) format address: 0ff9bh after reset: 00h r/w symbol <7> 6 <5> <4> 3210 rtpc rtpoe 0 byte extr 0000 rtpoe real-time output port operation control 0 operation disabled 1 operation enabled note byte real-time output port operating mode 0 4 bits 2 channels 1 8 bits 1 channel extr real-time output control by intp2 0 intp2 is not the real-time output trigger. 1 intp2 is the real-time output trigger. note when real-time output operation is enabled (rtpoe = 1), the values of the real-time output buffer registers (rtbh and rtbl) are transferred into the output latch of the real-time output port. caution when intp2 is specified as an output trigger, specify the valid edge using the external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0). table 6-3. operating modes and output triggers of real-time output port byte extr operating mode rtbh port output rtbl port output 0 0 4 bits 2 channels inttm2 inttm1 0 1 inttm1 intp2 1 0 8 bits 1 channel inttm1 1 1 intp2 154 chapter 6 real-time output functions user s manual u13570ej3v0ud 6.4 operation when real-time output is enabled by bit 7 (rtpoe) = 1 in the real-time output port control register (rtpc), data in the real-time output buffer registers (rtbh, rtbl) are transferred to the output latch synchronized to the generation of the selected transfer trigger (set by extr and byte note ). based on the setting of the real-time output port mode register (rtpm), only the transferred data for the bits specified in the real-time output port are output from bits rtp0 to rtp7. a port set in the port mode by rtpm can be used as a general-purpose i/o port. note extr: bit 4 of the real-time output port control register (rtpc) byte: bit 5 of the real-time output port control register (rtpc) figure 6-5. example of operation timing of real-time output port (extr = 0, byte = 0) inttm2 inttm1 cpu operation rtbh rtbl output latch p123 to p120 output latch p127 to p124 d01 d02 d03 d04 abababab d11 d12 d13 d14 d01 d02 d03 d04 d11 d12 d13 d14 a: software processing by inttm2 (rtbh write) b: software processing by inttm1 (rtbl write) 155 chapter 6 real-time output functions user s manual u13570ej3v0ud 6.5 usage (1) disabling the real-time output operation set bit 7 (rtpoe) = 0 in the real-time output port control register (rtpc). (2) initial settings set the output latch to 0. the value that is output by real-time output operation is the result of oring the output latches of the port and the real-time output port (refer to figure 6-1 block diagram of real-time output port ). therefore, after the real-time output operation is enabled, set the port output latch to 0 until the transfer trigger is generated. set the port in output mode. set the real-time output buffer registers (rtbh, rtbl) to the initial value. (3) enable real-time output operation. rtpoe = 1 after the real-time output operation is enabled, the values of rtbh and rtbl are latched to the real-time output port output latch. (4) when the selected transfer trigger is generated, the values of rtbh and rtbl are latched to the pin, and the next output is set to rtbh and rtbl by the interrupt processing corresponding to the trigger. (5) hereafter, the next real-time output values are sequentially set in the rtbh and rtbl by the interrupt processing corresponding to the selected trigger. 6.6 cautions for the initial setting, set bit 7 (rtpoe) in the real-time output port control register (rtpc) to 0 to disable the real- time output operation. 156 user s manual u13570ej3v0ud chapter 7 timer overview there are one on-chip 16-bit timer/event counter and six on-chip 8-bit timer/event counters. since a total of eight interrupt requests is supported, these timer/counters can function as eight timer/counters. table 7-1. timer/counter operation name 16-bit timer/ 8-bit timer/ 8-bit timer/ 8-bit timer/ 8-bit timer/ 8-bit timer/ 8-bit tim er/ item event counter event counter 1 event counter 2 event counter 5 event counter 6 event counter 7 event counter 8 count 8 bits width 16 bits operating interval timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch mode external event counter function timer output 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch ppg output pwm output square wave output one-shot pulse output pulse width measurement 2 inputs no. of interrupt requests 2 111111 157 chapter 7 timer overview user s manual u13570ej3v0ud figure 7-1. timer/counter block diagram (1/2) 16-bit timer/event counter f xx /4 f xx /16 inttm3 ti01 edge detector edge detector selector selector 16-bit timer counter 0 (tm0) 16-bit capture/compare register 00 (cr00) 16-bit capture/compare register 01 (cr01) 16 16 clear inttm00 inttm01 to0 output controller ti00 8-bit timer/event counter 1 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 selector selector 8-bit timer counter 1 (tm1) 8-bit compare register 10 (cr10) 8 clear ovf inttm1 output controller to1 ti1 edge detector inttm2 8-bit timer/event counter 2 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 selector 8-bit timer counter 2 (tm2) 8-bit compare register 20 (cr20) 8 clear ovf output controller to2 ti2 edge detector tm1 inttm2 remark ovf: overflow flag 158 chapter 7 timer overview user s manual u13570ej3v0ud figure 7-1. timer/counter block diagram (2/2) 8-bit timer/event counters 5 and 7 remark n = 5 or 7 8-bit timer/event counters 6 and 8 remark n = 6 or 8 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 selector selector 8-bit timer counter n (tmn) 8-bit compare register n0 (crn0) 8 clear ovf inttmn + 1 inttmn output controller ton edge detector tin f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 selector 8-bit timer counter n (tmn) 8-bit compare register n0 (crn0) 8 clear ovf inttmn output controller ton edge detector tmn 1 tin 159 user s manual u13570ej3v0ud chapter 8 16-bit timer/event counter 8.1 function the 16-bit timer/event counter has the following functions: interval timer ppg output pulse width measurement external event counter square wave output one-shot pulse output (1) interval timer when the 16-bit timer/event counter is used as an interval timer, it generates an interrupt request at predetermined time intervals. (2) ppg output the 16-bit timer/event counter can output a square wave whose frequency and output pulse width can be freely set. (3) pulse width measurement the 16-bit timer/event counter can be used to measure the pulse width of a signal input from an external source. (4) external event counter the 16-bit timer/event counter can be used to measure the number of pulses of a signal input from an external source. (5) square wave output the 16-bit timer/event counter can output a square wave with any frequency. (6) one-shot pulse output the 16-bit timer/event counter can output a one-shot pulse with any output pulse width. 160 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.2 configuration the 16-bit timer/event counter consists of the following hardware: table 8-1. 16-bit timer/event counter configuration item configuration timer counter 16 bits 1 (tm0) register 16-bit capture/compare register: 16 bits 2 (cr00, cr01) timer output 1 (to0) control register 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register (toc0) prescaler mode register 0 (prm0) figure 8-1. block diagram of 16-bit timer/event counter internal bus crc02 crc01 crc00 capture/compare control register 0 (crc0) ti01 f xx /4 f xx /16 inttm3 f xx ti00 noise eliminator 16-bit capture/compare register 00 (cr00) 16-bit timer counter 0 (tm0) 16-bit capture/compare register 01 (cr01) noise eliminator clear match match to0 inttm00 output controller inttm01 crc02 2 prescaler mode register 0 (prm0) timer mode control register (tmc0) 16-bit timer output control register (toc0) internal bus selector selector selector prm01 prm00 ovf0 tmc01 tmc02 tmc03 toe0 toc01 lvr0 lvs0 toc04 ospe ospt noise eliminator selector 161 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (1) 16-bit timer counter 0 (tm0) tm0 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> reset is input . <2> tmc03 and tmc02 are cleared. <3> valid edge of ti00 is input in the clear & start mode by inputting valid edge of ti00. <4> tm0 and cr00 match in the clear & start mode on match between tm0 and cr00. <5> bit 6 of toc0 (ospt) is set or if the valid edge of ti00 is input in the one-shot pulse output mode. 162 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (2) 16-bit capture/compare register 00 (cr00) cr00 is a 16-bit register that functions as a capture register and as a compare register. whether this register functions as a capture or compare register is specified by using bit 0 (crc00) of capture/compare control register 0 (crc0). when using cr00 as compare register the value set to cr00 is always compared with the count value of 16-bit timer counter 0 (tm0). when the values of the two match, an interrupt request (inttm00) is generated. when tm0 is used as an interval timer, cr00 can also be used as a register that holds the interval time. when using cr00 as capture register the valid edge of the ti00 or ti01 pin can be selected as a capture trigger. the valid edge of ti00 and ti01 is set via prescaler mode register 0 (prm0). tables 8-2 and 8-3 show the conditions that apply when the capture trigger is specified as the valid edge of the ti00 pin and the valid edge of the ti01 pin, respectively. table 8-2. valid edge of ti00 pin and capture trigger of cr00 es01 es00 valid edge of ti00 pin capture trigger of cr00 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation table 8-3. valid edge of ti01 pin and capture trigger of cr00 es01 es00 valid edge of ti01 pin capture trigger of cr00 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges cr00 is set by a 16-bit memory manipulation instruction. reset input sets cr00 to 0000h. caution set cr00 to the value other than 0000h. when using the register as an event counter, a count for one-pulse cannot be operated. 163 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (3) 16-bit capture/compare register 01 (cr01) this is a 16-bit register that can be used as a capture register and a compare register. whether it is used as a capture register or compare register is specified by bit 2 (crc02) of capture/compare control register 0 (crc0). when using cr01 as compare register the value set to cr01 is always compared with the count value of 16-bit timer counter 0 (tm0). when the values of the two match, an interrupt request (inttm01) is generated. when using cr01 as capture register the valid edge of the ti00 pin can be selected as a capture trigger. the valid edge of ti00 is specified by using prescaler mode register 0 (prm0). table 8-4 shows the conditions that apply when the capture trigger is specified as the valid edge of the ti00 pin. table 8-4. valid edge of ti00 pin and capture trigger of cr01 es01 es00 valid edge of ti00 pin capture trigger of cr01 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges cr01 is set by a 16-bit memory manipulation instruction. reset input sets cr01 to 0000h. caution set cr01 to the value other than 0000h. when using an event counter, a count for one-pulse cannot be operated. 164 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.3 control registers the following four types of registers control the 16-bit timer/event counter. 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register (toc0) prescaler mode register 0 (prm0) (1) 16-bit timer mode control register (tmc0) this register specifies the operation mode of the 16-bit timer; and the clear mode, output timing, and overflow detection of the 16-bit timer register. tmc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc0 to 00h. caution the 16-bit timer register starts operating when a value other than 0, 0 (operation stop mode) is set to tmc02 and tmc03. to stop the operation, set 0, 0 to tmc02 and tmc03. 165 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-2. format of 16-bit timer mode control register (tmc0) address: 0ff18h after reset: 00h r/w symbol 7654321<0> tmc0 0000 tmc03 tmc02 tmc01 ovf0 tmc03 tmc02 tmc01 selection of selection of to0 generation of operating mode output timing interrupt and clear mode 000 001 010 011 100 101 110 111 ovf0 detection of overflow of 16-bit timer register 0 overflows. 1 does not overflow. does not generate. generates on match between tm0 and cr00 or match between tm0 and cr01. operation stop (tm0 is cleared to 0). not affected match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01, or valid edge of ti00 match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01, or valid edge of ti00 match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01, or valid edge of ti00 free-running mode clears and starts at valid edge of ti00. clears and starts on match between tm0 and cr00. 166 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud cautions 1. before changing the clear mode and to0 output timing, be sure to stop the timer operation (reset tmc02 and tmc03 to 0, 0). the valid edge of the ti00 pin is selected by using prescaler mode register 0 (prm0). 2. when a mode in which the timer is cleared and started on a match between tm0 and cr00, the ovf0 flag is set to 1 when the count value of tm0 changes from ffffh to 0000h with cr00 set to ffffh. 3. the software trigger (bit 6 (ospt) of 16-bit timer output control register 0 (toc0) = 1) and the external trigger (ti00 input) are always valid in one-shot pulse output mode. if the software trigger is used in one-shot pulse output mode, the ti00 pin cannot be used as a general-purpose port pin. therefore, fix the ti00 pin to either high level or low level. remark to0: output pin of 16-bit timer counter (tm0) ti00: input pin of 16-bit timer counter (tm0) tm0: 16-bit timer register cr00: compare register 00 cr01: compare register 01 167 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (2) capture/compare control register 0 (crc0) this register controls the operation of the capture/compare registers (cr00 and cr01). crc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 to 00h. figure 8-3. format of capture/compare control register 0 (crc0) address: 0ff16h after reset: 00h r/w symbol 76543210 crc0 00000 crc02 crc01 crc00 crc02 selection of operation mode of cr01 0 operates as compare register. 1 operates as capture register. crc01 selection of capture trigger of cr00 0 captured at valid edge of ti01. 1 captured in reverse phase of valid edge of ti00. crc00 selection of operation mode of cr00 0 operates as compare register. 1 operates as capture register. cautions 1. before setting crc0, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on a match between tm0 and cr00 is selected by the 16-bit timer mode control register (tmc0), do not specify cr00 as a capture register. (3) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter output controller by setting or resetting the r-s flip-flop (lv0), enabling or disabling reverse output, enabling or disabling output of the 16-bit timer/event counter, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. toc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets toc0 to 00h. figure 8-4 shows the format of toc0. 168 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-4. format of 16-bit timer output control register (toc0) address: 0ff1ah after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc0 0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 ospt output trigger control of one-shot pulse by software 0 no one-shot pulse trigger 1 uses one-shot pulse trigger. ospe controls of one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output toc04 timer output control on match between cr01 and tm0 0 disables reverse timer output f/f. 1 enables reverse timer output f/f. lvs0 lvr0 timer output control by software 0 0 not affected 0 1 resets (0). 1 0 sets (1). 1 1 setting prohibited toc01 timer output control on match between cr00 and tm0 and valid edge of ti00 0 disables reverse timer output f/f. 1 enables reverse timer output f/f. toe0 output control of 16-bit timer/event counter 0 disables output (output is fixed to 0 level). 1 enables output. cautions 1. before setting toc0, be sure to stop the timer operation. 2. lvs0 and lvr0 are 0 when read after data have been set to them. 3. ospt is 0 when read because it is automatically cleared after data has been set. 169 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (4) prescaler mode register 0 (prm0) this register selects a count clock of the 16-bit timer counter (tm0) and the valid edge of the ti00, ti01 input. prm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets prm0 to 00h. figure 8-5. format of prescaler mode register 0 (prm0) address: 0ff1ch after reset: 00h r/w symbol 76543210 prm0 es11 es10 es01 es00 0 0 prm01 prm00 es11 es10 selection of valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 selection of valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 selection of count clock 00f xx /4 (3.13 mhz) 01f xx /16 (781 khz) 1 0 inttm3 (timer output for clock) 1 1 valid edge of ti00 caution when selecting the valid edge of ti00 as the count clock, do not specify the valid edge of ti00 to clear and start the timer and as a capture trigger. set the count clock to be f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz 170 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.4 operation 8.4.1 operation as interval timer (16-bit operation) the 16-bit timer/event counter operates as an interval timer when the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) are set as shown in figure 8-6. in this case, the 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register 00 (cr00). when the count value of the 16-bit timer counter (tm0) matches the set value of cr00, the value of tm0 is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttm00) is generated. the count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (prm00 and prm01) of prescaler mode register 0 (prm0). figure 8-6. control register settings during interval timer operation (a) 16-bit timer mode control register (tmc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the interval timer function. for details, refer to figures 8-2 and 8-3 . 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. 171 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-7. configuration of interval timer figure 8-8. timing of interval timer operation remark interval time = (n + 1) t: n = 0001h to ffffh f xx /4 f xx /16 inttm3 ti00/p35 selector 16-bit capture/compare register 00 (cr00) 16-bit timer counter (tm0) ovf0 clear circuit inttm00 count starts clear clear interrupt acknowledged interrupt acknowledged t 0000 0001 n 0000 0001 n 0000 0001 n n n n n interval time interval time interval time count clock tm0 count value cr00 inttm00 to0 172 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.4.2 operation as ppg output the 16-bit timer/event counter can be used for ppg (programmable pulse generator) output by setting the 16- bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-9. the ppg output function outputs a rectangular wave with a cycle specified by the count value set in advance to 16-bit capture/compare register 00 (cr00) and a pulse width specified by the count value set in advance to 16-bit capture/compare register 01 (cr01). figure 8-9. control register settings during ppg output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) 00000 crc02 0 crc01 crc00 0 crc0 cr00 as compare register cr01 as compare register (c) 16-bit timer output control register (toc0) remark : don t care caution set a value in the following range to cr00 and cr01. 0000h < cr01 < cr00 ffffh 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. 0 ospt 0 ospe 0 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. reverses output on match between tm0 and cr01. disables one-shot pulse output. specifies initial value of to0 output f/f. reverses output on match between tm0 and cr00. 173 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.4.3 operation as pulse width measurement the 16-bit timer counter (tm0) can be used to measure the pulse widths of the signals input to the ti00/p35 and ti01/p36 pins. measurement can be carried out with tm0 used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the ti00/p35 pin. (1) pulse width measurement with free-running counter and one capture register if the edge specified by prescaler mode register 0 (prm0) is input to the ti00/p35 pin when the 16-bit timer counter (tm0) is used as a free-running counter (refer to figure 8-10 ), the value of tm0 is loaded to 16-bit capture/ compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the edge is specified by using bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. figure 8-10. control register settings during pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as capture register remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 8-2 and 8-3 . 174 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-11. configuration of pulse width measurement with free-running counter figure 8-12. timing of pulse width measurement with free-running counter and one capture register (with both edges specified) t (d1 d0) t (10000h d1 + d2) t (d3 d2) t count clock 0000 0001 d0 d1 0000 d2 d3 tm0 count value d3 ti00 pin input value loaded to cr01 inttm01 ovf0 d0 d1 d2 ffff caution for simplication purposes, delay due to noise elimination is not taken into consideration in the capture operation by ti00 pin input and in the interrupt request generation timing in the above figure. for a more accurate picture, refer to figure 8-14 cr01 capture operation with rising edge specified. inttm01 f xx /4 f xx /16 inttm3 selector 16-bit capture/compare register 01 (cr01) 16-bit timer counter (tm0) ovf0 ti00/p35 internal bus 175 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (2) measurement of two pulse widths with free-running counter the pulse widths of the two signals respectively input to the ti00/p35 and ti01/p36 pins can be measured when the 16-bit timer counter (tm0) is used as a free-running counter (refer to figure 8-13 ). when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/p35 pin, the value of the tm0 is loaded to 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. when the edge specified by bits 6 and 7 (es10 and es11) of prescaler mode register 0 (prm0) is input to the ti01/p36 pin, the value of tm0 is loaded to 16-bit capture/compare register 00 (cr00), and an external interrupt request signal (inttm00) is set. the edges of the ti00/p35 and ti01/p36 pins are specified by bits 4 and 5 (es00 and es01) and bits 6 and 7 (es10 and es11) of prm0, respectively. the rising, falling, or both rising and falling edges can be specified. the valid edge of the ti00/p35 pin and ti01/p36 pin is detected through sampling at a count clock cycle selected by prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. fig u re 8-13. control register settings during measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 8-2 and 8-3 . 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 as capture register captures valid edge of ti01/p36 pin to cr00. cr01 as capture register 176 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud capture operation (free-running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 8-14. cr01 capture operation with rising edge specified count clock tm0 ti00 rising edge detection cr01 inttm01 n 3n 2n 1 n n + 1 n figure 8-15. timing of pulse width measurement with free-running counter (with both edges specified) t (d1 d0) t (10000h d1 + d2) t count clock 0000 0001 d0 d1 ffff 0000 d2 d3 tm0 count value d0 d1 d2 d3 ti00 pin input value loaded to cr01 inttm01 ovf0 d1 (10000h d1 + (d2 + 1)) t (d3 d2) t ti01 pin input value loaded to cr00 inttm00 note note d2 + 1 caution for simplication purposes, delay due to noise elimination is not taken into consideration in the capture operation by ti00 pin input and in the interrupt request generation timing in the above figure. for a more accurate picture, refer to figure 8-14 cr01 capture operation with rising edge specified. 177 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (3) pulse width measurement with free-running counter and two capture registers when the 16-bit timer counter (tm0) is used as a free-running counter (refer to figure 8-16 ), the pulse width of the signal input to the ti00/p35 pin can be measured. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/p35 pin, the value of tm0 is loaded to 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the value of tm0 is also loaded to 16-bit capture/compare register 00 (cr00) when an edge reverse to the one that triggers capturing to cr01 is input. the edge of the ti00/p35 pin is specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). the rising or falling edge can be specified. the valid edge of the ti00/p35 pin is detected through sampling at a count clock cycle selected by prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. caution if the valid edge of the ti00/p35 pin is specified to be both the rising and falling edges, 16- bit capture/compare register 00 (cr00) cannot perform its capture operation. figure 8-16. control register settings during pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 8-2 and 8-3 . 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/p35 pin. cr01 as capture register 178 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-17. timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) t (d1 d0) t (10000h d1 + d2) t count clock 0000 0001 d0 d1 ffff 0000 d2 d3 tm0 count value d0 d2 d3 ti00 pin input value loaded to cr01 value loaded to cr00 d1 (d3 d2) t inttm01 ovf0 caution for simplication purposes, delay due to noise elimination is not taken into consideration in the capture operation by ti00 pin input and in the interrupt request generation timing in the above figure. for a more accurate picture, refer to figure 8-14 cr01 capture operation with rising edge specified. 179 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (4) pulse width measurement by restarting when the valid edge of the ti00/p35 pin is detected, the pulse width of the signal input to the ti00/p35 pin can be measured by clearing the 16-bit timer counter (tm0) once and then resuming counting after loading the count value of tm0 to 16-bit capture/compare register 01 (cr01) (refer to figure 8-18 ). the edge of the ti00/p35 pin is specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). the rising or falling edge can be specified. the valid edge is detected through sampling at a count clock cycle selected by prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. caution if the valid edge of the ti00/p35 pin is specified to be both the rising and falling edges, 16- bit capture/compare register 00 (cr00) cannot perform its capture operation. figure 8-18. control register settings during pulse width measurement by restarting (a) 16-bit timer mode control register (tmc0) 0000 tmc03 1 tmc02 0 tmc01 0/1 ovf0 0 tmc0 clears and starts at valid edge of ti00/p35 pin. (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge of ti00/p35 pin. cr01 as capture register remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 8-2 and 8-3 . 180 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-19. timing of pulse width measurement by restarting (with rising edge specified) t d1 t d2 t count clock 0000 0001 d0 d1 0000 0001 d2 0001 tm0 count value d0 d2 ti00 pin input value loaded to cr01 value loaded to cr00 d1 inttm01 0000 caution for simplication purposes, delay due to noise elimination is not taken into consideration in the capture operation by ti00 pin input and in the interrupt request generation timing in the above figure. for a more accurate picture, refer to figure 8-14 cr01 capture operation with rising edge specified. 8.4.4 operation as external event counter the 16-bit timer/counter can be used as an external event counter which counts the number of clock pulses input to the ti00/p35 pin from an external source by using the 16-bit timer counter (tm0). each time the valid edge specified by prescaler mode register 0 (prm0) has been input to the ti00/p35 pin, tm0 is incremented. to perform a count operation using the ti00/p35 pin input clock, specify the ti00 valid edge using bits 0 and 1 of prm0 (prm00, prm01). set cr00 to a value other than 0000h (a 1-pulse counter can not be operated). the edge of the ti00/p35 pin is specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). the rising, falling, or both the rising and falling edges can be specified. when using the ti00 pin input as the count clock, sampling for valid edge detection is locked by the main system clock (f xx ) and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be eliminated. 181 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-20. control register settings during external event counter mode (a) 16-bit timer mode control register (tmc0) 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the external event counter function. for details, refer to figures 8-2 and 8-3. figure 8-21. configuration of external event counter 16-bit capture/compare register 00 (cr00) 16-bit timer counter (tm0) clear ovf0 inttm00 16-bit capture/compare register 01 (cr01) valid edge of ti00 internal bus 182 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-22. timing of external event counter operation (with rising edge specified) ti00 pin input 0000 0001 0003 0005 n 1 0001 0003 tm0 count value n cr00 inttm00 0002 0004 0000 0002 n caution read tm0 when reading the count value of the external event counter. 8.4.5 operation as square wave output the 16-bit timer/event counter can be used to output a square wave with any frequency at an interval specified by the count value set in advance to 16-bit capture/compare register 00 (cr00). by setting bits 0 (toe0) and 1 (toc01) of 16-bit timer output control register (toc0) to 1, the output status of the to0/p30 pin is reversed at an interval specified by the count value set in advance to cr00. in this way, a square wave of any frequency can be output. 183 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-23. control register settings during square wave output mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the square wave output function. for details, refer to figures 8-2 , 8-3 , and 8-4 . figure 8-24. timing of square wave output operation 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 0000 0001 n 1 n 0001 0002 n 1n n count clock tm0 count value cr00 0000 0000 0002 inttm00 to0 pin output 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. 0 ospt 0 ospe 0 toc04 0 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. disables one-shot pulse output. does not reverse output on match between tm0 and cr01. specifies initial value of to0 output. reverses output on match between tm0 and cr00. 184 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.4.6 operation as one-shot pulse output the 16-bit timer/event counter can output a one-shot pulse in synchronization with a software trigger and an external trigger (ti00/p35 pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output from the to0/p30 pin by setting the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and 16-bit timer output control register (toc0) as shown in figure 8-25, and by setting bit 6 (ospt) of toc0 by software. by setting ospt to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted active at the count value set in advance to 16-bit capture/compare register 01 (cr01). after that, the output is deasserted inactive at the count value set in advance to 16-bit capture/compare register 00 (cr00). even after the one-shot pulse has been output, tm0 continues its operation. to stop tm0, tmc0 must be reset to 00h. cautions 1. do not set ospt to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until inttm00, which occurs on a match between tm0 and cr00, occurs. 2. the software trigger (bit 6 (ospt) of 16-bit timer output control register 0 (toc0) = 1) and the external trigger (ti00 input) are always valid in one-shot pulse output mode. if the software trigger is used in one-shot pulse output mode, the ti00 pin cannot be used as a general-purpose port pin. therefore, fix the p35/ti00 pin to either high level or low level. 185 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-25. control register settings during one-shot pulse output with software trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the one- shot pulse output function. for details, refer to figures 8-2 , 8-3 , and 8-4 . caution set a value in the following range to cr00 and cr01. 0000h < cr01 < cr00 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as compare register 0000 tmc03 0/1 tmc02 0/1 tmc01 0/1 ovf0 0 tmc0 clears and starts, or free-running by the valid edge of ti00/p35 pin. 0 ospt 0 ospe 1 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. sets one-shot pulse output mode. set to 1 for output. specifies initial value of to0 output. reverses output on match between tm0 and cr01. reverses output on match between tm0 and cr00. 186 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-26. timing of one-shot pulse output operation with software trigger cautions 1. the 16-bit timer register starts operating as soon as a value other than 0, 0 (operation stop mode) has been set to tmc02 and tmc03. 2. the software trigger (bit 6 (ospt) of 16-bit timer output control register 0 (toc0) = 1) and the external trigger (ti00 input) are always valid in one-shot pulse output mode. if the software trigger is used in one-shot pulse output mode, the ti00 pin cannot be used as a general-purpose port pin. therefore, fix the p35/ti00 pin to either high level or low level. (2) one-shot pulse output with external trigger a one-shot pulse can be output from the to0/p30 pin by setting the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and 16-bit timer output control register (toc0) as shown in figure 8-27, and by using the valid edge of the ti00/p35 pin as an external trigger. the valid edge of the ti00/p35 pin is specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti00/p35 pin is detected, the 16-bit timer/event counter is cleared and started, and the output is asserted active at the count value set in advance to 16-bit capture/compare register 01 (cr01). after that, the output is deasserted inactive at the count value set in advance to 16-bit capture/compare register 00 (cr00). sets 0ch to tmc0 (tm0 count starts) count clock 0000 0001 0000 tm0 count value m n cr01 set value cr00 set value ospt inttm01 inttm00 to0 pin output n + 1 m 1 m+1 m+2 m+3 m n m n m n nn n 1m 187 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud cautions 1. if the external trigger is generated while the one-shot pulse is output, the counter is cleared and started, and the one-shot pulse is output again. 2. the software trigger (bit 6 (ospt) of 16-bit timer output control register 0 (toc0) = 1) and the external trigger (ti00 input) are always valid in one-shot pulse output mode. if the software trigger is used in one-shot pulse output mode, the ti00 pin cannot be used as a general-purpose port pin. therefore, fix the p35/ti00 pin to either high level or low level. figure 8-27. control register settings during one-shot pulse output with external trigger (a) 16-bit timer mode control register (tmc0) 0000 tmc03 0/1 tmc02 0/1 tmc01 0/1 ovf0 0 tmc0 clears and starts, or free-running at valid edge of ti00/p35 pin. (b) capture/compare control register 0 (crc0) 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as compare register (c) 16-bit timer output control register (toc0) remark 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the one- shot pulse output function. for details, refer to figures 8-2 , 8-3, and 8-4 . caution set a value in the following range to cr00 and cr01. 0000h < cr01 < cr00 0 ospt 0 ospe 1 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. sets one-shot pulse output mode. specifies initial value of to0 output. reverses output on match between tm0 and cr00. reverses output on match between tm0 and cr01. 188 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud figure 8-28. timing of one-shot pulse output operation with external trigger (with rising edge specified) sets 08h to tmc0 (tm0 count starts) count clock 0000 0001 0000 tm0 count value m n cr01 set value cr00 set value ti00 pin input inttm01 inttm00 to0 pin output n + 1 n + 2 m 1m m n m n m n nm 2 m + 1 m + 2 m + 3 cautions 1. the 16-bit timer register starts operating as soon as a value other than 0, 0 (operation stop mode) has been set to tmc02 and tmc03. 2. the software trigger (bit 6 (ospt) of 16-bit timer output control register 0 (toc0) = 1) and the external trigger (ti00 input) are always valid in one-shot pulse output mode. if the software trigger is used in one-shot pulse output mode, the ti00 pin cannot be used as a general-purpose port pin. therefore, fix the p35/ti00 pin to either high level or low level. 189 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud 8.5 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the 16-bit timer counter (tm0) is started asynchronously in respect to the count pulse. figure 8-29. start timing of 16-bit timer register tm0 count value 0000h 0001h 0002h 0004h count pulse timer starts 0003h (2) setting 16-bit compare register set 16-bit capture/compare register 00, 01 (cr00, cr01) to a value other than 0000h. when using this register as an event counter, a count for one-pulse cannot be operated. (3) setting compare register during timer count operation if the value to which the current value of 16-bit capture/compare register 00 (cr00) has been changed is less than the value of the 16-bit timer counter (tm0), tm0 continues counting, overflows, and starts counting again from 0. if the new value of cr00 (m) is less than the old value (n), the timer must be restarted after the value of cr00 has been changed. figure 8-30. timing after changing value of compare register during timer count operation cr00 nm count pulse tm0 count value x 1 x ffffh 0000h 0001h 0002h remark n > x > m 190 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (4) data hold timing of capture register if the valid edge is input to the ti00/p35 pin while 16-bit capture/compare register 01 (cr01) is read, cr01 does not perform the capture operation, and holds the data. however, the interrupt request flag (inttm01) is set as a result of detection of the valid edge. figure 8-31. data hold timing of capture register (5) setting valid edge before setting the valid edge of the ti00/p35 pin, stop the timer operation by resetting bits 2 and 3 (tmc02 and tmc03) of the 16-bit timer mode control register (tmc0) to 0, 0. set the valid edge by using bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). (6) cautions on edge detection <1> when the ti00/ti01 pin is high level immediately after system reset, it may be detected as a rising edge after the first 16-bit timer/event counter operation is enabled. bear this in mind when pulling up, etc. <2> regardless of whether interrupt acknowledgement is disabled (di) or enabled (ei), the edge of the external input signal is detected at the second clock after the signal is changed. tm0 count value n n + 1 n + 2 m m + 1 m + 2 n + 1 x count pulse edge input interrupt request flag capture read signal value loaded to cr01 capture operation ignored edge detection ti00/ti01 pin input count clock interrupt acknow- ledgement status interrupts disabled (di) interrupts enabled (ei) 191 chapter 8 16-bit timer/event counter user s manual u13570ej3v0ud (7) trigger for one-shot pulse the software trigger (bit 6 (ospt) of 16-bit timer output control register 0 (toc0) = 1) and the external trigger (ti00 input) are always valid in one-shot pulse output mode. if the software trigger is used in one-shot pulse output mode, the p35/ti00 pin cannot be used as a general- purpose port pin. therefore, fix the p35/ti00 pin to either high level or low level. (8) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set ospt to 1. do not output the one-shot pulse again until inttm00, which occurs on a match between tm0 and cr00, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs while a one-shot pulse is output, the counter is cleared and started, and the one-shot pulse is output again. (9) operation of ovf0 flag the ovf0 flag is set to 1 in the following case: select mode in which the 16-bit timer/event counter is cleared and started on a match between tm0 and cr00 set cr00 to ffffh when tm0 counts up from ffffh to 0000h figure 8-32. operation timing of ovf0 flag ffffh fffeh ffffh 0000h 0001h count pulse cr00 tm0 ovf0 inttm00 (10) contention operation <1> contention between the read period of 16-bit capture/compare registers (cr00 and cr01) and the capture trigger input (cr00 and cr01 are used as capture registers) the capture trigger input has priority. the read data of cr00 and cr01 is undefined. <2> match timing contention between the write period of 16-bit capture/compare registers (cr00 and cr01) and 16-bit timer counter (tm0) (cr00 and cr01 are used as compare registers) match detection is not normally performed. do not perform the write operation of cr00 and cr01 around the match timing. 192 user s manual u13570ej3v0ud chapter 9 8-bit timer/event counter 1, 2 9.1 functions 8-bit timer/event counter 1, 2 (tm1, tm2) have the following two modes. mode using 8-bit timer/event counter 1, 2 (tm1, tm2) alone (individual mode) mode using the cascade connection (16-bit resolution: cascade connection mode) these two modes are described next. (1) mode using 8-bit timer/event counter 1, 2 alone (individual mode) the timer operates as an 8-bit timer/event counter. it can have the following functions. interval timer external event counter square wave output pwm output (2) mode using the cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by connecting in cascade. it can have the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution 193 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.2 configuration 8-bit timer/event counter 1, 2 consist of the following hardware. table 9-1. 8-bit timer/event counter 1, 2 configuration item configuration timer counter 8 bits 2 (tm1, tm2) register 8 bits 2 (cr10, cr20) timer output 2 (to1, to2) control register 8-bit timer mode control register 1 (tmc1) 8-bit timer mode control register 2 (tmc2) prescaler mode register 1 (prm1) prescaler mode register 2 (prm2) figure 9-1. block diagram of 8-bit timer/event counter 1, 2 (1/2) (1) 8-bit timer/event counter 1 internal bus internal bus tcl12 tcl11 tcl10 prescaler mode register 1 (prm1) 8-bit timer mode control register 1 (tmc1) toe1 tmc16 0 lvs1 lvr1 tmc1 toe1 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 7 f xx /2 9 ti1 tm2 compare match selector edge detector 8-bit compare register 10 (cr10) match 8-bit timer counter 1 (tm1) selector selector output controller mask circuit clear inttm2 inttm1 to tm2 to1 194 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-1. block diagram of 8-bit timer/event counter 1, 2 (2/2) (2) 8-bit timer/event counter 2 internal bus internal bus tcl22 tcl21 tcl20 prescaler mode register 2 (prm2) 8-bit timer mode control register 2 (tmc2) toe2 tmc26 tmc24 lvs2 lvr2 tmc2 toe2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 7 f xx /2 9 ti2 tm1 overflow selector edge detector 8-bit compare register 20 (cr20) match 8-bit timer counter 2 (tm2) selector selector output controller mask circuit clear inttm2 to2 195 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud (1) 8-bit timer counter 1, 2 (tm1, tm2) tm1 and tm2 are 8-bit read-only registers that count the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when the count is read out during operation, the count clock input temporarily stops and the count is read at that time. in the following cases, the count becomes 00h. <1> reset is input. <2> tcen is cleared. <3> tmn and crn0 match in the clear and start mode. caution in a cascade connection, the count becomes 00h by clearing both bit 7 (tce1) of 8-bit timer mode control register 1 (tmc1) and bit 7 (tce2) of 8-bit timer mode control register 2 (tmc2). remark n = 1, 2 (2) 8-bit compare register (cr10, cr20) the value set in cr10 and cr20 are compared to the count in 8-bit timer counter 1 (tm1) and 8-bit timer counter 2 (tm2), respectively. if the two values match, interrupt requests (inttm1, inttm2) is generated (except in the pwm mode). the values of cr10 and cr20 can be set in the range of 00h to ffh, and can be written during counting. caution while the timers are connected in cascade, always set data after stopping the timer. to stop timer operation, clear both bit 7 of tmc1 (tce1) and bit 7 of tmc2 (tce2). 196 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.3 control registers the following four registers control 8-bit timer/event counter 1, 2. 8-bit timer mode control register 1, 2 (tmc1, tmc2) prescaler mode register 1, 2 (prm1, prm2) (1) 8-bit timer mode control register 1, 2 (tmc1, tmc2) the tmc1 and tmc2 registers make the following six settings. <1> controls the counting for 8-bit timer counter 1, 2 (tm1, tm2). <2> selects the operating mode of 8-bit timer counter 1, 2 (tm1, tm2). <3> selects the individual mode or cascade mode. <4> sets the state of the timer output. <5> controls the timer output or selects the active level during the pwm (free-running) mode. <6> controls timer output. tmc1 and tmc2 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc1 and tmc2 to 00h. figures 9-2 and 9-3 show the tmc1 format and tmc2 format respectively. 197 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-2. format of 8-bit timer mode control register 1 (tmc1) address: 0ff54h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc1 tce1 tmc16 0 0 lvs1 lvr1 tmc11 toe1 tce1 tm1 count control 0 counting is disabled (prescaler disabled) after the counter is cleared to 0. 1 start counting tmc16 tm1 operating mode selection 0 clear and start mode when tm1 and cr10 match. 1 pwm (free-running) mode lvs1 lvr1 timer output control by software 0 0 no change 0 1 reset (to 0). 1 0 set (to 1). 1 1 setting prohibited tmc11 other than pwm mode (tmc16 = 0) pwm mode (tmc16 = 1) timer output control active level selection 0 disable inversion operation active high 1 enable inversion operation active low toe1 timer output control 0 disable output (port mode) 1 enable output caution when selecting the tm1 operation mode using tmc16, stop the timer operation in advance. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce1 = 0. 2. if lvs1 and lvr1 are read after setting data, 0 is read. 198 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-3. format of 8-bit timer mode control register 2 (tmc2) address: 0ff55h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc2 tce2 tmc26 0 tmc24 lvs2 lvr2 tmc21 toe2 tce2 tm2 count control 0 counting is disabled (prescaler disabled) after the counter is cleared to 0. 1 start counting tmc26 tm2 operating mode selection 0 clear and start mode when tm2 and cr20 match 1 pwm (free-running) mode tmc24 individual mode or cascade connection mode selection 0 individual mode 1 cascade connection mode (connection with tm1) lvs2 lvr2 timer output control by software 0 0 no change 0 1 reset (to 0). 1 0 set (to 1). 1 1 setting prohibited tmc21 other than pwm mode (tmc26 = 0) pwm mode (tmc26 = 1) timer output control active level selection 0 disable inversion operation active high 1 enable inversion operation active low toe2 timer output control 0 disable output (port mode) 1 enable output caution when selecting the tm2 operation mode using tmc26 or selecting discrete/cascade connec- tion mode using tmc24, stop timer operation in advance. to stop the timer operation during cascade connection, clear both bit 7 (tce1) of 8-bit timer mode control register 1 (tmc1) and bit 7 (tce2) of tmc2. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce2 = 0. 2. if lvs2 and lvr2 are read after setting data, 0 is read. 199 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud (2) prescaler mode register 1, 2 (prm1, prm2) this register sets the count clock of 8-bit timer counter 1, 2 (tm1, tm2) and the valid edge of ti1, ti2 inputs. prm1 and prm2 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets prm1 and prm2 to 00h. figure 9-4. format of prescaler mode register 1 (prm1) address: 0ff56h after reset: 00h r/w symbol 76543210 prm1 00000 tcl12 tcl11 tcl10 tcl12 tcl11 tcl10 count clock selection 0 0 0 falling edge of ti1 0 0 1 rising edge of ti1 010f xx /4 (3.13 mhz) 011f xx /8 (1.56 mhz) 100f xx /16 (781 khz) 101f xx /32 (391 khz) 110f xx /128 (97.6 khz) 111f xx /512 (24.4 khz) cautions 1. if writing data different than that of prm1, stop the timer beforehand. 2. be sure to set bits 3 to 7 of prm1 to 0. 3. when specifying the valid edge of ti1 for the count clock, set the count clock to f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 200 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-5. format of prescaler mode register 2 (prm2) address: 0ff57h after reset: 00h r/w symbol 76543210 prm2 00000 tcl22 tcl21 tcl20 tcl22 tcl21 tcl20 count clock selection 0 0 0 falling edge of ti2 0 0 1 rising edge of ti2 010f xx /4 (3.13 mhz) 011f xx /8 (1.56 mhz) 100f xx /16 (781 khz) 101f xx /32 (391 khz) 110f xx /128 (97.6 khz) 111f xx /512 (24.4 khz) cautions 1. if writing data different than that of prm2, stop the timer beforehand. 2. be sure to set bits 3 to 7 of prm2 to 0. 3. when specifying the valid edge of ti2 for the count clock, set the count clock to f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 201 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.4 operation 9.4.1 operation as interval timer (8-bit operation) the timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the preset count in 8-bit compare register 10, 20 (cr10, cr20). if the count in 8-bit timer register 1, 2 (tm1, tm2) matches the value set in cr10, cr20, simultaneous to clearing the value of tm1, tm2 to 0 and continuing the count, the interrupt request signal (inttm1, inttm2) is generated. the tm1 and tm2 count clocks can be selected with bits 0 to 2 (tcln0 to tcln2) in prescaler mode register 1, 2 (prm1, prm2). 202 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-6. timing of interval timer operation (1/3) (a) basic operation start count clear clear interrupt request received interrupt request received t 00h 01h n 00h 01h n 00h 01h n n n n n interval time interval time interval time count clock tmn count crn0 inttmn ton tcen remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 1, 2 203 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-6. timing of interval timer operation (2/3) (b) when crn0 = 00h t count clock tmn crn0 tcen inttmn ton interval time 00h 00h 00h 00h 00h (c) when crn0 = ffh t count clock tmn crn0 tcen inttmn ton 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt request acknowledged interrupt request acknowledged remark n = 1, 2 204 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-6. timing of interval timer operation (3/3) (d) operated by crn0 transition (m < n) count clock tmn crn0 tcen inttmn ton n 00h m n ffh 00h m 00h nm crn0 transition tmn overflows since m < n. h (e) operated by crn0 transition (m > n) count clock tmn crn0 tcen inttmn ton n 1n n 00h 01h n m 1 m 00h 01h m crn0 transition h remark n = 1, 2 205 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.4.2 operation as external event counter the external event counter counts the number of external clock pulses that are input to the ti1/p33 and ti2/p34 pins with 8-bit timer counter 1, 2 (tm1, tm2). each time a valid edge specified in prescaler mode register 1, 2 (prm1, prm2) is input, tm1 and tm2 are incremented. the edge setting is selected to be either a rising edge or falling edge. if the counting of tm1 and tm2 matches with the values of 8-bit compare register 10, 20 (cr10, cr20), the tm1 and tm2 are cleared to 0 and the interrupt request signal (inttm1, inttm2) is generated. inttm1 and inttm2 are generated each time when the value of the tm1 and tm2 matches the value of cr10 and cr20. figure 9-7. timing of external event counter operation (with rising edge specified) remark n = 00h to ffh n = 1, 2 tin pin input 00h 01h 03h 05h n 1 01h 03h tmn count n crn0 inttmn 02h 04h 00h 02h n 206 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.4.3 operation as square wave output (8-bit resolution) a square wave having any frequency is output at the interval preset in 8-bit compare register 10, 20 (cr10, cr20). by setting bit 0 (toe1, toe2) of 8-bit timer mode control register 1, 2 (tmc1, tmc2) to 1, the output state of to1, to2 is inverted with the count preset in cr10, cr20 as the interval. therefore, a square wave output having any frequency (duty cycle = 50 %) is possible. 207 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.4.4 operation as 8-bit pwm output by setting bit 6 (tmc16, tmc26) of 8-bit timer mode control register 1, 2 (tmc1, tmc2) to 1, the timer operates as a pwm output. pulses with the duty cycle determined by the value set in 8-bit compare register 10, 20 (cr10, cr20) is output from to1, to2. set the width of the active level of the pwm pulse in cr10, cr20. the active level can be selected by bit 1 (tmc11, tmc12) in tmc1, tmc2. the count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of prescaler mode register 1, 2 (prm1, prm2). the pwm output can be enabled and disabled by bit 0 (toe1, toe2) of tmc1, tmc2. (1) basic operation of the pwm output 208 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-8. timing of pwm output (a) basic operation (active level = h) count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h nn mn n n active level reload reload inactive level active level (b) when crn0 = 0 count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h 00h 00h m 00h inactive level inactive level reload reload n + 2 00h (c) when crn0 = ffh count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h m ffh ffh ffh ffh ffh active level inactive level n + 2 active level inactive level inactive level reload reload remark n = 1, 2 209 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-9. timing of operation based on crn0 transitions (a) when the crn0 value from n to m before tmn overflows count clock tmn crn0 crn0 read value tcen inttmn ton crn0 transition (n m) reload n n + 1n + 2 ffh 00h 01h m m + 1m + 2 ffh 00h 01h 02h m m + 1m + 2 n 02h mm h reload n m m (b) when the crn0 value changes from n to m after tmn overflows count clock tmn crn0 crn0 read value tcen inttmn ton n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h 03h m m m + 1m + 2 crn0 transition (n m) reload reload nnmm (c) when the crn0 value changes from n to m during two clocks (00h, 01h) immediately after tmn overflows count clock tmn crn0 crn0 read value tcen inttmn ton n n + 1n + 2 ffh 00h 01h n n + 1n + 2 ffh 00h 01h 02h n 02h n h m m m + 1m + 2 reload & crn0 transition (n m) reload mm m n remarks 1. n = 1, 2 2. crn0 (m): master side, crn0 (s): slave side 210 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud 9.4.5 operation as interval timer (16-bit operation) cascade connection (16-bit timer) mode by setting bit 4 (tmc24) of 8-bit timer mode control register 2 (tmc2) to 1, the timer enters the timer/counter mode with 16-bit resolution. with the count preset in 8-bit compare register 10, 20 (cr10, cr20) as the interval, the timer operates as an interval timer by repeatedly generating interrupt requests. 211 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud figure 9-10. cascade connection mode with 16-bit resolution count clock tm1 tm2 cr10 cr20 tce1 tce2 inttm1 to1 00h 00h 01h n + 1 n ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h n m 01h 02h m 1 m 00h b 00h enable operation starting count interval time interrupt request generated level inverted counter cleared operation stopped 9.5. cautions (1) error when the timer starts the time until the match signal is generated after the timer starts has a maximum error of one clock. the reason is the starting of 8-bit timer counter 1, 2 (tm1, tm2) is asynchronous with respect to the count pulse. figure 9-11. start timing of 8-bit timer counter tm1, tm2 count 00h 01h 02h 04h count pulse timer starts 03h 212 chapter 9 8-bit timer/event counter 1, 2 user s manual u13570ej3v0ud (2) operation after the compare register is changed while the timer is counting if the value after 8-bit compare register 10, 20 (cr10, cr20) changes is less than the value of the 8-bit timer counter (tm1, tm2), counting continues, overflows, and counting starts again from 0. consequently, when the value (m) after cr10, cr20 changes is less than the value (n) before the change, the timer must restart after cr10, cr20 changes. figure 9-12. timing after compare register changes during timer counting caution except when the ti1, ti2 input is selected, always set tce1 = 0, tce2 = 0 before setting the stop mode. remark n > x > m (3) tm1, tm2 read out during timer operation since the count clock stops temporarily when tm1 and tm2 are read during operation, select for the count clock a waveform with a high and low level that exceed 2 cycles of the cpu clock. when reading tm1 and tm2 during cascade connection, to avoid reading while the count is changing, take measures such as obtaining a count match by reading twice using software. cr10, cr20 nm count pulse tm1, tm2 count x 1 x ffffh 0000h 0001h 0002h 213 user s manual u13570ej3v0ud chapter 10 8-bit timer/event counter 5, 6 10.1 functions 8-bit timer/event counter 5, 6 (tm5, tm6) have the following two modes. mode using 8-bit timer/event counter 5, 6 (tm5, tm6) alone (individual mode) mode using the cascade connection (16-bit resolution: cascade connection mode) these two modes are described next. (1) mode using 8-bit timer/event counter 5, 6 alone (individual mode) the timer operates as an 8-bit timer/event counter. it can have the following functions. interval timer external event counter square wave output pwm output (2) mode using the cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by connecting in cascade. it can have the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution 214 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud 10.2 configuration 8-bit timer/event counter 5, 6 consist of the following hardware. table 10-1. 8-bit timer/event counter 5, 6 configuration item configuration timer counter 8 bits 2 (tm5, tm6) register 8 bits 2 (cr50, cr60) timer outputs 2 (to5, to6) control registers 8-bit timer mode control register 5 (tmc5) 8-bit timer mode control register 6 (tmc6) prescaler mode register 5 (prm5) prescaler mode register 6 (prm6) figure 10-1. block diagram of 8-bit timer/event counter 5, 6 (1/2) (1) 8-bit timer/event counter 5 tm6 compare match edge detector ti5 to5 to tm6 inttm5 selector selector clear inttm6 match internal bus internal bus selector mask circuit 8-bit compare register 50 (cr50) output controller 8-bit timer counter 5 (tm5) prescaler mode register 5 (prm5) 8-bit timer mode control register 5 (tmc5) tcl52 tcl51 tcl50 tce5 tmc56 0 lvs5 lvr5 tmc51 toe5 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 7 f xx /2 9 215 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-1. block diagram of 8-bit timer/event counter 5, 6 (2/2) (2) 8-bit timer/event counter 6 ti6 to6 inttm6 match selector selector clear internal bus mask circuit selector 8-bit compare register 60 (cr60) 8-bit timer counter 6 (tm6) circuit controller edge detector internal bus tcl62 prescaler mode register 6 (prm6) 8-bit timer mode control register 6 (tmc6) tcl61 tcl60 tce6 tmc66 tmc64 lvs6 lvr6 tmc61 toe6 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 7 f xx /2 9 tm5 overflow 216 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud (1) 8-bit timer counter 5, 6 (tm5, tm6) tm5 and tm6 are 8-bit read-only registers that count the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when the count is read out during operation, the count clock input temporarily stops and the count is read at that time. in the following cases, the count becomes 00h. <1> reset is input. <2> tcen is cleared. <3> tmn and crn0 match in the clear and start mode. caution in a cascade connection, the count becomes 00h by clearing bit 7 (tce5) of 8-bit timer mode control register 5 (tmc5) and bit 7 (tce6) of 8-bit timer mode control register 6 (tmc6). remark n = 5, 6 (2) 8-bit compare register (cr50, cr60) the value set in cr50 and cr60 are compared to the count in 8-bit timer counter 5 (tm5) and 8-bit timer counter 6 (tm6), respectively. if the two values match, interrupt requests (inttm5, inttm6) is generated (except in the pwm mode). the values of cr50 and cr60 can be set in the range of 00h to ffh, and can be written during counting. caution be sure to stop the timer operation before setting data in cascade connection mode. to stop the timer operation, clear both bit 7 (tce5) of tmc5 and bit 7 (tce6) of tmc6. 217 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud 10.3 control registers the following four registers control 8-bit timer/event counter 5, 6. 8-bit timer mode control register 5, 6 (tmc5, tmc6) prescaler mode register 5, 6 (prm5, prm6) (1) 8-bit timer mode control register 5, 6 (tmc5, tmc6) the tmc5 and tmc6 registers make the following six settings. <1> controls the counting for 8-bit timer counter 5, 6 (tm5, tm6). <2> selects the operating mode of 8-bit timer counter 5, 6 (tm5, tm6). <3> selects the individual mode or cascade mode. <4> sets the state of the timer output. <5> controls the timer output or selects the active level during the pwm (free-running) mode. <6> controls timer output. tmc5 and tmc6 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc5 and tmc6 to 00h. figures 10-2 and 10-3 show the tmc5 format and tmc6 format respectively. 218 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-2. format of 8-bit timer mode control register 5 (tmc5) address: 0ff68h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc5 tce5 tmc56 0 0 lvs5 lvr5 tmc51 toe5 tce5 tm5 count control 0 counting is disabled (prescaler disabled) after the counter is cleared to 0. 1 start counting tmc56 tm5 operating mode selection 0 clear and start mode when tm5 and cr50 match. 1 pwm (free-running) mode lvs5 lvr5 timer output control by software 0 0 no change 0 1 reset (to 0). 1 0 set (to 1). 1 1 setting prohibited tmc51 other than pwm mode (tmc56 = 0) pwm mode (tmc56 = 1) timer output control active level selection 0 disable inversion operation active high 1 enable inversion operation active low toe5 timer output control 0 disable output (port mode) 1 enable output caution when selecting the tm5 operation mode using tmc56, stop the timer operation in advance. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce5 = 0. 2. if lvs5 and lvr5 are read after setting data, 0 is read. 219 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-3. format of 8-bit timer mode control register 6 (tmc6) address: 0ff69h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc6 tce6 tmc66 0 tmc64 lvs6 lvr6 tmc61 toe6 tce6 tm6 count control 0 counting is disabled (prescaler disabled) after the counter is cleared to 0. 1 start counting tmc66 tm6 operating mode selection 0 clear and start mode when tm6 and cr60 match 1 pwm (free-running) mode tmc64 individual mode or cascade connection mode selection 0 individual mode 1 cascade connection mode (connection with tm5) lvs6 lvr6 timer output control by software 0 0 no change 0 1 reset (to 0). 1 0 set (to 1). 1 1 setting prohibited tmc61 other than pwm mode (tmc66 = 0) pwm mode (tmc66 = 1) timer output control active level selection 0 disable inversion operation active high 1 enable inversion operation active low toe6 timer output control 0 disable output (port mode) 1 enable output caution when selecting the tm6 operation mode using tmc66 or selecting discrete/cascade connection mode using tmc64, stop the timer operation in advance. to stop the timer operation during cascade connection, clear both bit 7 (tce5) of 8-bit timer mode control register 5 (tmc5) and bit 7 (tce6) of tmc6. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce6 = 0. 2. if lvs6 and lvr6 are read after setting data, 0 is read. 220 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud (2) prescaler mode register 5, 6 (prm5, prm6) this register sets the count clock of 8-bit timer counter 5, 6 (tm5, tm6) and the valid edge of ti5, ti6 inputs. prm5 and prm6 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets prm5 and prm6 to 00h. figure 10-4. format of prescaler mode register 5 (prm5) address: 0ff6ch after reset: 00h r/w symbol 76543210 prm5 00000 tcl52 tcl51 tcl50 tcl52 tcl51 tcl50 count clock selection 0 0 0 falling edge of ti5 0 0 1 rising edge of ti5 010f xx /4 (3.13 mhz) 011f xx /8 (1.56 mhz) 100f xx /16 (781 khz) 101f xx /32 (391 khz) 110f xx /128 (97.6 khz) 111f xx /512 (24.4 khz) cautions 1. if writing data different than that of prm5, stop the timer beforehand. 2. be sure to set bits 3 to 7 of prm5 to 0. 3. when specifying the valid edge of ti5 for the count clock, set the count clock to f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 221 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-5. format of prescaler mode register 6 (prm6) address: 0ff6dh after reset: 00h r/w symbol 76543210 prm6 00000 tcl62 tcl61 tcl60 tcl62 tcl61 tcl60 count clock selection 0 0 0 falling edge of ti6 0 0 1 rising edge of ti6 010f xx /4 (3.13 mhz) 011f xx /8 (1.56 mhz) 100f xx /16 (781 khz) 101f xx /32 (391 khz) 110f xx /128 (97.6 khz) 111f xx /512 (24.4 khz) cautions 1. if writing data different than that of prm6, stop the timer beforehand. 2. be sure to set bits 3 to 7 of prm6 to 0. 3. when specifying the valid edge of ti6 for the count clock, set the count clock to f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 222 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud 10.4 operation 10.4.1 operation as interval timer (8-bit operation) the timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the preset count in 8-bit compare register 50, 60 (cr50, cr60). if the count in 8-bit timer counter 5, 6 (tm5, tm6) matches the value set in cr50, cr60, the value of tm5, tm6 is cleared to 0, counting continues, and the interrupt request signals (inttm5, inttm6) are generated. the tm5 and tm6 count clocks can be selected with bits 0 to 2 (tcln0 to tcln2) in prescaler mode register 5, 6 (prm5, prm6). 223 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud start count clear clear interrupt request received interrupt request received t 00h 01h n 00h 01h n 00h 01h n n n n n interval time interval time interval time count clock tmn count crn0 inttmn ton tcen figure 10-6. timing of interval timer operation (1/3) (a) basic operation remarks 1. interval time = (n + 1) t; n = 00h to ffh 2. n = 5, 6 224 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-6. timing of interval timer operation (2/3) (b) when crn0 = 00h t count clock tmn crn0 tcen inttmn ton interval time 00h 00h 00h 00h 00h (c) when crn0 = ffh t count clock tmn crn0 tcen inttmn ton 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt request received interrupt request received remark n = 5, 6 225 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-6. timing of interval timer operation (3/3) (d) operated by crn0 transition (m < n) count clock tmn crn0 tcen inttmn ton n 00h m n ffh 00h m 00h nm crn0 transition tmn overflows since m < n. h (e) operated by crn0 transition (m > n) count clock tmn crn0 tcen inttmn ton n 1n n 00h 01h n m 1 m 00h 01h m crn0 transition h remark n = 5, 6 226 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud tin pin input 00h 01h 03h 05h n 1 01h 03h tmn count n crn0 inttmn 02h 04h 00h 02h n 10.4.2 operation as external event counter the external event counter counts the number of external clock pulses that are input to ti5/p100 and ti6/p101 pins with 8-bit timer counter 5, 6 (tm5, tm6). each time a valid edge specified in prescaler mode register 5, 6 (prm5, prm6) is input, tm5 and tm6 are incremented. the edge setting is selected to be either a rising edge or falling edge. if the counting of tm5 and tm6 matches the values of 8-bit compare register 50, 60 (cr50, cr60), the tm5 and tm6 are cleared to 0 and the interrupt request signal (inttm5, inttm6) is generated. inttm5 and inttm6 are generated each time when the value of the tm5 and tm6 matches with the value of cr50 and cr60. figure 10-7. timing of external event counter operation (with rising edge specified) remark n = 00h to ffh n = 5, 6 227 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud 10.4.3 operation as square wave output (8-bit resolution) a square wave having any frequency is output at the interval preset in 8-bit compare register 50, 60 (cr50, cr60). by setting bit 0 (toe5, toe6) of 8-bit timer mode control register 5, 6 (tmc5, tmc6) to 1, the output state of to5, to6 is inverted with the count preset in cr50, cr60 as the interval. therefore, a square wave output having any frequency (duty cycle = 50 %) is possible. 228 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud 10.4.4 operation as 8-bit pwm output by setting bit 6 (tmc56, tmc66) of 8-bit timer mode control register 5, 6 (tmc5, tmc6) to 1, the timer operates as a pwm output. pulses with the duty cycle determined by the value set in 8-bit compare register 50, 60 (cr50, cr60) is output from to5, to6. set the width of the active level of the pwm pulse in cr50, cr60. the active level can be selected by bit 1 (tmc51, tmc61) in tmc5, tmc6. the count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of prescaler mode register 5, 6 (prm5, prm6). the pwm output can be enabled and disabled by bit 0 (toe5, toe6) of tmc5, tmc6. (1) basic operation of the pwm output 229 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-8. timing of pwm output (a) basic operation (active level = h) (b) when crn0 = 0 count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h 00h 00h m 00h inactive level inactive level reload reload n + 2 00h (c) when crn0 = ffh remark n = 5, 6 count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h nn mn n n active level reload reload inactive level active level count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h m ffh ffh ffh ffh ffh active level inactive level n + 2 active level inactive level inactive level reload reload 230 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud count clock tmn crn0 crn0 read value tcen inttmn ton crn0 transition (n m) reload n n + 1n + 2 ffh 00h 01h m m + 1m + 2 ffh 00h 01h 02h m m + 1m + 2 n 02h mm h reload n m m count clock tmn crn0 crn0 read value tcen inttmn ton n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h 03h m m m + 1m + 2 crn0 transition (n m) reload reload nnmm count clock tmn crn0 crn0 read value tcen inttmn ton n n + 1n + 2 ffh 00h 01h n n + 1n + 2 ffh 00h 01h 02h n 02h n h m m m + 1m + 2 reload & crn0 transition (n m) reload mm m n figure 10-9. timing of operation based on crn0 transitions (a) when the crn0 value changes from n to m before tmn overflows (b) when the crn0 value changes from n to m after tmn overflows (c) when the crn0 value changes from n to m during two clocks (00h, 01h) immediately after tmn overflows remarks 1. n = 1, 2 2. crn0(m): master side, crn0(s): slave side 231 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud 10.4.5 operation as interval timer (16-bit operation) cascade connection (16-bit timer) mode by setting bit 4 (tmc64) of 8-bit timer mode control register 6 (tmc6) to 1, the timer enters the timer/counter mode with 16-bit resolution. with the count preset in 8-bit compare register 50, 60 (cr50, cr60) as the interval, the timer operates as an interval timer by repeatedly generating interrupt requests. 232 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud figure 10-10. cascade connection mode with 16-bit resolution count clock tm5 tm6 cr50 cr60 tce5 tce6 inttm5 to5 00h 00h 01h n + 1 n ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h n m 01h 02h m 1 m 00h b 00h enable operation starting count interval time interrupt request generated level inverted counter cleared operation stopped 10.5 cautions (1) error when the timer starts the time until the match signal is generated after the timer starts has a maximum error of one clock. the reason is the starting of 8-bit timer counter 5, 6 (tm5, tm6) is asynchronous with respect to the count pulse. figure 10-11. start timing of 8-bit timer counter tm5, tm6 count 00h 01h 02h 04h count pulse timer starts 03h 233 chapter 10 8-bit timer/event counter 5, 6 user s manual u13570ej3v0ud cr50, cr60 nm count pulse tm5, tm6 count x 1 x ffffh 0000h 0001h 0002h (2) operation after the compare register is changed while the timer is counting if the value after 8-bit compare register 50, 60 (cr50, cr60) changes is less than the value of the 8-bit timer counter (tm5, tm6), counting continues, overflows, and counting starts again from 0. consequently, when the value (m) after cr50, cr60 changes is less than the value (n) before the change, the timer must restart after cr50, cr60 changes. figure 10-12. timing after compare register changes during timer counting caution except when the ti5, ti6 input is selected, always set tce5 = 0, tce6 = 0 before setting the stop mode. remark n > x > m (3) tm5, tm6 read out during timer operation since the count clock stops temporarily when tm5 and tm6 are read during operation, select for the count clock a waveform with a high and low level that exceed 2 cycles of the cpu clock. when reading tm5 and tm6 in cascade connection mode, to avoid reading while the count is changing, take measures such as obtaining a count match by reading twice using software. 234 user s manual u13570ej3v0ud chapter 11 8-bit timer/event counter 7, 8 11.1 functions 8-bit timer/event counter 7, 8 (tm7, tm8) have the following two modes. mode using 8-bit timer/event counter 7, 8 (tm7, tm8) alone (individual mode) mode using the cascade connection (16-bit resolution: cascade connection mode) these two modes are described next. (1) mode using 8-bit timer/event counter 7, 8 alone (individual mode) the timer operates as an 8-bit timer/event counter. it can have the following functions. interval timer external event counter square wave output pwm output (2) mode using the cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by connecting in cascade. it can have the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square wave output with 16-bit resolution 235 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.2 configuration 8-bit timer/event counter 7, 8 are constructed from the following hardware. table 11-1. 8-bit timer/event counter 7, 8 configuration item configuration timer counter 8 bits 2 (tm7, tm8) register 8 bits 2 (cr70, cr80) timer output 2 (to7, to8) control register 8-bit timer mode control register 7 (tmc7) 8-bit timer mode control register 8 (tmc8) prescaler mode register 7 (prm7) prescaler mode register 8 (prm8) figure 11-1. block diagram of 8-bit timer/event counter 7, 8 (1/2) (1) 8-bit timer/event counter 7 internal bus internal bus tcl72 tcl71 tcl70 prescaler mode register 7 (prm7) 8-bit timer mode control register 7 (tmc7) toe7 tmc76 0 lvs7 lvr7 tmc7 toe7 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 7 f xx /2 9 ti7 tm8 compare match selector edge detector 8-bit compare register 70 (cr70) match 8-bit timer counter 7 (tm7) selector selector output controller mask circuit clear inttm8 inttm7 to tm8 to7 236 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-1. block diagram of 8-bit timer/event counter 7, 8 (2/2) (1) 8-bit timer/event counter 8 internal bus internal bus tcl82 tcl81 tcl80 prescaler mode register 8 (prm8) 8-bit timer mode control register 8 (tmc8) toe8 tmc86 tmc84 lvs8 lvr8 tmc8 toe8 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 7 f xx /2 9 ti8 tm7 overflow selector edge detector 8-bit compare register 80 (cr80) match 8-bit timer counter 8 (tm8) selector selector output controller mask circuit clear inttm8 to8 237 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud (1) 8-bit timer counter 7, 8 (tm7, tm8) tm7 and tm8 are 8-bit read-only registers that count the count pulses. the counter is incremented synchronous to the rising edge of the count clock. when the count is read out during operation, the count clock input temporarily stops and the count is read at that time. in the following cases, the count becomes 00h. <1> reset is input. <2> tcen is cleared. <3> tmn and crn0 match in the clear and start mode. caution in a cascade connection, the count becomes 00h by clearing bit 7 (tce7) of 8-bit timer mode control register 7 (tmc7) and bit 7 (tce8) of 8-bit timer mode control register 8 (tmc8). remark n = 7, 8 (2) 8-bit compare register (cr70, cr80) the value set in cr70 and cr80 are compared to the count in 8-bit timer counter 7 (tm7) and 8-bit timer counter 8 (tm8), respectively. if the two values match, interrupt requests (inttm7, inttm8) is generated (except in the pwm mode). the values of cr70 and cr80 can be set in the range of 00h to ffh, and can be written during counting. caution while the timers are connected in cascade, always set data after stopping the timer. to stop timer operation, clear both bit 7 of tmc7 (tce7) and bit 7 of tmc8 (tce8). 238 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.3 control registers the following four registers control 8-bit timer/event counter 7, 8. 8-bit timer mode control register 7, 8 (tmc7, tmc8) prescaler mode register 7, 8 (prm7, prm8) (1) 8-bit timer mode control register 7, 8 (tmc7, tmc8) the tmc7 and tmc8 registers make the following six settings. <1> controls the counting for 8-bit timer counter 7, 8 (tm7, tm8) <2> selects the operating mode of 8-bit timer counter 7, 8 (tm7, tm8) <3> selects the individual mode or cascade mode <4> sets the state of the timer output <5> controls the timer output or selects the active level during the pwm (free-running) mode <6> controls timer output tmc7 and tmc8 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc7 and tmc8 to 00h. figures 11-2 and 11-3 show the tmc7 format and tmc8 format respectively. 239 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-2. format of 8-bit timer mode control register 7 (tmc7) address: 0ff6ah after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc7 tce7 tmc76 0 0 lvs7 lvr7 tmc71 toe7 tce7 tm7 count control 0 counting is disabled (prescaler disabled) after the counter is cleared to 0. 1 start counting tmc76 tm7 operating mode selection 0 clear and start mode when tm7 and cr70 match. 1 pwm (free-running) mode lvs7 lvr7 timer output control by software 0 0 no change 0 1 reset (to 0). 1 0 set (to 1). 1 1 setting prohibited tmc71 other than pwm mode (tmc76 = 0) pwm mode (tmc76 = 1) timer output control active level selection 0 disable inversion operation active high 1 enable inversion operation active low toe7 timer output control 0 disable output (port mode) 1 enable output caution when selecting the tm7 operation mode using tmc76, stop the timer operation in advance. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce7 = 0. 2. if lvs7 and lvr7 are read after setting data, 0 is read. 240 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-3. format of 8-bit timer mode control register 8 (tmc8) address: 0ff6bh after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc8 tce8 tmc86 0 tmc84 lvs8 lvr8 tmc81 toe8 tce8 tm8 count control 0 counting is disabled (prescaler disabled) after the counter is cleared to 0. 1 start counting tmc86 tm8 operating mode selection 0 clear and start mode when tm8 and cr80 match 1 pwm (free-running) mode tmc84 individual mode or cascade connection mode selection 0 individual mode 1 cascade connection mode (connection with tm7) lvs8 lvr8 timer output control by software 0 0 no change 0 1 reset (to 0) 1 0 set (to 1) 1 1 setting prohibited tmc81 other than pwm mode (tmc86 = 0) pwm mode (tmc86 = 1) timer output control active level selection 0 disable inversion operation active high 1 enable inversion operation active low toe8 timer output control 0 disable output (port mode) 1 enable output caution when selecting the tm8 operation mode using tmc86 or selecting the discrete/cascade connection mode using tmc84, stop the timer operation in advance. to stop the timer operation during cascade connection, clear both bit 7 (tce7) of 8-bit timer mode control register 7 (tmc7) and bit 7 (tce8) of tmc8. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce8 = 0. 2. if lvs8 and lvr8 are read after setting data, 0 is read. 241 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud (2) prescaler mode register 7, 8 (prm7, prm8) this register sets the count clock of 8-bit timer counter 7, 8 (tm7, tm8) and the valid edge of ti7, ti8 inputs. prm7 and prm8 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets prm7 and prm8 to 00h. figure 11-4. format of prescaler mode register 7 (prm7) address: 0ff6eh after reset: 00h r/w symbol 76543210 prm7 00000 tcl72 tcl71 tcl70 tcl72 tcl71 tcl70 count clock selection 0 0 0 falling edge of ti7 0 0 1 rising edge of ti7 010f xx /4 (3.13 mhz) 011f xx /8 (1.56 mhz) 100f xx /16 (781 khz) 101f xx /32 (391 khz) 110f xx /128 (97.6 khz) 111f xx /512 (24.4 khz) cautions 1. if writing data different than that of prm7 is written, stop the timer beforehand. 2. be sure to set bits 3 to 7 of prm7 to 0. 3. when specifying the valid edge of ti7 for the count clock, set the count clock to f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 242 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-5. format of prescaler mode register 8 (prm8) address: 0ff6fh after reset: 00h r/w symbol 76543210 prm8 00000 tcl82 tcl81 tcl80 tcl82 tcl81 tcl80 count clock selection 0 0 0 falling edge of ti8 0 0 1 rising edge of ti8 010f xx /4 (3.13 mhz) 011f xx /8 (1.56 mhz) 100f xx /16 (781 khz) 101f xx /32 (391 khz) 110f xx /128 (97.6 khz) 111f xx /512 (24.4 khz) cautions 1. if writing data different than that of prm8 is written, stop the timer beforehand. 2. be sure to set bits 3 to 7 of prm8 to 0. 3. when specifying the valid edge of ti8 for the count clock, set the count clock to f xx /4 or below. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 243 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.4 operation 11.4.1 operation as interval timer (8-bit operation) the timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the preset count in 8-bit compare register 70, 80 (cr70, cr80). if the count in 8-bit timer counter 7, 8 (tm7, tm8) matches the value set in cr70, cr80, simultaneous to clearing the value of tm7, tm8 to 0 and continuing the count, the interrupt request signal (inttm7, inttm8) is generated. the tm7 and tm8 count clocks can be selected with bits 0 to 2 (tcln0 to tcln2) in prescaler mode register 7, 8 (prm7, prm8). 244 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-6. timing of interval timer operation (1/3) (a) basic operation start count clear clear interrupt request received interrupt request received t 00h 01h n 00h 01h n 00h 01h n n n n n interval time interval time interval time count clock tmn count crn0 inttmn ton tcen remarks 1. interval time = (n + 1) t; n = 00h to ffh 2. n = 7, 8 245 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-6. timing of interval timer operation (2/3) (b) when crn0 = 00h t count clock tmn crn0 tcen inttmn ton interval time 00h 00h 00h 00h 00h (c) when crn0 = ffh t count clock tmn crn0 tcen inttmn ton 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt request received interrupt request received remark n = 7, 8 246 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-6. timing of interval timer operation (3/3) (d) operated by crn0 transition (m < n) count clock tmn crn0 tcen inttmn ton n 00h m n ffh 00h m 00h nm crn0 transition tmn overflows since m < n h (e) operated by crn0 transition (m > n) count clock tmn crn0 tcen inttmn ton n 1n n 00h 01h n m 1 m 00h 01h m crn0 transition h remark n = 7, 8 247 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.4.2 operation as external event counter the external event counter counts the number of external clock pulses that are input to ti7/p102 and ti8/p103 pins with 8-bit timer counter 7, 8 (tm7, tm8). each time a valid edge specified in prescaler mode register 7, 8 (prm7, prm8) is input, tm7 and tm8 are incremented. the edge setting is selected to be either a rising edge or falling edge. if the counting of tm7 and tm8 matches with the values of 8-bit compare register 70, 80 (cr70, cr80), the tm7 and tm8 are cleared to 0 and the interrupt request signal (inttm7, inttm8) is generated. inttm7 and inttm8 are generated each time when the value of the tm7 and tm8 matches with the value of cr70 and cr80. figure 11-7. timing of external event counter operation (with rising edge specified) remark n = 00h to ffh n = 7, 8 tin pin input 00h 01h 03h 05h n 1 01h 03h tmn count n crn0 inttmn 02h 04h 00h 02h n 248 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.4.3 operation as square wave output (8-bit resolution) a square wave having any frequency is output at the interval preset in 8-bit compare register 70, 80 (cr70, cr80). by setting bit 0 (toe7, toe8) of 8-bit timer mode control register 7, 8 (tmc7, tmc8) to 1, the output state of to7, to8 is inverted with the count preset in cr70, cr80 as the interval. therefore, a square wave output having any frequency (duty cycle = 50 %) is possible. 249 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.4.4 operation as 8-bit pwm output by setting bit 6 (tmc76, tmc86) of 8-bit timer mode control register 7, 8 (tmc7, tmc8) to 1, the timer operates as a pwm output. pulses with the duty cycle determined by the value set in 8-bit compare register 70, 80 (cr70, cr80) is output from to7, to8. set the width of the active level of the pwm pulse in cr70, cr80. the active level can be selected by bit 1 (tmc71, tmc81) in tmc7, tmc8. the count clock can be selected by bits 0 to 2 (tcln0 to tcln2) of prescaler mode register 7, 8 (prm7, prm8). the pwm output can be enabled and disabled by bit 0 (toe7, toe8) of tmc7, tmc8. (1) basic operation of the pwm output 250 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-8. timing of pwm output (a) basic operation (active level = h) (b) when crn0 = 0 count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h 00h 00h m 00h inactive level inactive level reload reload n + 2 00h (c) when crn0 = ffh remark n = 7, 8 count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h m ffh ffh ffh ffh ffh active level inactive level n + 2 active level inactive level inactive level reload reload count clock tmn crn0 crn0 read value tcen inttmn ton 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h nn mn n n active level reload reload inactive level active level 251 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-9. timing of operation based on crn0 transitions (a) when the crn0 value changes from n to m before tmn overflows (b) when the crn0 value changes from n to m after tmn overflows (c) when the crn0 value changes from n to m during two clocks (00h, 01h) immediately after tmn overflows remarks 1. n = 7, 8 2. crn0 (m): master side, crn0 (s): slave side tmn count clock crn0 tcen inttmn ton n n+2 n+2 ffh 00h 01h n n+2 n+2 ffh 00h 01h 02h n 02h n h 03h m m m+1 m+2 crn0 transition (n m) reload reload crn0 read value nnmm tmn count clock crn0 tcen inttmn ton n n+2 n+2 ffh 00h 01h n n+2 n+2 ffh 00h 01h 02h n 02h n h m m m+1 m+2 reload & crn0 transition (n m) reload crn0 read value nmm m tmn count clock crn0 crn0 read value tcen inttmn ton crn0 transition (n m) reload reload n n+2 n+2 ffh 00h 01h m m+1 m+2 ffh 00h 01h 02h m m+1 m+2 n 02h mm h nm m 252 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud 11.4.5 operation as interval timer (16-bit operation) cascade connection (16-bit timer) mode by setting bit 4 (tmc84) of 8-bit timer mode control register 8 (tmc8) to 1, the timer enters the timer/counter mode with 16-bit resolution. with the count preset in 8-bit compare register 70, 80 (cr70, cr80) as the interval, the timer operates as an interval timer by repeatedly generating interrupt requests. 253 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud figure 11-10. cascade connection mode with 16-bit resolution count clock tm7 tm8 cr70 cr80 tce7 tce8 inttm7 to7 00h 00h 01h n + 1 n ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h n m 01h 02h m 1 m 00h b 00h enable operation starting count interval time interrupt request generated level inverted counter cleared operation stopped 11.5 cautions (1) error when the timer starts the time until the match signal is generated after the timer starts has a maximum error of one clock. the reason is the starting of 8-bit timer counter 7, 8 (tm7, tm8) is asynchronous with respect to the count pulse. figure 11-11. start timing of 8-bit timer counter register tm7, tm8 count 00h 01h 02h 04h count pulse timer starts 03h 254 chapter 11 8-bit timer/event counter 7, 8 user s manual u13570ej3v0ud (2) operation after the compare register is changed while the timer is counting if the value after 8-bit compare register 70, 80 (cr70, cr80) changes is less than the value of the 8-bit timer counter (tm7, tm8), counting continues, overflows, and counting starts again from 0. consequently, when the value (m) after cr70, cr80 changes is less than the value (n) before the change, the timer must restart after cr70, cr80 changes. figure 11-12. timing after compare register changes during timer counting caution except when the ti7, ti8 input is selected, always set tce7 = 0, tce8 = 0 before setting the stop mode. remark n > x > m (3) tm7, tm8 read out during timer operation since the count clock stops temporarily when tm7 and tm8 are read during operation, select for the count clock a waveform with a high and low level that exceed 2 cycles of the cpu clock. when reading tm7 and tm8 in cascade connection mode, to avoid reading while the count is changing, take measures such as obtaining a count match by reading twice using software. cr70, cr80 nm count pulse tm7, tm8 count x 1 x ffffh 0000h 0001h 0002h 255 user s manual u13570ej3v0ud chapter 12 watch timer 12.1 function the watch timer has the following functions: watch timer interval timer the watch timer and interval timer functions can be used at the same time. (1) watch timer the watch timer generates an interrupt request (intwt) at time intervals of 0.5 seconds by using the main system clock of 4.19 mhz or subsystem clock of 32.768 khz. caution the time interval of 0.5 seconds cannot be created with the 12.5 mhz main system clock. use the 32.768 khz subsystem clock to create the 0.5-second time interval. (2) interval timer the watch timer generates an interrupt request (inttm3) at time intervals specified in advance. table 12-1. interval time of interval timer interval time f xx = 12.5 mhz f xx = 4.19 mhz f xt = 32.768 khz 2 11 1/f xx 164 s 488 s 488 s 2 12 1/f xx 328 s 977 s 977 s 2 13 1/f xx 655 s 1.95 ms 1.95 ms 2 14 1/f xx 1.31 ms 3.91 ms 3.91 ms 2 15 1/f xx 2.62 ms 7.81 ms 7.81 ms 2 16 1/f xx 5.24 ms 15.6 ms 15.6 ms remark f xx : main system clock frequency f xt : subsystem clock oscillation frequency 256 chapter 12 watch timer user s manual u13570ej3v0ud 12.2 configuration the watch timer consists of the following hardware. table 12-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm) figure 12-1. block diagram of watch timer selector selector selector internal bus 5-bit counter 9-bit prescaler f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 9 f w wtm0 intwt inttm3 wtm1 wtm3 wtm4 wtm5 wtm6 wtm7 watch timer mode control register (wtm) f xx /2 7 f xt clear clear remark f xx : main system clock frequency f xt : subsystem clock oscillation frequency 257 chapter 12 watch timer user s manual u13570ej3v0ud 12.3 control register watch timer mode control register (wtm) this register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. 258 chapter 12 watch timer user s manual u13570ej3v0ud figure 12-2. format of watch timer mode control register (wtm) address: 0ff9ch after reset: 00h r/w symbol 765432<1><0> wtm wtm7 wtm6 wtm5 wtm4 wtm3 0 wtm1 wtm0 wtm7 selects count clock of watch timer 0 main system clock (f xx /2 7 ) 1 subsystem clock (f xt ) wtm6 wtm5 wtm4 selects interval time of prescaler 0002 4 /f w (488 s) 0012 5 /f w (977 s) 0102 6 /f w (1.95 ms) 0112 7 /f w (3.91 ms) 1002 8 /f w (7.81 ms) 1012 9 /f w (15.6 ms) other than above setting prohibited wtm3 selects set time of watch flag 02 14 /f w (0.5 s) 12 5 /f w (977 s) wtm1 controls operation of 5-bit counter 0 clear after operation stop 1 start wtm0 enables operation of watch timer 0 operation stop (clear both prescaler and timer) 1 operation enable cautions 1. stop the timer operation before overwriting wtm. 2. do not overwrite wtm when both the watch timer and interval timer are being used. if the timer is stopped to overwrite wtm, both the prescaler and timer are cleared, causing an error to occur in the watch timer interrupt (intwt). remarks 1. f w : watch timer clock frequency (f xx /2 7 or f xt ) f xx : main system clock frequency f xt : subsystem clock oscillation frequency 2. figures in parentheses apply to operation with f w = 32.768 khz. 259 chapter 12 watch timer user s manual u13570ej3v0ud 12.4 operation 12.4.1 operation as watch timer the watch timer operates with time intervals of 0.5 seconds with the main system clock (4.19 mhz) or subsystem clock (32.768 khz). the watch timer generates an interrupt request (intwt) at fixed time intervals. the count operation of the watch timer is started when bits 0 (wtm0) and 1 (wtm1) of the watch timer mode control register (wtm) are set to 1. when these bits are cleared to 0, the 5-bit counter is cleared, and the watch timer stops the count operation. only the watch timer can be started from zero seconds by clearing wtm1 to 0 when the interval timer operates at the same time. in this case, however, the 9-bit prescaler is not cleared. therefore, an error of up to 1/f w or 2 9 1/f w occurs at the first overflow (intwt) after the watch timer has been started from zero seconds. 12.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt request (inttm3) at intervals specified by a count value set in advance. the interval time can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 12-3. interval time of interval timer wtm6 wtm5 wtm4 interval time f xx = 12.5 mhz f xx = 4.19 mhz f xt = 32.768 khz 0002 4 1/f w 164 s 488 s 488 s 0012 5 1/f w 328 s 977 s 977 s 0102 6 1/f w 655 s 1.95 ms 1.95 ms 0112 7 1/f w 1.31 ms 3.91 ms 3.91 ms 1002 8 1/f w 2.62 ms 7.81 ms 7.81 ms 1012 9 1/f w 5.24 ms 15.6 ms 15.6 ms other than above setting prohibited cautions 1. stop the timer operation before overwriting wtm. 2. do not overwrite wtm when both the watch timer and interval timer are being used. if the timer is stopped to overwrite wtm, both the prescaler and timer are cleared, causing an error to occur in the watch timer interrupt (intwt). remark f w : watch timer clock frequency (f xx /2 7 or f xt ) f xx : main system clock frequency f xt : subsystem clock oscillation frequency 260 chapter 12 watch timer user s manual u13570ej3v0ud figure 12-3. operation timing of watch timer/interval timer caution when enabling operation of the watch timer mode control register (wtm), watch timer, and 5- bit counter, the time until the first watch timer interrupt request (intwt) is generated is not exactly the same time as set by bits 4 to 6 of wtm (wtm4 to wtm6). this is because the 5-bit counter starts counting 1 cycle after 9-bit prescaler output. following the first intwt generation, the intwt signal is generated at the set interval time. remark n: number of interval timer operations 0h start overflow overflow watch timer count clock watch timer interrupt intwt interval timer interrupt inttm3 interrupt time of watch timer interrupt time of watch timer interval time (t) interval time (t) nt nt 261 user s manual u13570ej3v0ud chapter 13 watchdog timer the watchdog timer detects runaway programs. program or system errors are detected by the generation of watchdog timer interrupts. therefore, at each location in the program, the instruction that clears the watchdog timer (starts the count) within a constant time is input. if the watchdog timer overflows without executing the instruction that clears the watchdog timer within the set period, a watchdog timer interrupt (intwdt) is generated to signal a program error. 13.1 configuration figure 13-1 shows a block diagram of the watchdog timer. figure 13-1. watchdog timer block diagram note write 1 to bit 7 (run) of the watchdog timer mode register (wdm). remark f clk : internal system clock (f xx to f xx /8), and subsystem clock watchdog timer f clk f clk /2 21 f clk /2 20 f clk /2 19 f clk /2 17 intwdt selector clear signal run note halt idle stop 262 chapter 13 watchdog timer user s manual u13570ej3v0ud 13.2 control register watchdog timer mode register (wdm) the wdm is the 8-bit register that controls watchdog timer operation. to prevent the watchdog timer from erroneously clearing this register due to a runaway program, this register is only written by a special instruction. this special instruction has a special code format (4 bytes) in the mov wdm, #byte instruction. writing takes place only when the third and fourth op codes are mutual 1 s complements. if the third and fourth op codes are not mutual 1 s complements and not written, the operand error interrupt is generated. in this case, the return address saved in the stack is the address of the instruction that caused the error. therefore, the address that caused the error can be identified from the return address saved in the stack. if returning by simply using the retb instruction from the operand error, an infinite loop results. since an operand error interrupt is generated only when the program is running wild (the correct special instruction is only generated when mov wdm, #byte is described in the ra78k4 nec electronics assembler), make the program initialize the system. other write instructions (mov wdm, a; and wdm, #byte; set1 wdm.7, etc.) are ignored and nothing happens. in other words, wdm is not written, and interrupts, such as operand error interrupts, are not generated. after a system reset (reset input), when the watchdog timer starts (when the run bit is set to 1), the wdm contents cannot change. only a reset can stop the watchdog timer. the watchdog timer can be cleared by a special instruction. the wdm can be read by 8-bit data transfer instructions. reset input sets wdm to 00h. figure 13-2 shows the wdm format. 263 chapter 13 watchdog timer user s manual u13570ej3v0ud figure 13-2. watchdog timer mode register (wdm) format address: 0ffc2h after reset: 00h r/w symbol 76543210 wdm run 0 0 wdt4 0 wdt2 wdt1 0 run watchdog timer operation setting 0 stops the watchdog timer. 1 clears the watchdog timer and starts counting. wdt4 watchdog timer interrupt request priority 0 watchdog timer interrupt request < nmi pin input interrupt request 1 watchdog timer interrupt request > nmi pin input interrupt request wdt2 wdt1 count clock overflow time [ms] (f clk = 12.5 mhz) 00f clk /2 17 10.5 01f clk /2 19 41.9 10f clk /2 20 83.9 11f clk /2 21 167.8 cautions 1. only the special instruction (mov wdm, #byte) can write to the watchdog timer mode register (wdm). 2. when writing to wdm to set the run bit to 1, write the same value every time. even if different values are written, the contents written the first time cannot be updated. 3. when the run bit is set to 1, it cannot be reset to 0 by the software. remark f clk : internal system clock (f xx to f xx /8), and subsystem clock 264 chapter 13 watchdog timer user s manual u13570ej3v0ud 13.3 operations 13.3.1 count operation the watchdog timer is cleared by setting the run bit of the watchdog timer mode register (wdm) to 1 to start counting. after the run bit is set to 1, when the overflow time set by bits wdt2 and wdt1 in wdm has elapsed, a non-maskable interrupt (intwdt) is generated. if the run bit is reset to 1 before the overflow time elapses, the watchdog timer is cleared, and counting restarts. 13.3.2 interrupt priority order the watchdog timer interrupt (intwdt) can be specified as either maskable or non-maskable according to the interrupt selection control register (snmi) setting. when writing 0 to bit 1 (sdwt) of snmi, the watchdog timer interrupt can be used as a non-maskable interrupt. in addition to the intwdt, the non-maskable interrupts include the interrupt (nmi) from the nmi pin. by setting bit 4 of the watchdog timer mode register (wdm), the acceptance order when intwdt and nmi are simultaneously generated can be set. if accepting nmi is given priority, even if intwdt is generated in an nmi processing program that is executing, intwdt is not accepted, but is accepted after the nmi processing program ends. 265 chapter 13 watchdog timer user s manual u13570ej3v0ud 13.4 cautions 13.4.1 general cautions when using watchdog timer (1) the watchdog timer is one way to detect runaway operation, but all runaway operations cannot be detected. therefore, in a device that particularly demands reliability, the runaway operation must be detected early not only by the on-chip watchdog timer but by an externally attached circuit; and when returning to the normal state or while in the stable state, processing like stopping the operation must be possible. (2) the watchdog timer cannot detect runaway operation in the following cases. <1> when the watchdog timer is cleared in a timer interrupt servicing program <2> when there are successive temporary stores of interrupt requests and macro services (see 23.9 when interrupt requests and macro service are temporarily held pending ) <3> when runaway operation is caused by logical errors in the program (when each module in the program operates normally, but the entire system does not operate properly), and when the watchdog timer is periodically cleared <4> when the watchdog timer is periodically cleared by an instruction group that is executed during runaway operation <5> when the stop, halt, or idle mode is the result of runaway operation <6> when the watchdog timer also runs wild when the cpu runs wild because of introduced noise in cases <1>, <2>, and <3>, detection becomes possible by correcting the program. in case <4>, the watchdog timer can be cleared only by the 4-byte special instruction. similarly in <5>, if there is no 4-byte special instruction, the stop, halt, or idle mode cannot be set. since the result of the runaway operation is to enter state <2>, three or more bytes of consecutive data must be a specific pattern (example, bt pswl.bit, $$). therefore, the results of <4>, <5>, and the runaway operation are believed to very rarely enter state <2>. 13.4.2 cautions about pd784218a subseries watchdog timer (1) only the special instruction (mov wdm, #byte) can write to the watchdog timer mode register (wdm). (2) if the run bit is set to 1 by writing to the watchdog timer mode register (wdm), write the same value every time. even when different values are written, the contents written the first time cannot be changed. (3) if the run bit is set to 1, it cannot be reset to 0 by the software. 266 user s manual u13570ej3v0ud chapter 14 a/d converter 14.1 functions the a/d converter converts analog inputs to digital values, and is configured by eight 8-bit resolution channels (ani0 to ani7). successive approximation is used as the conversion method, and conversion results are saved in the 8-bit a/d conversion result register (adcr). a/d conversion operation is activated by the following two methods. (1) hardware start conversion is started by trigger input (p03) (rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting the a/d converter mode register (adm). a/d converter selects one channel for analog input from ani0 to ani7 to perform a/d conversion. at the hardware start time, a/d conversion stops after the a/d conversion operation is completed, and an interrupt request (intad) is issued. at the software start time, the a/d conversion operation is repeated. each time one a/d conversion is completed, an interrupt request (intad) is issued. 14.2 configuration the a/d converter has the following hardware configuration. table 14-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) control registers a/d converter mode register (adm) a/d converter input selection register (adis) registers successive approximation register (sar) a/d conversion result register (adcr) 267 chapter 14 a/d converter user s manual u13570ej3v0ud figure 14-1. a/d converter block diagram note valid edge specified with bit 3 of the egp0, egn0l registers (refer to figure 22-1 format of external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0) ). ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 selector a/d converter mode register (adm) trigger enable sample & hold circuit 3 adcs internal bus edge detector edge detector controller series resistor string av dd voltage comparator tap selector intad intp3 successive approximation register (sar) a/d converter input selection register (adis) adis2 adis1 adis0 intp3/p03 trg fr2 fr1 fr0 ega1 ega0 adce a / d conversion result register (adcr) av ref0 av ss note 268 chapter 14 a/d converter user s manual u13570ej3v0ud (1) successive approximation register (sar) compares the voltage of the analog input with the voltage tap (comparison voltage) from the series resistor string, and retains the result from the most significant bit (msb). when retaining the result to the least significant bit (lsb) (a/d conversion end), the contents of the sar register are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr) retains a/d conversion results. at the end of each a/d conversion operation, the conversion result from the successive approximation register is loaded. adcr is read with an 8-bit memory manipulation instruction. reset input makes its contents undefined. (3) sample & hold circuit samples analog input signals one by one as they are sent from the input circuit, and sends them to the voltage comparator. the sampled analog input voltages are saved during a/d conversion. (4) voltage comparator compares the analog input voltage with the output voltage of the series resistor string. (5) series resistor string connected between av ref0 and av ss , generates the voltage that is compared with that of analog input. (6) ani0 to ani7 pins eight analog input channels used for inputting analog data to the a/d converter for a/d conversion. pins not selected for analog input with the a/d converter input selection register (adis) can be used as input ports. cautions 1. use ani0 to ani7 input voltages within the rated voltage range. inputting a voltage equal to or greater than av ref0 , or equal to or smaller than av ss (even if within the absolute maximum rated range) will cause the channel? conversion values to become undefined, or may affect the conversion values of other channels. 2. analog input (an10 to an17) pins alternate with input port (p10 to p17) pins. when performing an a/d conversion with the selection of any one of inputs from an10 to an17, do not execute input instructions to port 1 during conversion. conversion resolution may decrease. when a digital pulse is applied to the pin which adjoins a pin in the a/ d conversion, an expected a/d conversion value may not be acquired due to the coupling noise. therefore do not apply a pulse to the pin which adjoins the pin in the a/d conversion. (7) av ref0 pin used to input the reference voltage of the a/d converter. based on the voltage applied between av ref0 and av ss , signals input to ani0 to ani7 are converted to digital signals. (8) av ss pin ground pin of the a/d converter. always use this pin at the same electric potential as the v ss pin, even when not using the a/d converter. 269 chapter 14 a/d converter user s manual u13570ej3v0ud (9) av dd pin analog power supply pin of the a/d converter. always use this pin at the same electric potential as the v dd pin, even when not using the a/d converter. 14.3 control registers the a/d converter controls the following two registers. a/d converter mode register (adm) a/d converter input selection register (adis) (1) a/d converter mode register (adm) used to set the a/d conversion time of analog input to be converted, start/stop of conversion operation, and external triggers. adm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adm to 00h. 270 chapter 14 a/d converter user s manual u13570ej3v0ud figure 14-2. a/d converter mode register (adm) format address: 0ff80h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> adm adcs trg fr2 fr1 fr0 ega1 ega0 adce adcs a/d conversion control 0 conversion stop 1 conversion enable trg software start/hardware start selection 0 software start 1 hardware start fr2 fr1 fr0 a/d conversion time selection number of clocks @f xx = 12.5 mhz @f xx = 6.25 mhz 0 0 0 144/f xx setting prohibited 23.0 s 0 0 1 120/f xx setting prohibited 19.2 s 0 1 0 96/f xx setting prohibited 15.4 s 1 0 0 288/f xx 23.0 s 46.1 s 1 0 1 240/f xx 19.2 s 38.4 s 1 1 0 192/f xx 15.4 s 30.7 s other than above setting prohibited ega1 ega0 external trigger signal valid edge selection 0 0 no edge detection 0 1 detection of falling edge 1 0 detection of rising edge 1 1 detection of both falling and rising edges adce reference voltage circuit control 0 circuit stopped note 1 circuit operating note the reference voltage circuit operates when adcs is 1. 271 chapter 14 a/d converter user s manual u13570ej3v0ud cautions 1. set the a/d conversion time as follows: when v dd = 2.7 v to 5.5 v: 14 s or more when v dd = 2.0 v to 2.7 v: 28 s or more when v dd = 1.9 v to 2.0 v: 48 s or more (flash version only, such as pd78f4218a) when v dd = 1.8 v to 2.0 v: 48 s or more (mask version only, such as pd784218a) 2. when overwriting fr0 to fr2 to different data, temporarily end the a/d conversion operations before continuing. 3. if adcs is set after adce is set and the following time has elapsed, the first a/d conversion value can be used. when v dd = 2.7 v to 5.5 v: 14 s or more when v dd = 2.0 v to 2.7 v: 28 s or more when v dd = 1.9 v to 2.0 v: 48 s or more (flash version only, such as pd78f4218a) when v dd = 1.8 v to 2.0 v: 48 s or more (mask version only, such as pd784218a) 4. if adcs is set when adce = 0, the first a/d conversion value is undefined. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency (2) a/d converter input selection register (adis) used to specify the input ports for analog signals to be a/d converted. adis can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adis to 00h. figure 14-3. a/d converter input selection register (adis) format address: 0ff81h after reset: 00h r/w symbol 76543210 adis 00000 adis2 adis1 adis0 adis2 adis1 adis0 analog input channel setting 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7 272 chapter 14 a/d converter user s manual u13570ej3v0ud 14.4 operations 14.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the a/d converter input selection register (adis). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> after sampling has been performed for a certain time, the sample & hold circuit enters the hold status, and the input analog voltage is held until a/d conversion ends. <4> bit 7 of the successive approximation register (sar) is set, and the tap selector brings the series resistor string voltage tap to half the av ref0 level. <5> the series resistor string voltage tap and the analog input voltage difference are compared by the voltage comparator. if the analog input is equal to or greater than half the av ref0 level, it is set to the msb of sar. if the analog input is equal to or smaller than one half the av ref0 level, the msb is reset. <6> next, bit 6 of sar is automatically set, and the next comparison is started. the series resistor string voltage tap is selected as shown below according to bit 7 to which a result has already been set. bit 7 = 1: (3/4) av ref0 bit 7 = 0: (1/4) av ref0 the voltage tap and analog input voltage are compared, and bit 6 of sar is manipulated according to the result, as follows. analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 <7> comparisons of this kind are repeated until bit 0 of sar. <8> when comparison of all eight bits is completed, the valid digital result remains in sar, and this value is transferred to the a/d conversion result register (adcr) and latched. at the same time, it is possible to have an a/d conversion end interrupt request (intad) issued. caution the value of the first a/d conversion is undefined if adcs is set when bit 0 (adce) of the a/ d converter mode register (adm) is 0. 273 chapter 14 a/d converter user s manual u13570ej3v0ud figure 14-4. basic operations of a/d converter a/d conversion is performed continuously until adm bit 7 (adcs) is reset to 0 by software. if a write operation to adm or adis is performed during a/d conversion, the conversion operation is reset and conversion restarts from the beginning if the adcs bit is set to 1. reset input makes adcr undefined. if bit 0 (adce) of the a/d converter mode register is not set to 1, the value of the first a/d conversion is undefined immediately after a/d conversion starts. poll the a/d conversion end interrupt request (intad) and take measures such as discarding the first a/d conversion result. sar adcr intad a/d converter operation sampling time sampling a /d conversion conversion time undefined 80h c0h or 40h conversion result conversion result 274 chapter 14 a/d converter user s manual u13570ej3v0ud 14.4.2 input voltage and conversion result the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (value saved in a/d conversion result register (adcr)) is expressed by the following equation. adcr = int ( 256 + 0.5) or (adcr 0.5) v in < (adcr + 0.5) remark int( ): function returning the integer portion of the value in parentheses v in : analog input voltage av ref0 :av ref0 pin voltage adcr: a/d conversion result register (adcr) value figure 14-5 shows the relationship between analog input voltage and the a/d conversion result. figure 14-5. relationship between analog input voltage and a/d conversion result v in av ref0 a v ref0 256 av ref0 256 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 a/d conversion result (adcr) input voltage/av ref0 275 chapter 14 a/d converter user s manual u13570ej3v0ud 14.4.3 operation mode of a/d converter one channel is selected from ani0 to ani7 by the a/d converter input selection register (adis) and start the a/d conversion. a/d conversion can be started in the following two ways. hardware start: conversion start by trigger input (p03) software start: conversion start by setting adm the a/d conversion result is saved in the a/d conversion result register (adcr), and an interrupt request signal (intad) is issued at the same time. (1) a/d conversion operation by hardware start the a/d conversion operation can be made to enter the standby status by setting ??to bit 6 (trg) and bit 7 (adcs) of the a/d converter mode register (adm). when an external trigger signal (p03) is input, conversion of the voltage applied to the analog input pin set with adis begins. when the a/d conversion ends, the conversion result is saved in the a/d conversion result register (adcr), and an interrupt request signal (intad) is issued. when the a/d conversion operation that was started completes the first a/d conversion, no other a/d conversion operation is started unless an external trigger signal is input. when adcs is rewritten during the operation of a/d conversion, that operation is interrupted and waits until an external trigger signal is input. when the external trigger signal is input again, the a/d conversion is performed from the beginning. when adcs is rewritten during the standby for a/d conversion, the operation of a/d conversion starts at the time when the next external trigger input signal is input. if, during a/d conversion, data that adcs is 0 is written to adm, a/d conversion is immediately stopped. caution when p03/intp3 is used as the external trigger input (p03), specify a valid edge with bits 1 and 2 (ega0 and ega1) of the a/d converter mode register (adm) and set 1 to the interrupt mask flag (pmk3). figure 14-6. a/d conversion operation by hardware start (with falling edge specified) note if bit 0 (adce) of the a/d converter mode register is not set to 1, the value of the first a/d conversion is undefined immediately after a/d conversion starts. poll the a/d conversion end interrupt request (intad) and take measures such as discarding the first a/d conversion result. remark n = 0, 1, ...... , 7 m = 0, 1, ...... , 7 adm write adcs = 1, trg = 1 standby status anin p03 a /d conversion adcr intad anin note anin anin anim note anim anin anin standby status standby status adm write adcs = 1, trg = 1 anim anim anim 276 chapter 14 a/d converter user s manual u13570ej3v0ud (2) a/d conversion operation by software start a/d conversion of the voltage applied to the analog input pin specified with adis is started by setting 0 to bit 6 (trg) and 1 to bit 7 (adcs) of the a/d converter mode register (adm). when a/d conversion ends, the conversion result is saved in the a/d conversion result register (adcr), and an interrupt request signal (intad) is issued. when an a/d conversion operation that was started completes the first a/d conversion, the next a/d conversion starts immediately. a/d conversion operations are performed continuously until new data is written to adm. if, during a/d conversion, adcs is rewritten, the a/d conversion operation being performed at that time is interrupted, and a/d conversion of the newly selected analog input channels starts. if, during a/d conversion, data where adcs is 0 is written to adm, the a/d conversion operation is immediately stopped. figure 14-7. a/d conversion operation by software start note if bit 0 (adce) of the a/d converter mode register is not set to 1, the value of the first a/d conversion is undefined immediately after a/d conversion starts. poll the a/d conversion end interrupt request (intad) and take measures such as discarding the first a/d conversion result. remark n = 0, 1, ...... , 7 m = 0, 1, ...... , 7 setting adm adcs = 1, trg = 0 a /d conversion adcr intad anin note anin anim note anin anim anim anin anin adis rewrite adcs = 0 conversion operation interrupted and conver- sion result not left over stop 277 chapter 14 a/d converter user s manual u13570ej3v0ud 14.5 cautions (1) current consumption standby mode the a/d converter operation is stopped during the standby mode. at this time, the current consumption can be reduced by setting bit 7 (adcs) of the a/d converter mode register (adm) to 0 or by stopping the reference voltage circuit (bit of adm (adce) = 0). the method to reduce the current consumption in the standby mode is shown in figure 14-8. figure 14-8. method to reduce current consumption in standby mode (2) ani0 to ani7 input range use ani0 to ani7 input voltages within the rated voltage range. inputting a voltage equal to or greater than av ref0 , or equal to or smaller than av ss (even if within the absolute maximum rated range) will cause the channel s conversion values to become undefined, or may affect the conversion values of other channels. (3) contention operation <1> contention with adcr read due to contention between a/d conversion result register (adcr) write and instruction at conversion end the read operation to adcr is prioritized. after the read operation, a new conversion result is written to adcr. <2> contention between adcr write and external trigger signal input at conversion end external trigger signals cannot be received during a/d conversion. therefore, external trigger signals during adcr write operation are not received. <3> contention between adcr write and a/d converter mode register (adm) write, or between a/d converter input selection register (adis) write at conversion end the write operation to adm or adis is prioritized. write to adcr is not performed. moreover, no interrupt signal (intad) is issued at conversion end. series resistor string reference voltage circuit adcs adce p-ch av dd av ss 278 chapter 14 a/d converter user s manual u13570ej3v0ud (4) anti-noise measures attention must be paid to noise fed to av ref0 and ani0 to ani7 to preserve the 8-bit resolution. the influence of noise grows proportionally to the output impedance of the analog input source. therefore, it is recommended to connect c externally, as shown in figure 14-9. figure 14-9. handling of analog input pin (5) ani0/p10 to ani7/p17 the analog input pins (ani0 to ani7) can also be used as an input port pin (p10 to p17). if any of ani0 to ani7 is selected and a/d conversion is performed, do not execute input instructions to port1 during conversion. this would result in a lowered resolution. moreover, if a digital pulse is applied to pins adjacent to the pin for which a/d conversion is being performed, the a/d conversion value will not be obtained as expected because of coupling noise. therefore, do not apply a pulse to pins adjacent to the pin for which a/d conversion is being performed. (6) input impedance of av ref0 pin a series resistor string of approximately 46 k ? is connected between the av ref0 and av ss pins. therefore, if the output impedance of the reference voltage source is high, connecting in parallel a series resistor string between the av ref0 and av ss pins will result in a large reference voltage error. ani0 to ani7 av ref0 v dd av dd av ss v ss reference voltage input c = 100 to 1,000 pf if there is the possibility that noise equal to or greater than av ref0 , or equal to or smaller than av ss , may enter, clamp with a diode having a small v f (0.3 v or less). v dd 279 chapter 14 a/d converter user s manual u13570ej3v0ud (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the a/d converter input select register (adis) is changed. therefore, if the analog input pin is changed during a/d conversion, the a/d conversion result for the analog input immediately preceding the write operation to adis, and adif may be set. also, if adif is read immediately after adis is written to, adif may be set even if a/d conversion for the analog input following the write operation to adis is not completed. these facts should be kept in mind. moreover, if a/d conversion is stopped once and then resumed, clear adif before resuming conversion. figure 14-10. a/d conversion end interrupt generation timing note if bit 0 (adce) of the a/d converter mode register is not set to 1, the value of the first a/d conversion is undefined immediately after a/d conversion starts. poll the a/d conversion end interrupt request (intad) and take measures such as discarding the first a/d conversion result. remark n = 0, 1, , 7 m = 0, 1, , 7 (8) bit 0 (adce) of a/d converter mode register (adm) setting adce to 1 allows the value of the first a/d conversion immediately after a/d conversion operation start to be used. adm write (anin conversion start) anin a/d conversion adcr intad anin anim anim anin note anin anim note anim adis write (anim conversion start) adif is set, but anim conversion has not completed 280 chapter 14 a/d converter user s manual u13570ej3v0ud (9) conversion results immediately after a/d conversion is started if bit 7 (adcs0) of the a/d converter mode register (adm) is set to 1 without setting bit 0 (adce) to 1, the value of the first a/d conversion is undefined immediately after the a/d conversion operation starts. poll the a/d conversion end interrupt request (intad) and take measures such as discarding the first conversion result. figure 14-11. conversion results immediately after a/d conversion is started a/d conversion end a/d conversion end undefined value normal conversion result a/d conversion end adcr intad adcs a/d startup dummy reading of conversion result (10) reading a/d conversion result register (adcr) if the conversion result register (adcr) is read after stopping the a/d conversion operation, the conversion result may be undefined. therefore, be sure to read adcr before stopping operation of the a/d converter. (11) timing that makes the a/d conversion result undefined if the timing of the end of a/d conversion and the timing of the stop of operation of the a/c converter conflict, the a/d conversion value may be undefined. because of this, be sure to read the a/d conversion result while the a/d converter is in operation. furthermore, when reading an a/d conversion result after the a/d converter operation has stopped, be sure to have done so by the time the next conversion result is complete. the conversion result read timing is shown in figures 14-12 and 14-13 below. figure 14-12. conversion result read timing (when conversion result is undefined) a/d conversion end a/d conversion end adcr intad adcs normal conversion result read normal conversion result undefined value a/d operation stopped undefined value read 281 chapter 14 a/d converter user s manual u13570ej3v0ud figure 14-13. conversion result read timing (when conversion result is normal) (12) cautions on board design in order to avoid negative effects from digital circuit noise on the board, analog circuits must be placed as far away as possible from digital circuits. it is particularly important to prevent analog and digital signal lines from crossing or coming into close proximity, as a/d conversion characteristics are vulnerable to degradation from the induction of noise or other such factors. (13) av dd pin the av dd pin is the power supply pin of the analog circuit, and also supplies power to the ani0/p10 to ani7/ p17 input circuits. therefore, be sure to apply the same electric potential level as v dd as shown in figure 14-14, even in applications that can be switched to a backup power supply. figure 14-14. handling of av dd pin a/d conversion end adcr intad adcs a/d operation stopped normal conversion result read normal conversion result main power supply av ref0 v dd av dd av ss v ss backup capacitor (14) internal equivalence circuit and allowable signal source impedance of ani0 to ani7 in order to complete sampling within the sampling time and obtain a high enough a/d conversion accuracy, it is necessary to sufficiently reduce the impedance of the sensor and other signal sources. figure 14-15 shows the internal equivalence circuit of the ani0 to ani7 pins in the microcontroller. if the impedance of the signal source is high, it can be made to seem smaller by connecting a large capacitance to the ani0 to ani7 pins. a circuit example is shown in figure 14-16. in this case, because a low pass filter is configured in the circuit, impedance will no longer be able to follow analog signals with large differential coefficients. when converting high-speed analog signals or performing conversion in scan mode, be sure to insert a low- impedance buffer. 282 chapter 14 a/d converter user s manual u13570ej3v0ud figure 14-15. internal equivalence circuit of ani0 to ani7 pins remark n = 0 to 7 table 14-2. resistance and capacitance values for equivalent circuits (reference values) v dd0 r1 r2 c1 c2 c3 1.8 v 75 k ? 30 k ? 3 pf 4 pf 2 pf 2.7 v 12 k ? 8 k ? 3 pf 3 pf 2 pf 4.5 v 3 k ? 2.7 k ? 3 pf 1.4 pf 2 pf caution the resistance and capacitance values in table 14-2 cannot be guaranteed. figure 14-16. example of circuit when signal source impedance is high anin r1 r2 c1 c2 c3 remark n = 0 to 7 283 user s manual u13570ej3v0ud chapter 15 d/a converter 15.1 function the d/a converter converts the digital input into analog values and consists of two channels of voltage output d/ a converters with 8-bit resolution. the conversion method is a r-2r resistor ladder. set dace0 of d/a converter mode register 0 (dam0) and dace1 of d/a converter mode register 1 (dam1) to start the d/a conversion. the d/a converter has the following two modes. (1) normal mode after d/a conversion, the analog voltage is immediately output. (2) real-time output mode after d/a conversion, the analog voltage is output synchronized to the output trigger. since a sine wave is created when this mode is used, msk modems can be easily incorporated into cordless phones. caution if only one channel of the d/a converter is used when av ref1 < v dd , make either of the following setting at pins that are not used for analog output. set the port mode register (pm13 ) to 1 (input mode) and connect to v ss . set the port mode register (pm13 ) to 0 (output mode) and the output latch to 0, and output a low level. 15.2 configuration the d/a converter has the following hardware. table 15-1. d/a converter configuration item configuration registers d/a conversion setting register 0 (dacs0) d/a conversion setting register 1 (dacs1) control registers d/a converter mode register 0 (dam0) d/a converter mode register 1 (dam1) 284 chapter 15 d/a converter user s manual u13570ej3v0ud figure 15-1. d/a converter block diagram internal bus dacs1 write inttm2 dacs0 write inttm1 av ref1 av ss d/a conversion setting register 1 (dacs1) d/a conversion setting register 0 (dacs0) 2r 2r 2r 2r r r ano1/p131 ano0/p130 dace1 d/a converter mode register 0 (dam0) internal bus 2r 2r 2r 2r r r selector selector dam1 dace0 dam0 d/a converter mode register 1 (dam1) (1) d/a conversion setting registers 0, 1 (dacs0, dacs1) the dacs0 and dacs1 registers set the analog voltages that are output to the ano0 and ano1 pins, respectively. dacs0 and dacs1 are set by 8-bit memory manipulation instructions. reset input sets dacs0 and dacs1 to 00h. the analog voltages output by the ano0 and ano1 pins are determined by the following equation. anon output voltage = av ref1 dacsn 256 n = 0, 1 cautions 1. in the real-time output mode, when the data set in dacs0 and dacs1 are read before the output trigger is generated, the set data is not read and the previous data is read. 2. in the real-time output mode, set the data of dacs0 and dacs1 until the next output trigger is generated after the output trigger is generated. 285 chapter 15 d/a converter user s manual u13570ej3v0ud 15.3 control registers d/a converter mode registers 0, 1 (dam0, dam1) d/a converters are controlled by d/a converter mode registers 0, 1 (dam0, dam1). these registers enable or stop the operation of the d/a converters. dam0 and dam1 are set by a 1-bit and 8-bit memory manipulation instruction. reset input sets dam0 and dam1 to 00h. figure 15-2. d/a converter mode registers 0, 1 (dam0, dam1) formats address: 0ff86h, 0ff87h after reset: 00h r/w symbol 7654321<0> damn 000000 damn dacen damn d/a converter channel n operating mode 0 normal mode 1 real-time output mode dacen d/a converter channel n control 0 stop conversion 1 enable conversion cautions 1. when the d/a converters are used, set the shared port pins to the input mode and disconnect the pull-up resistors. 2. always set bits 2 to 7 to 0. 3. the output when the d/a converter operation has stopped enters high impedance state. 4. the output triggers in the real-time output mode are inttm1 in channel 0 and inttm2 in channel 1. remark n = 0, 1 286 chapter 15 d/a converter user s manual u13570ej3v0ud 15.4 operation <1> select the operating mode in channel 0 in dam0 of d/a converter mode register 0 (dam0) and the operating mode of the channel 1 in dam1 of d/a converter mode register 1 (dam1). <2> set the data that corresponds to the analog voltages that are output to pins ano0/p130 and ano1/p131 of d/a conversion setting registers 0 and 1 (dacs0, dacs1). <3> set dace0 of dam0 and dace1 of dam1 to start d/a conversion in channels 0 and 1. <4> after d/a conversion in the normal mode, the analog voltages at pins ano0/p130 and ano1/p131 are immediately output. in the real-time output mode, the analog voltage is output synchronized to the output trigger. <5> in the normal mode, the output analog voltages are maintained until new data are set in dacs0 and dacs1. in the real-time output mode, after new data are set in dacs0 and dacs1, they are held until the next output trigger is generated. caution set dace0 and dace1 after data are set in dacs0 and dacs1. 15.5 cautions (1) output impedances of the d/a converters since the output impedances of the d/a converters are high, the current cannot be taken from the anon pin (n = 0,1). if the input impedance of the load is low, insert a buffer amp between the load and the anon pin. in addition, use the shortest possible wire from the buffer amp or load (to increase the output impedance). if the wire is long, surround it with a ground pattern. 287 chapter 15 d/a converter user s manual u13570ej3v0ud figure 15-3. buffer amp insertion example (a) inverting amp (b) voltage follower (2) output voltages of the d/a converters since the output voltages of the d/a converters change in stages, use the signals output from the d/a converters after passing them through low-pass filters. (3) av ref1 pin when av ref1 < v dd and the d/a converter is used in only one channel, handle the pins that are not used for analog output in either of the following ways. set the port mode register (pm13 ) to 1 (input mode) and connect to v ss . set the port mode register (pm13 ) to 0 (output mode), set the output latch to 0, and output a low level. + c r 2 r 1 the input impedance of the buffer amp is r 1 . anon + r 1 c r anon the input impedance of the buffer amp is r 1 . if there is no r 1 and reset is low, the output is undefined. 288 user s manual u13570ej3v0ud chapter 16 serial interface overview the pd784218a subseries has a serial interface with three independent channels. therefore, communication outside and within the system can be simultaneous on the three channels. asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 channels see chapter 17 . clock-synchronized serial interface (csi) 1 channel 3-wire serial i/o mode (msb first) see chapter 18 . ? 2 c bus mode (multimaster compatible) (only in the pd784216ay, 784218ay subseries) see chapter 19 . 289 chapter 16 serial interface overview user s manual u13570ej3v0ud figure 16-1. serial interface example (a) uart + i 2 c (b) uart + 3-wire serial i/o note handshake lines pd784218ay (master) pd4711a rs-232c driver/receiver pd4711a (uart) (uart) ? ? ? ? ? ? port port rxd1 txd1 rxd2 txd2 sda0 scl0 (i 2 c) lcd pd78054y (slave) pd78062y (slave) v dd sda scl sda scl v dd rs-232c driver/receiver pd784218ay (master) pd4711a (uart) ? ? ? port rxd2 txd2 pd75108 (slave) si so sck port int [3-wire serial i/o] note so1 si1 sck1 intpm port rs-232c driver/receiver 290 user s manual u13570ej3v0ud chapter 17 asynchronous serial interface/3-wire serial i/o the pd784218a provides on-chip two serial interface channels for which the asynchronous serial interface (uart) mode and the 3-wire serial i/o (ioe) mode can be selected. these two serial interface channels have exactly the same functions. table 17-1. designation differences between uart1/ioe1 and uart2/ioe2 item uart1/ioe1 uart2/ioe2 pin name p22/asck1/sck1, p72/asck2/sck2, p20/r x d1/si1, p70/r x d2/si2, p21/t x d1/so2 p71/t x d2/so2 asynchronous serial interface mode register asim1 asim2 name of bits inside asynchronous serial interface mode register txe1, rxe1, ps11, txe2, rxe2, ps21, ps10, cl1, sl1, ps20, cl2, sl2, isrm1, irdam1 isrm2, irdam2 asynchronous serial interface status register asis1 asis2 name of bits inside asynchronous serial interface status register pe1, fe1, ove1 pe2, fe2, ove2 serial operation mode register csim1 csim2 name of bits inside serial operation mode register csie1, mode1, csie2, mode2, scl11, scl10 scl21, scl20 baud rate generator control register brgc1 brgc2 name of bits inside baud rate generator control register tps10 to tps12, tps20 to tps22, mdl10 to mdl13 mdl20 to mdl23 interrupt request name intsr1/intcsi1, intsr2/intcsi2, intser1, intst1 intser2, intst2 interrupt control register and name of bits used in this chapter sric1, seric1, stic1, sric2, seric2, stic2, srif1, serif1, stif1 srif2, serif2, stif2 291 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode the asynchronous serial interface mode and the 3-wire serial i/o mode cannot be used at the same time. both these modes can be switched by setting the asynchronous serial interface mode registers (asim1, asim2) and the serial operation mode registers (csim1, csim2), as shown in figure 17-1 below. figure 17-1. switching asynchronous serial interface mode and 3-wire serial i/o mode txe2 rxe2 ps21 ps20 cl2 0ff71h asim2 sl2 isrm2 irdam2 00h r/w txe1 txe2 0 0 0 1 1 rxe1 rxe2 0 0 1 0 1 operation stop mode 3-wire serial i/o mode txe1 <7> rxe1 <6> ps11 ps10 4 cl1 3210 0ff70h address asim1 sl1 isrm1 irdam1 5 00h after reset r/w r/w specification of operation in asynchronous serial interface mode (see figure 17-3 ). csie1 csie2 0 1 0 0 0 other than above csie20000 0ff92h csim2 mode2 scl21 scl20 00h r/w csie1 <7> 0 6 00 4 0 3210 0ff91h address csim1 mode1 scl11 scl10 5 00h after reset r/w r/w specification of operation in 3-wire serial i/o mode (see figure 17-13 ). asynchronous serial interface mode setting prohibited operation mode 292 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud table 17-2. serial interface operation mode settings (1) operation stopped mode asimn csimn pm20 p20 pm21 p21 pm22 p22 first shift p20/rxd1/si1 p21/txd1/so1 p22/asck1/sck1 txen rxen csien scln1 scln0 pm70 p70 pm71 p71 pm72 p72 bit clock p70/rxd2/si2 p71/txd2/so2 p72/asck2/sck2 pin function pin function pin function 000 note 1 note 1 note 1 note 1 note 1 note 1 p20 p21 p22 p70 p71 p72 other than above setting prohibited (2) asynchronous serial interface mode asimn csimn pm20 p20 pm21 p21 pm22 p22 first shift p20/rxd1/si1 p21/txd1/so1 p22/asck1/sck1 txen rxen csien scln1 scln0 pm70 p70 pm71 p71 pm72 p72 bit clock p70/rxd2/si2 p71/txd2/so2 p72/asck2/sck2 pin function pin function pin function 100 note 1 note 1 0 note 2 01 lsb external p20 txdn asckn input clock p70 (cmos output) note 1 note 1 internal p22 clock p72 01 1 note 1 note 1 1 external rxdn p21 asckn input clock p71 note 1 note 1 internal p22 clock p72 11 0 note 2 01 external txdn asckn input clock (cmos output) note 1 note 1 internal p22 clock p72 other than above setting prohibited (3) 3-wire serial i/o mode asimn csimn pm20 p20 pm21 p21 pm22 p22 first shift p20/rxd1/si1 p21/txd1/so1 p22/asck1/sck1 txen rxen csien scln1 scln0 pm70 p70 pm71 p71 pm72 p72 bit clock p70/rxd2/si2 p71/txd2/so2 p72/asck2/sck2 pin function pin function pin function 00100 1 note 3 note 3 001 msb external sin note 3 son sckn input clock (cmos output) note 4 note 4 00 internal sckn output clock other than above setting prohibited notes 1. these pins can be used for port functions. 2. refer to asynchronous serial interface mode (c) transmission. 3. when only transmission is used, these pins can be used as p20, p70 (cmos input/output). 4. refer to serial operation mode registers 1, 2 (csim1, csim2). remark : don t care n = 1, 2 293 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.2 asynchronous serial interface mode the asynchronous serial interface (uart: universal asynchronous receiver transmitter) offers the following three modes. (1) operation stop mode this mode is used when serial transfer is not performed to reduce the power consumption. (2) asynchronous serial interface (uart) mode this mode is used to send and receive 1-byte data that follows the start bit, and supports full-duplex transmission. a uart-dedicated baud rate generator is provided on-chip, enabling transmission at any baud rate within a broad range. the baud rate can also be defined by dividing the input clock to the asck pin. the midi specification baud rate (31.25 kbps) can be used by utilizing the uart-dedicated baud rate generator. (3) infrared data transfer mode 17.2.1 configuration the asynchronous serial interface has the following hardware configuration. figure 17-2 gives the block diagram of the asynchronous serial interface. table 17-3. asynchronous serial interface configuration item configuration registers transmit shift registers (txs1, txs2) receive shift registers (rx1, rx2) receive buffer registers (rxb1, rxb2) control registers asynchronous serial interface mode registers (asim1, asim2) asynchronous serial interface status registers (asis1, asis2) baud rate generator control registers (brgc1, brgc2) 294 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud figure 17-2. block diagram in asynchronous serial interface mode internal bus 8 8 8 receive buffer registers 1, 2 (rxb1, rxb2) transmit shift registers 1, 2 (txs1, txs2) receive control parity check transmit control parity addition rxd1, rxd2 txd1, txd2 asck1, asck2 baud rate generator intsr1, intsr2 intst1, intst2 selector 5-bit counter 2 transmission/reception clock generator f xx to f xx /2 5 to1 receive shift registers 1, 2 (rx1, rx2) 295 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (1) transmit shift registers (txs1, txs2) these registers are used to set transmit data. data written to txs1 and txs2 is sent as serial data. if a data length of 7 bits is specified, bits 0 to 6 of the data written to txs1 and txs2 are transferred as transmit data. transmission is started by writing data to txs1 and txs2. txs1 and txs2 can be written with an 8-bit memory manipulation instruction, but cannot be read. reset input sets txs1 and txs2 to ffh. caution do not write to txs1 and txs2 during transmission. txs1, txs2, and receive buffer registers (rxb1, rxb2) are allocated to the same address. therefore, attempting to read txs1 and txs2 will result in reading the values of rxb1 and rxb2. (2) receive shift registers (rx1, rx2) these registers are used to convert serial data input to the r x d1 and r x d2 pins to parallel data. receive data is transferred to the receive buffer register (rxb1, rsb2) one byte at a time as it is received. rx1 and rx2 cannot be directly manipulated by program. (3) receive buffer registers (rxb1, rxb2) these registers are used to hold receive data. each time one byte of data is received, new receive data is transferred from the receive shift registers (rx1, rx2). if a data length of 7 bits is specified, receive data is transferred to bits 0 to 6 of rxb1 and rxb2, and the msb of rxb1 and rxb2 always becomes 0. rxb1 and rxb2 can be read by an 8-bit memory manipulation instruction, but cannot be written. reset input sets rxb1 and rxb2 to ffh. caution rxb1, rxb2, and transmit shift registers (txs1, txs2) are allocated to the same address. therefore, attempting to write to rxb1 and rxb2 will result in writing the values to txs1 and txs2. (4) transmission control circuit this circuit controls transmit operations such as the addition of a start bit, parity bit, and stop bit(s) to data written to the transmit shift registers (txs1, txs2), according to the contents set to the asynchronous serial interface mode registers (asim1, asim2). (5) reception control circuit this circuit controls reception according to the contents set to the asynchronous serial interface mode registers (asim1, asim2). it also performs error check for parity errors, etc., during reception. if it detects an error, it sets a value corresponding to the nature of the error in the asynchronous serial interface status registers (asis1, asis2). 296 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.2.2 control registers the asynchronous serial interface controls the following six types of registers. asynchronous serial interface mode registers 1, 2 (asim1, asim2) asynchronous serial interface status registers 1, 2 (asis1, asis2) baud rate generator control registers 1, 2 (brgc1, brgc2) (1) asynchronous serial interface mode registers 1, 2 (asim1, asim2) asim1 and asim2 are 8-bit registers that control serial transfer using the asynchronous serial interface. asim1 and asim2 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim1 and asim2 to 00h. 297 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud figure 17-3. asynchronous serial interface mode registers 1, 2 (asim1, asim2) format address: 0ff70h, 0ff71h after reset: 00h r/w symbol <7> <6> 543210 asimn txen rxen psn1 psn0 cln sln isrmn irdamn txen rxen operation mode rxd1/p20, rxd2/p70 txd1/p21, txd2/p71 pin function pin function 0 0 operation stop port function port function 0 1 uart mode serial function port function (receive only) 1 0 uart mode port function serial function (transmit only) 1 1 uart mode serial function serial function (transmit/receive) psn1 psn0 parity bit specification 0 0 no parity 0 1 always add 0 parity during transmission do not perform parity check during reception (parity error not generated) 1 0 odd parity 1 1 even parity cln transmit data character length specification 0 7 bits 1 8 bits sln transmit data stop bit length specification 0 1 bit 1 2 bits isrmn receive completion interrupt control at error occurrence 0 generate receive completion interrupt when error occurs 1 do not generate receive completion interrupt when error occurs irdamn infrared data transfer mode operation specification note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. specification of the uart/infrared data transfer mode is controlled with txen and rxen. 2. when the infrared data transfer mode is used, be sure to set 0000 (set clock to f sck /16) to bits 3 to 0 (mldn3 to mldn0) of baud rate generator control register n (brgcn). caution before switching the operation mode, stop serial transmission or reception. remark n = 1, 2 298 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (2) asynchronous serial interface status registers 1, 2 (asis1, asis2) asis1 and asis2 are registers used display the type of error when a receive error occurs. asis1 and asis2 can be read with 1-bit and 8-bit memory manipulation instructions. reset input sets asis1 and asis2 to 00h. figure 17-4. asynchronous serial interface status registers 1, 2 (asis1, asis2) format address: 0ff72h, 0ff73h after reset: 00h r/w symbol 76543<2><1><0> asisn 00000penfen oven pen parity error flag 0 parity error not generated 1 parity error generated (when parity of transmit data does not match) fen framing error flag 0 framing error not generated 1 framing error generated note 1 (when stop bit(s) is not detected) oven overrun error flag 0 overrun error not generated 1 overrun error generated note 2 (when next receive operation is completed before data from receive buffer register is read) notes 1. even if the stop bit length has been set to 2 bits with bit 2 (sln) of asynchronous serial interface mode register n (asimn), stop bit detection during reception is only 1 bit. 2. be sure to read receive buffer register n (rxbn) when an overrun error occurs. an overrun error is generated each time data is received until rxbn is read. remark n = 1, 2 299 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (3) baud rate generator control registers 1, 2 (brgc1, brgc2) brgc1 and brgc2 are registers used to set the serial clock of the asynchronous serial interface. brgc1 and brgc2 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets brgc1 and brgc2 to 00h. 300 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud figure 17-5. baud rate generator control registers 1, 2 (brgc1, brgc2) format address: 0ff76h, 0ff77h after reset: 00h r/w symbol 76543210 brgcn 0 tpsn2 tpsn1 tpsn0 mdln3 mdln2 mdln1 mdln0 tpsn2 tpsn1 tpsn0 5-bit counter source clock selection m 0 0 0 external clock (asckn) 0 00 1f xx (12.5 mhz) 0 01 0f xx /2 (6.25 mhz) 1 01 1f xx /4 (3.13 mhz) 2 10 0f xx /8 (1.56 mhz) 3 10 1f xx /16 (781 khz) 4 11 0f xx /32 (391 khz) 5 1 1 1 to1 (tm1 output) 0 mdln3 mdln2 mdln1 mdln0 baud rate generator k input clock selection 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited cautions 1. if a write operation to brgcn is performed during communication, the baud rate generator output will become garbled and normal communication will not be achieved. therefore, do not perform write operations to brgcn during communication. 2. refer to the data sheet for details of the high-/low-level width of asckn when selecting the external clock (asckn) for the source clock of the 5-bit counter. remarks 1. n = 1, 2 2. data in parentheses is for when f xx = 12.5 mhz 3. f sck : source clock of 5-bit counter 4. m: value set in tpsn0 to tpsn2 (0 m 5) 5. k: value set in mdln0 to mdln3 (0 k 14) 301 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.3 operation the asynchronous serial interface has the following three types of operation modes. operation stop mode asynchronous serial interface (uart) mode infrared data transfer mode 17.3.1 operation stop mode serial transfer cannot be performed in the operation stop mode, resulting in reduced power consumption. moreover, in the operation stop mode, pins can be used as regular ports. (1) register setting setting of the operation stop mode is done with asynchronous serial interface mode registers 1 and 2 (asim1, asim2). asim1 and asim2 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim1 and asim2 to 00h. address: 0ff70h, 0ff71h after reset: 00h r/w symbol <7> <6> 543210 asimn txen rxen psn1 psn0 cln sln isrmn irdamn txen rxen operation mode rxd1/p20, rxd2/p70 txd1/p21, txd2/p71 pin function pin function 0 0 operation stop port function port function 0 1 uart mode serial function port function (receive only) 1 0 uart mode port function serial function (transmit only) 1 1 uart mode serial function serial function (transmit/receive) caution before switching the operation mode, stop serial transmission or reception. remark n = 1, 2 302 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.3.2 asynchronous serial interface (uart) mode this mode is used to transmit and receive the 1-byte data following the start bit. it supports full-duplex operation. a uart-dedicated baud rate generator is incorporated enabling communication using any baud rate within a large range. the midi standard s baud rate (31.25 kbps) can be used utilizing the uart-dedicated baud rate generator. (1) register setting the uart mode is set with asynchronous serial interface mode registers 1 and 2 (asim1, asim2), asynchronous serial interface status registers 1 and 2 (asis1, asis2), and baud rate generator control registers 1 and 2 (brgc1, brgc2). 303 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (a) asynchronous serial interface mode registers 1, 2 (asim1, asim2) asim1 and asim2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets asim1 and asim2 to 00h. address: 0ff70h, 0ff71h after reset: 00h r/w symbol <7> <6> 543210 asimn txen rxen psn1 psn0 cln sln isrmn irdamn txen rxen operation mode rxd1/p20, rxd2/p70 txd1/p21, txd2/p71 pin function pin function 0 0 operation stop port function port function 0 1 uart mode serial function port function (receive only) 1 0 uart mode port function serial function (transmit only) 1 1 uart mode serial function serial function (transmit/receive) psn1 psn0 parity bit specification 0 0 no parity 0 1 always add 0 parity during transmission do not perform parity check during reception (parity error not generated) 1 0 odd parity 1 1 even parity cln transmit data character length specification 0 7 bits 1 8 bits sln transmit data stop bit length specification 0 1 bit 1 2 bits isrmn receive completion interrupt control at error occurrence 0 generate receive completion interrupt when error occurs 1 do not generate receive completion interrupt when error occurs irdamn infrared data transfer mode operation specification note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. specification of the uart or infrared data transfer mode is controlled with txen and rxen. 2. when the infrared data transfer mode is used, be sure to set 0000 (set clock to f sck /16) to bits 3 to 0 (mldn3 to mldn0) of baud rate generator control register n (brgcn). caution before switching the operation mode, stop serial transmission or reception. remark n = 1, 2 304 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (b) asynchronous serial interface status registers 1, 2 (asis1, asis2) asis1 and asis2 can be read by a 1-bit or 8-bit memory manipulation instruction. reset input sets asis1 and asis2 to 00h. address: 0ff72h, 0ff73h after reset: 00h r symbol 76543<2><1><0> asisn 00000penfen oven pen parity error flag 0 parity error not generated 1 parity error generated (when parity of transmit data does not match) fen framing error flag 0 framing error not generated 1 framing error generated note 1 (when stop bit(s) is not detected) oven overrun error flag 0 overrun error not generated 1 overrun error generated note 2 (when next receive operation is completed before data from receive buffer register is read) notes 1. even if the stop bit length has been set to 2 bits with bit 2 (sln) of asynchronous serial interface mode register n (asimn), stop bit detection during reception is only 1 bit. 2. be sure to read receive buffer register n (rxbn) when an overrun error occurs. an overrun error is generated each time data is received until rxbn is read. remark n = 1, 2 305 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (c) baud rate generator control registers 1, 2 (brgc1, brgc2) brgc1 and brgc2 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets brgc1 and brgc2 to 00h. address: 0ff76h, 0ff77h after reset: 00h r/w symbol 76543210 brgcn 0 tpsn2 tpsn1 tpsn0 mdln3 mdln2 mdln1 mdln0 tpsn2 tpsn1 tpsn0 5-bit counter source clock selection m 0 0 0 external clock (asckn) 0 00 1f xx (12.5 mhz) 0 01 0f xx /2 (6.25 mhz) 1 01 1f xx /4 (3.13 mhz) 2 10 0f xx /8 (1.56 mhz) 3 10 1f xx /16 (781 khz) 4 11 0f xx /32 (391 khz) 5 1 1 1 to1 (tm1 output) 0 mdln3 mdln2 mdln1 mdln0 baud rate generator k input clock selection 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited 306 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud cautions 1. if a write operation to brgc1 and brgc2 is performed during communication, the baud rate generator output will become garbled and normal communication will not be achieved. therefore, do not perform write operations to brgc1 and brgc2 during communication. 2. refer to the data sheet for details of the high-/low-level width of asckn when selecting the external clock (asckn) for the source clock of the 5-bit counter. 3. set the 8-bit timer mode control register (tmc1) as follows when selecting to1 for the source clock of the 5-bit counter. tmc16 = 0, lvs1 = 0, lvr1 = 0, tmc11 = 1 moreover, set toe1 to 0 when to1 is not output externally and to 1 when to1 is output externally. remarks 1. n = 1, 2 2. figures in parentheses apply to operation at f xx = 12.5 mhz. 3. f sck : source clock of 5-bit counter 4. m: value set in tpsn0 to tpsn2 (0 m 5) 5. k: value set in mdln0 to mdln3 (0 k 14) the transmit/receive clock for the baud rate to be generated is the signal obtained by dividing the 5-bit counter source clock. generation of transmit/receive clock for baud rate the baud rate is obtained from the following equation. [baud rate] = [hz] t: 5-bit counter source clock when using a divided main system clock: main system clock (f xx ) when an external clock (asckn) is selected: output frequency of asckn when the timer 1 output (to1) is selected: output frequency of to1 m: value set in tpsn0 to tpsn2 (0 m 5) k: value set in mdln0 to mdln3 (0 k 14) baud rate capacity error range the baud rate capacity range depends on the number of bits per frame and the counter division ratio [1/(16 + k)]. table 17-4 shows the relation between the main system clock and the baud rate, figure 17-6 shows a baud rate capacity error example. t 2 m+1 (k + 16) 307 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud table 17-4. relationship between main system clock and baud rate baud rate f xx = 12.5 mhz f xx = 6.25 mhz f xx = 3.00 mhz (bps) brgc value error (%) brgc value error (%) brgc value error (%) 2,400 64h 2.34 4,800 64h 1.73 54h 2.34 9,600 64h 1.73 54h 1.73 44h 2.34 19,200 54h 1.73 44h 1.73 34h 2.34 31,250 49h 0.00 39h 0.00 28h 0 38,400 44h 1.73 34h 1.73 24h 2.34 76,800 34h 1.73 24h 1.73 14h 2.34 150k 24h 1.73 14h 1.73 300k 14h 1.73 remark when tm1 output is used, 150 to 38,400 bps is supported (during operation with f xx = 12.5 mhz) figure 17-6. baud rate capacity error considering sampling errors (when k = 0) remark t: 5-bit counter source clock period baud rate capacity error (k = 0) 100 = 4.8438 (%) 15.5 320 d0 32t 30.45t 64t 256t 288t ideal sampling point 304t 336t d7 p reference timing (clock period t) stop start 352t 320t d0 d7 p low-speed clock for which normal reception is enabled (clock period t ) stop start d0 15.5t d7 p high-speed clock for which normal reception is enabled (clock period t ) stop start 60.9t 33.55t 67.1t 301.95t 335.5t 304.5t 15.5t sampling error 0.5t 308 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (2) communication operation (a) data format the transmission/reception data format consists of a start bit, character bits, parity bit, and stop bit(s) forming character frames, as shown in figure 17-7. specification of the character bit length inside data frames, selection of the parity, and selection of the stop bit length, are performed with asynchronous serial interface mode register n (asimn). figure 17-7. asynchronous serial interface transmit/receive data format start bit ......................... 1 bit character bits .............. 7 bits/8 bits parity bit ....................... even parity/odd parity/0 parity/no parity stop bit(s) .................... 1 bit/2 bits if 7 bits has been selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid. in the case of transmission, the highest bit (bit 7) is ignored. in the case of reception, the highest bit (bit 7) always becomes 0 . the setting of the serial transfer rate is performed with asynchronous serial interface mode register n (asimn) and baud rate generator control register n (brgcn). if a serial data reception error occurs, it is possible to determine the contents of the reception error by reading the status of asynchronous serial interface status register n (asisn). remark n = 1, 2 d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit(s) start bit 1-data frame character bit 309 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (b) parity types and operations parity bits serve to detect bit errors in transmit data. normally, the parity bit used on the transmit side and the receive side are of the same type. in the case of even parity and odd parity, it is possible to detect 1 bit (odd number) errors. in the case of 0 parity and no parity, errors cannot be detected. (i) even parity during transmission makes the number of 1 s in transmit data that includes the parity bit even. the value of the parity bit changes as follows. if the number of 1 bits in transmit data is odd: 1 if the number of 1 bits in transmit data is even: 0 during reception the number of 1 bits in receive data that includes the parity bit is counted, and if it is odd, a parity error occurs. (ii) odd parity during transmission odd parity is the reverse of even parity. it makes the number of 1 s in transmit data that includes the parity bit odd. the value of the parity bit changes as follows. if the number of 1 bits in transmit data is odd: 0 if the number of 1 bits in transmit data is even: 1 during reception the number of 1 bits in receive data that includes the parity bit is counted, and if it is even, a parity error occurs. (iii) 0 parity during transmission, makes the parity bit 0 , regardless of the transmit data. parity bit check is not performed during reception. therefore, no parity error occurs, regardless of whether the parity bit value is 0 or 1 . (iv) no parity no parity is appended to transmit data. receive data is received assuming that it has no parity bit. no parity error can occur because there is no parity bit. 310 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (c) transmission transmission is begun by writing transmit data to transmit shift register n (txsn). the start bit, parity bit, and stop bit(s) are automatically added. the contents of transmit shift register n (txsn) are shifted out upon transmission start, and when transmit shift register n (txsn) becomes empty, a transmit completion interrupt (intstn) is generated. caution in the case of uart transmission, follow the procedure below when performing transmission for the first time. <1> set the port to the input mode (pm21 = 1 or pm71 = 1), and write 0 to the port latch. <2> set bit 7 (txen) of asynchronous serial interface mode register n (asimn) to 1 to enable uart transmission (output a high level from the txdn pin). <3> set the port to the output mode (pm21 = 0 or pm71 = 0). <4> write transmit data to txsn, and start transmission. if the port is set to the output mode first, 0 will be output from the pins, which may cause malfunction. remark n = 1, 2 figure 17-8. asynchronous serial interface transmit completion interrupt timing (a) stop bit length: 1 (b) stop bit length: 2 caution do not write to asynchronous serial interface mode register n (asimn) during transmission. if you write to the asimn register during transmission, further transmission operations may become impossible (in this case, input reset to return to normal). whether transmission is in progress or not can be judged by software, using the transmit completion interrupt (intstn) or the interrupt request flag (stifn) set by intstn. remark n = 1, 2 d1 d2 d6 d7 parity d0 txdn (output) intstn stop start d1 d2 d6 d7 parity d0 txdn (output) intstn stop start 311 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (d) reception when the rxen bit of asynchronous serial interface mode register n (asimn) is set to 1, reception is enabled and sampling of the rxdn pin input is performed. sampling of the rxdn pin input is performed by the serial clock set in baud rate generator control register n (brgcn). when the rxdn pin input becomes low level, the 5-bit counter of the baud rate generator starts counting, and outputs the data sampling start timing signal when half the time of the set baud rate has elapsed. if the result of re-sampling the rxdn pin input with this start timing signal is low level, the rxdn pin input is perceived as the start bit, the 5-bit counter is initialized and begins counting, and data sampling is performed. when, following the start bit, character data, the parity bit, and one stop bit are detected, reception of one frame of data is completed. when reception of one frame of data is completed, the receive data in the shift register is transferred to receive buffer register n (rxbn), and a receive completion interrupt (intsrn) is generated. moreover, even if an error occurs, the receive data for which the error occurred is transferred to rxbn. if an error occurs, when bit 1 (isrmn) of asimn is cleared (0), intsrn is generated (refer to figure 17-10 ). when bit isrmn is set (1), intsrn is not generated. when bit rxen is reset to 0 during a receive operation, the receive operation is immediately stopped. at this time, the contents of rxbn and asisn remain unchanged, and intsrn and intsern are not generated. remark n = 1, 2 figure 17-9. asynchronous serial interface receive completion interrupt timing caution even when a receive error occurs, be sure to read the receive buffer register (rxbn). if rxbn is not read, an overrun error will occur during reception of the next data, and the reception error status will continue indefinitely. remark n = 1, 2 d1 d2 d6 d7 parity d0 rxdn (input) intsrn stop start 312 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (e) receive error errors that occur during reception are of three types: parity errors, framing errors, and overrun errors. as the data reception result error flag is set inside asynchronous serial interface status register n (asisn), the receive error interrupt (intsern) is generated. a receive error interruption is generated before a receive end interrupt (intsrn). receive error causes are shown in table 17-5. what type of error has occurred during reception can be detected by reading the contents of asynchronous serial interface status register n (asisn) during processing of the receive error interrupt (refer to table 17- 5 and figure 17-10 ). the contents of asisn are reset to 0 either when receive buffer register n (rxbn) is read or when the next data is received (if the next data has an error, this error flag is set). remark n = 1, 2 table 17-5. receive error causes receive error cause asisn parity error parity specified for transmission and parity of receive data don t match 04h framing error stop bit was not detected 02h overrun error next data reception was completed before data was read from the receive buffer register 01h figure 17-10. receive error timing note if a receive error occurs, when bit isrmn is set (1), intsrn is not generated. cautions 1. the contents of the asisn register are reset to 0 either when receive buffer register n (rxbn) is read or when the next data is received. to find out the contents of the error, be sure to read asisn before reading rxbn. 2. be sure to read receive buffer register n (rxbn) even when a receive error occurs. if rxbn is not read, an overrun error will occur at reception of the next data, and the receive error status will continue indefinitely. remark n = 1, 2 d1 d2 d6 d7 parity d0 rxdn (input) intsrn note stop start intsern (framing/overrrun errors occur) intsern (when parity errors occur) 313 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.3.3 infrared data transfer mode infrared data transfer mode enables pulse output and pulse reception in the following data format. however this mode does not conform to the irda specifications. (1) data format a comparison of the data format in the uart mode and the data format in the infrared data transfer mode is shown in figure 17-11. ir frames correspond to the bit strings of uart frames made up of a start bit, eight data bits, and a stop bit. the length of the electrical pulse transmitted/received with these ir frames is 3/16 of a 1-bit period. a pulse of 3/16 of a 1-bit period rises from the center of the bit period (see figure below). figure 17-11. comparison of infrared data transfer mode and uart mode data formats bit time pulse width = 3/16 bit time 0 start bit 1 stop bit 1 d0 0 d1 1 d2 0 d3 0 d4 0 d7 1 d5 1 d6 uart frame data bits start bit stop bit 10100 0 11 ir frame data bits bit time pulse width = 3/16 bit time 0 1 314 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (2) bit rate and pulse width the bit rates, bit rate capacity errors, and pulse widths are shown in table 17-6. per specifications, the minimum pulse width can be either 3/16 of the bit period or the minimum pulse width of a 115.2 kbps signal (1.63 s to 22 s capacity error), and thus is the same regardless of the bit rate. the maximum pulse width is obtained by adding the greater of 2.5 % of the bit period or 1.08 s to 3/16 of the bit time. table 17-6. bit rate and pulse width values bit rate bit rate capacity error minimum pulse width pulse width 3/16 rating pulse width maximum value (kbits/s) (% of bit rate) ( s) note 1 ( s) ( s) 2.4 note 2 +/- 0.87 1.41 78.13 88.55 9.6 note 2 +/- 0.87 1.41 19.53 22.13 19.2 note 2 +/- 0.87 1.41 9.77 11.07 38.4 note 2 +/- 0.87 1.41 4.88 5.96 57.6 +/- 0.87 1.41 3.26 4.34 115.2 +/- 0.87 1.41 1.63 2.71 notes 1. the minimum value of the pulse width that can be received can be calculated as follows: [minimum value of receivable pulse width] = 2. the minimum pulse width of 1.41 s cannot be detected unless the bit rate is 44.4 kbps or more. an example of how to calculate the maximum pulse width when the bit rate is 2.4 kbps is shown below. 78.13 + (78.13 0.025) = 88.55 [ s] 16 3 1 16 [bit rate] 315 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (3) i/o data and internal signals transmission timing reception timing reception of half data of set baud rate is delayed. uart output data start bit stop bit uart (inverted data) infrared data transfer enable signal t x d1, t x d2 pins output signal uart transfer data start bit stop bit edge detection sampling clock reception rate conversion data sampling timing r x d1, r x d2 input 316 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.3.4 standby mode operation (1) halt mode operation serial transfer operation is normally performed. (2) stop mode or idle mode operation (a) when internal clock is selected as serial clock asynchronous serial interface mode register n (asimn), transmit shift register n (txsn), receive shift register n (rxn), and receive buffer register n (rxbn) stop operation holding the value immediately before the clock stops. if the clock stops (stop mode) during transmission, the txdn pin output data immediately before the clock stopped is held. if the clock stops during reception, receive data up to immediately before the clock stopped is stored, and subsequent operation is stopped. when the clock is restarted, reception is resumed. remark n = 1, 2 (b) when external clock is selected as serial clock serial transfer operation is performed normally. however, interrupt requests are pended without being acknowledged. interrupt requests are acknowledged after the stop mode or idle mode has been released through nmi input, intp0 to intp6 input, watch timer interrupt or key return interrupt (p80 to p87). 317 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.4 3-wire serial i/o mode this mode is used to perform 8-bit data transfer with the serial clock (sck1, sck2), serial output (so1, so2), and serial input (si1, si2) lines. the 3-wire serial i/o mode supports simultaneous transmit/receive operation, thereby reducing the data transfer processing time. the start bit of 8-bit data for serial transfer is fixed as the msb. the 3-wire serial i/o mode is effective when connecting a peripheral i/o with an on-chip clocked serial interface, a display controller, etc. 17.4.1 configuration the 3-wire serial i/o mode has the following hardware configuration. figure 17-12 shows the block diagram for the 3-wire serial i/o mode. table 17-7. 3-wire serial i/o configuration item configuration register serial i/o shift registers 1, 2 (sio1, sio2) control register serial operation mode registers 1, 2 (csim1, csim2) 318 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud figure 17-12. block diagram in 3-wire serial i/o mode serial i/o shift registers 1, 2 (sio1, sio2) these are 8-bit registers that perform parallel-serial conversion, and serial transmission/reception (shift operation) in synchronization with the serial clock. sion is set with an 8-bit memory manipulation instruction. when bit 7 (csien) of the serial operation mode register (csimn) is 1, serial operation can be started by writing/ reading data to/from sion. during transmission, data written to sion is output to the serial output pin (son). during reception, data is read into sion from the serial input pin (sin). reset input sets sio1 and sio2 to 00h. caution during transfer operation, do not perform access to sion other than access acting as a transfer start trigger (read and write are prohibited when moden = 0 and moden = 1, respectively). remark n = 1, 2 internal bus 8 interrupt generator selector serial clock counter serial clock controller serial i/o shift registers 1, 2 (sio1, sio2) si1, si2 so1, so2 sck1, sck2 intcsi1, intcsi2 to2 f xx /8 f xx /16 319 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.4.2 control registers serial operation mode registers 1, 2 (csim1, csim2) csim1 and csim2 are used to set the serial clock, operation mode, and operation enable/disable during the 3-wire serial i/o mode. csim1 and csim2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 and csim2 to 00h. figure 17-13. serial operation mode registers 1, 2 (csim1, csim2) format address: 0ff91h, 0ff92h after reset: 00h r/w symbol <7> 6543210 csimn csien 0000 moden scln1 scln0 csien sion operation enable/disable setting shift register operation serial counter port 0 operation disable clear port function note 1 operation enable counter operation serial function + port enable function moden transfer operation mode flag operation mode transfer start trigger son output 0 transmit or transmit/receive mode sion write normal output 1 receive-only mode sion read fix to low level scln1 scln0 clock selection 0 0 external clock to sckn 0 1 8-bit timer/counter 2 (tm2) output 10f xx /8 (1.56 mhz) 11f xx /16 (781 khz) notes 1. when csien = 0 (sion operation stop status), pins connected to sin, son, and sckn can be used as ports. 2. set the external clock and to2 to f xx /8 or below when selecting the external clock (sckn) and tm2 output (to2) for the clock. remarks 1. n = 1, 2 2. figures in parentheses apply to operation with f xx = 12.5 mhz. 320 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud 17.4.3 operation the following two types of 3-wire serial i/o operation mode are available. operation stop mode 3-wire serial i/o mode (1) operation stop mode serial transfer is not possible in the operation stop mode, which reduces power consumption. moreover, in operation stop mode, pins can normally be used a i/o ports. (a) register setting the operation stop mode is set by serial operation registers 1 and 2 (csim1, csim2). csim1 and csim2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 and csim2 to 00h. figure 17-14. serial operation mode registers 1, 2 (csim1, csim2) format address: 0ff91h, 0ff92h after reset: 00h r/w symbol <7> 6543210 csimn csien 0000 moden scln1 scln0 csien sion operation enable/disable setting shift register operation serial counter port 0 operation disable clear port function note 1 operation enable counter operation serial function + port enable function note when csien = 0 (sion operation stop status), pins connected to sin, son, and sckn can be used as ports. remark n = 1, 2 321 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (2) 3-wire serial i/o mode the 3-wire serial i/o mode is effective when connecting a peripheral i/o with an on-chip clocked serial interface, a display controller, etc. this mode is used to perform communication with the serial clock (sck1, sck2), serial output (so1, so2), and serial input (si1, si2) lines. (a) register setting the 3-wire serial i/o mode is set by serial operation mode registers 1 and 2 (csim1, csim2). csim1 and csim2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 and csim2 to 00h. figure 17-15. serial operation mode registers 1, 2 (csim1, csim2) format address: 0ff91h, 0ff92h after reset: 00h r/w symbol <7> 6543210 csimn csien 0000 moden scln1 scln0 csien sion operation enable/disable setting shift register operation serial counter port 0 operation disable clear port function note 1 operation enable counter operation serial function + port enable function moden transfer operation mode flag operation mode transfer start trigger son output 0 transmit or transmit/receive mode sion write normal output 1 receive-only mode sion read fix to low level scln1 scln0 clock selection 0 0 external clock to sckn 0 1 8-bit timer/counter 2 (tm2) output 10f xx /8 (1.56 mhz) 11f xx /16 (781 khz) notes 1. when csien = 0 (sion operation stop status), pins connected to sin, son, and sckn can be used as ports. 2. set the external clock and to2 to f xx /8 or below when selecting the external clock (sckn) and tm2 output (to2) for the clock. remarks 1. n = 1, 2 2. figures in parentheses apply to operation with f xx = 12.5 mhz. 322 chapter 17 asynchronous serial interface/3-wire serial i/o user s manual u13570ej3v0ud (b) communication operation the 3-wire serial i/o mode performs data transmission/reception in 8-bit units. data is transmitted and received one bit at a time in synchronization with the serial clock. the shift operation of serial i/o shift register n (sion) is performed in synchronization with the falling edge of the serial clock (sckn). transmit data is held in the son latch, and is output from the son pin. receive data input to the sin pin is latched to sion at the rising edge of the sckn signal. sion operation is automatically stopped when 8-bit transfer ends, and an interrupt request flag (srifn) is set. remark n = 1, 2 figure 17-16. 3-wire serial i/o mode timing sin sckn 12345678 di7 di6 di5 di4 di3 di2 di1 di0 son do7 do6 do5 do4 do3 do2 do1 do0 srifn transfer start in synchronization with falling edge of sckn transfer completion remark n = 1, 2 (c) transfer start serial transfer starts by setting (or reading) transfer data to serial i/o shift register n (sion) when the following two conditions are satisfied. sion operation control bit (csien) = 1 following 8-bit serial transfer, the internal serial clock is stopped, or sckn is high level transmit or transmit/receive mode when csien = 1 and moden = 0, transfer is started with sion write receive-only mode when csien = 1 and moden = 1, transfer is started with sion read remark n = 1, 2 caution after data is written to sion, transfer will not start even if csien is set to ?? serial transfer automatically stops at the end of 8-bit transfer, and the interrupt request flag (srifn) is set. 323 user s manual u13570ej3v0ud chapter 18 3-wire serial i/o mode 18.1 function this mode transfers 8-bit data by using the three lines of the serial clock (sck0), the serial output (so0), and the serial input (si0). since the 3-wire serial i/o mode can perform simultaneous transmission and reception, the data transfer processing time becomes shorter. the starting bit of the 8-bit data to be serially transferred is fixed at the msb. the 3-wire serial i/o mode is valid when the peripheral i/o or display controller equipped with a clocked serial interface is connected. 18.2 configuration the 3-wire serial i/o mode consists of the following hardware. figure 18-1 is a block diagram of the clocked serial interface (csi) in the 3-wire serial i/o mode. table 18-1. 3-wire serial i/o configuration item configuration register serial i/o shift register 0 (sio0) control register serial operating mode register 0 (csim0) 324 chapter 18 3-wire serial i/o mode user s manual u13570ej3v0ud figure 18-1. block diagram of clocked serial interface (in 3-wire serial i/o mode) internal bus interrupt generator serial clock counter serial clock control circuit serial i/o shift register 0 (sio0) si0 so0 sck0 intcsi0 8 selector to2 f xx /8 f xx /16 serial i/o shift register 0 (sio0) this 8-bit shift register performs parallel to serial conversion and serially communication (shift operation) synchronized to the serial clock. sio0 is set by an 8-bit memory manipulation instruction. when bit 7 (csie0) in serial operation mode register 0 (csim0) is 1, serial operation starts by writing data to or reading it from sio0. when transmitting, the data written to sio0 is output to the serial output (so0). when receiving, data is read from the serial input (si0) to sio0. reset input sets sio0 to 00h. caution do not access sio0 during a transfer except for an access that becomes a transfer start trigger. (when mode0 = 0, reading is disabled; and when mode0 = 1, writing is disabled.) 325 chapter 18 3-wire serial i/o mode user s manual u13570ej3v0ud 18.3 control registers serial operation mode register 0 (csim0) the csim0 register sets the serial clock and operating mode to the 3-wire serial i/o mode, and enables or stops operation. csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. figure 18-2. serial operation mode register 0 (csim0) format address: 0ff90h after reset: 00h r/w symbol <7> 6543210 csim0 csie0 0000 mode0 scl01 scl00 csie0 sio0 operation enable/disable setting shift register operation serial counter port 0 disable operation clear port function note 1 enable operation enable count operation serial function + port function mode0 transfer operation mode flag operation mode transfer start trigger so0 output 0 transmit or transmit/receive sio0 write normal output mode 1 receive-only mode sio0 read fixed low scl01 scl00 clock selection 0 0 external clock to sck0 0 1 8-bit timer/counter 2 (tm2) output 10f xx /8 (1.56 mhz) 11f xx /16 (781 khz) note if csie0 = 0 (sio0 operation stopped state), the pins connected to si0, so0 and sck0 can function as ports. cautions 1. set 8-bit timer mode control register 2 (tmc2) as follows when selecting 8-bit timer counter 2 (tm2) output as the clock. tmc26 = 0, tmc24 = 0, lvs2 = 0, lvr2 = 0, tmc21 = 1 moreover, set toe2 to 0 when to2 is not output externally and to 1 when to2 is output externally. 2. set the external clock and to2 to f xx /8 or below when selecting the external clock (sckn) and tm2 output (to2) for the clock. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 326 chapter 18 3-wire serial i/o mode user s manual u13570ej3v0ud table 18-2. serial interface operation mode settings (1) operation stopped mode csim0 pm25 p25 pm26 p26 pm27 p27 first shift p25/si0/sda0 p26/so0 p27/sck0/scl0 csie0 scl01 scl00 bit clock pin function pin function pin function 0 note 1 note 1 note 1 note 1 note 1 note 1 p25 p26 p27 other than above setting prohibited (2) 3-wire serial i/o mode csim0 pm25 p25 pm26 p26 pm27 p27 first shift p25/si0/sda0 p26/so0 p27/sck0/scl0 csie0 scl01 scl00 bit clock pin function pin function pin function 100 1 note 2 note 2 00 1 msb external sio note 2 so0 sck0 input clock (cmos output) note 3 note 3 00 internal sck0 output clock other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p25 (cmos input/output). 3. refer to serial operation mode register 0 (csim0). remark : don t care 327 chapter 18 3-wire serial i/o mode user s manual u13570ej3v0ud 18.4 operation 3-wire serial i/o has the following two operating modes. operation stop mode 3-wire serial i/o mode (1) operation stop mode since serial transfers are not performed in the operation stop mode, power consumption can be decreased. in the operation stop mode, the pin can be used as an ordinary i/o port. (a) register settings the operation stop mode is set in serial operation mode register 0 (csim0). csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. figure 18-3. serial operation mode register 0 (csim0) format address: 0ff90h after reset: 00h r/w symbol <7> 6543210 csim0 csie0 0000 mode0 scl01 scl00 csie0 sio0 operating enable/disable setting shift register operation serial counter port 0 disable operation clear port function note 1 enable operation enable count operation serial function + port function note if csie0 = 0 (sio0 operation stopped state), the pins connected to si0, so0, and sck0 can function as ports. 328 chapter 18 3-wire serial i/o mode user s manual u13570ej3v0ud (2) 3-wire serial i/o mode the 3-wire serial i/o mode is valid when connected to peripheral i/o or a display controller equipped with the clocked serial interface. communication is over three lines, the serial clock (sck0), serial output (so0), and serial input (si0). (a) register setting the 3-wire serial i/o mode is set in serial operation mode register 0 (csim0). csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. figure 18-4. serial operation mode register 0 (csim0) format address: 0ff90h after reset: 00h r/w symbol <7> 6543210 csim0 csie0 0000 mode0 scl01 scl00 csie0 sio0 operation enable/disable setting shift register operation serial counter port 0 disable operation clear port function note 1 enable operation enable count operation serial function + port function mode0 transfer operation mode flag operation mode transfer start trigger so0 output 0 transmit or transmit/receive sio0 write normal output mode 1 receive-only mode sio0 read low level fixed scl01 scl00 clock selection 0 0 external clock to sck0 0 1 8-bit timer/counter 2 (tm2) output 10f xx /8 (1.56 mhz) 11f xx /16 (781 khz) note if csie0 = 0 (sio0 operation stopped state), the pins connected to si0, so0, and sck0 can function as ports. cautions 1. set 8-bit timer mode control register 2 (tmc2) as follows when selecting 8-bit timer counter 2 (tm2) output as the clock. tmc26 = 0, tmc24 = 0, lvs2 = 0, lvr2 = 0, tmc21 = 1 moreover, set toe2 to 0 when to2 is not output externally and to 1 when to2 is output externally. 2. set the external clock and to2 to f xx /8 or below when selecting the external clock (sckn) and tm2 output (to2) for the clock. remark figures in parentheses apply to operation with f xx = 12.5 mhz. 329 chapter 18 3-wire serial i/o mode user s manual u13570ej3v0ud (b) communication the 3-wire serial i/o mode transmits and receives in 8-bit units. data is transmitted and received with each bit synchronized to the serial clock. the shifting of serial i/o shift register 0 (sio0) is synchronized to the falling edge of the serial clock (sck0). the transmitted data are held in the latch and output from the so0 pin. at the rising edge of sck0, the received data that was input at the si0 pin is latched to sio0. the end of the 8-bit transfer automatically stops sio0 operation and sets the interrupt request flag (csiif0). figure 18-5. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end transfer start transfer synchronized to the falling edge of sck0 sck0 si0 so0 csiif0 (c) start transfer if the following two conditions are satisfied, the serial transfer starts when the transfer data is set in serial i/o shift register 0 (sio0). control bit (csie0) = 1 during sio0 operation after an 8-bit serial transfer, the internal serial clock enters the stopped state or sck0 is high. transmit or transmit/receive mode when csie0 = 1 and mode0 = 0, the transfer starts with an sio0 write. receive-only mode when csie0 = 1 and mode0 = 1, the transfer starts with an sio0 read. caution even if csie0 is set to 1 after the data is written to sio0, transfer does not start. serial transfer is automatically stopped by the end of the 8-bit transfer, and the interrupt request flag (csiif0) is set. 330 user s manual u13570ej3v0ud chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) 19.1 overview of function ? 2 c (inter ic) bus mode (multimaster compatible) this interface communicates with devices that conform to the i 2 c bus format. eight bit data transfers with multiple devices are performed by the two lines of the serial clock (scl0) and the serial data bus (sda0). in the i 2 c bus mode, the master can output the start condition, data, and stop condition on the serial data bus to the slaves. the slaves automatically detect the received data by hardware. the i 2 c bus control portion of the application program can be simplified by using this function. since scl0 and sda0 become open-drain outputs in the i 2 c bus mode, pull-up resistors are required on the serial clock line and serial data bus line. cautions 1. if the power to the pd784218ay is disconnected while pd784218ay functions are not used, the problem is i 2 c communication will no longer be possible. even when not used, do not disconnect the power to the pd784218ay. 2. if the i 2 c bus mode is used, set the scl0/p27 and sda0/p25 pins to n-channel open-drains by setting the port function control register (pf2). 331 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-1. serial bus configuration example in i 2 c bus mode master cpu 1 slave cpu 1 sda0 scl0 serial data bus serial clock slave cpu 2 address 1 address 2 slave ic address 3 slave ic address n +v dd sda0 scl0 sda0 scl0 sda0 scl0 sda0 scl0 +v dd master cpu 2 slave cpu 3 19.2 configuration the clocked serial interface in the i 2 c bus mode consists of the following hardware. figure 19-2 is a block diagram of clocked serial interface (csi) in the i 2 c bus mode. table 19-1. i 2 c bus mode configuration item configuration registers serial shift register (iic0) slave address register (sva0) control registers i 2 c bus control register (iicc0) i 2 c bus status register (iics0) prescaler mode register for serial clock (sprm0) 332 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-2. block diagram of clocked serial interface (i 2 c bus mode) internal bus slave address register (sva0) noise eliminator sda0 match signal serial shift register (iic0) start condition detector stop condition detector interrupt request signal generator serial clock counter serial clock controller serial clock wait controller prescaler mode register for serial clock (sprm0) noise eliminator scl0 n-ch open- drain output internal bus f xx cl1 cl0 wake-up controller acknowledge detector acknowledge detector data hold time correction circuit cl1, cl0 dq so latch set prescaler clear iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 intiic0 i 2 c bus status register (iics0) i 2 c bus control register (iicc0) tm2 output cld dad smc dfc 333 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (1) serial shift register (iic0) the iic0 register converts 8-bit serial data into 8-bit parallel data and 8-bit parallel data into 8-bit serial data. iic0 is used in both transmission and reception. the actual transmission and reception are controlled by writing and reading iic0. iic0 is set by an 8-bit memory manipulation instruction. reset input sets iic0 to 00h. (2) slave address register (sva0) when used as a slave, this register sets a slave address. sva0 is set by an 8-bit memory manipulation instruction. reset input sets sva0 to 00h. (3) so latch the so latch holds the output level of the sda0 pin. (4) wake-up controller this circuit generates an interrupt request when the address set in the slave address register (sva0) and the reception address matched, or when an extended code was received. (5) clock selector this selects the sampling clock that is used. (6) serial clock counter the serial clock that is output or input during transmission or reception is counted to check 8-bit data communication. (7) interrupt request signal generator this circuit controls the generation of the interrupt request signal (intiic0). the i 2 c interrupt request is generated by the following two triggers. eighth or ninth clock of the serial clock (set by the wtim0 bit note ) interrupt request generated by detecting the stop condition (set by the spie0 bit note ) note wtim0 bit: bit 3 in the i 2 c bus control register (iicc0) spie0 bit: bit 4 in the i 2 c bus control register (iicc0) 334 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (8) serial clock controller in the master mode, the clock output to pin scl0 is generated by the sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) acknowledge output circuit, stop condition detector, start condition detector, acknowledge detector these circuits output and detect the control signals. (11) data hold time correction circuit this circuit generates the hold time of the data to the falling edge of the serial clock. 19.3 control registers the i 2 c bus mode is controlled by the following three registers. i 2 c bus control register (iicc0) i 2 c bus status register (iics0) prescaler mode register for serial clock (sprm0) the following registers are also used. serial shift register (iic0) slave address register (sva0) (1) i 2 c bus control register (iicc0) the iicc0 register enables and disables the i 2 c bus mode, sets the wait timing, and sets other i 2 c bus mode operations. iicc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets iicc0 to 00h. 335 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-3. i 2 c bus control register (iicc0) format (1/4) address: 0ffb0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enabled 0 disables operation. preset the i 2 c bus status register (iics0). stops internal operation. scl0 and sda0 lines output low level. 1 enables operation. clear condition (iice0 = 0) set condition (iice0 = 1) cleared by an instruction set by an instruction when reset is input lrel0 release communication 0 normal operation 1 releases microcontroller from the current communication and sets it in the wait state. automatically clears after execution. the extended code that is unrelated to the base is used during reception. the scl0 and sda0 lines are put in the high impedance state. the following flags are cleared. std0 ackd0 trc0 coi0 exc0 msts0 stt0 spt0 until the following communication participation conditions are satisfied, the wait state that was released from communication is entered. start as the master after detecting the stop condition. address match or extended code reception after the start condition clear condition (lrel0 = 0) note set condition (lrel0 = 1) automatically cleared after execution. set by an instruction when reset is input wrel0 wait release 0 the wait is not released. 1 the wait is released. after the wait is released, it is automatically cleared. clear condition (wrel0 = 0) note set condition (wrel0 = 1) automatically cleared after execution. set by an instruction when reset is input spie0 enable/disable generation of interrupt requests by stop condition detection 0 disable 1 enable clear condition (spie0 = 0) note set condition (spie0 = 1) cleared by an instruction set by an instruction when reset is input note iice0 = 0 makes this flag signal invalid. 336 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-3. i 2 c bus control register (iicc0) format (2/4) wtim0 control of wait and interrupt request generation 0 interrupt request generated at the falling edge of the eighth clock for the master: after the eighth clock is output, wait with the clock output low. for the slave: after the eighth clock is input, the master waits with the clock low. 1 interrupt request generated at the falling edge of the ninth clock for the master: after the ninth clock is output, wait with the clock output low. for the slave: after the ninth clock is input, the master waits with the clock low. this bit setting becomes invalid during an address transfer, and becomes valid after the transfer ends. in the master, a wait is inserted at the falling edge of the ninth clock in an address transfer. the slave that received the base address inserts a wait at the falling edge of the ninth clock after the acknowledge is generated. the slave that received the extended code inserts the waits at the falling edge of the eighth clock. clear condition (wtim0 = 0) note set condition (wtim0 = 1) cleared by an instruction set by an instruction when reset is input acke0 acknowledge control 0 acknowledge is disabled. 1 acknowledge is enabled. the sda0 line during the ninth clock period goes low. however, the control is invalid during an address transfer. when exc0 = 1, the control is valid. clear condition (acke0 = 0) note set condition (acke0 = 1) cleared by an instruction set by an instruction when reset is input note iice0 = 0 makes this flag signal invalid. 337 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-3. i 2 c bus control register (iicc0) format (3/4) stt0 start condition trigger 0 the start condition is not generated. 1 when the bus is released (stop condition): the start condition is generated (started as the master). the sda0 line is changed from high to low, and the start condition is generated. then, the standard time is guaranteed, and scl0 goes low. when not participating with the bus: the trigger functions as the start condition reserved flag. when set, the start condition is automatically generated after the bus is released. wait status (when master) the wait status is canceled and the restart condition is generated. set timing cautions when the master is receiving: setting during a transfer is prohibited. when acke0 = 0 is set, the end of reception can be set only during the wait period after the transmission to the slave. when the master is transmitting: during the ack0 acknowledge period, the start condition may not be normally generated. set stt0 during the wait period. setting synchronized to spt0 is prohibited. resetting between setting stt0 and the generation of the clear condition is prohibited. clear condition (stt0 = 0) note set condition (stt0 = 1) cleared by an instruction set by an instruction iice0 = 0 lrl0 = 1 when arbitration failed clear after generating the start condition in the master when reset is input note iice0 = 0 makes this flag signal invalid. 338 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-3. i 2 c bus control register (iicc0) format (4/4) spt0 stop condition trigger 0 the stop condition is not generated. 1 the stop condition is generated (ends the transfer as the master). after the sda0 line goes low, the scl0 line goes high, or wait until scl0 goes high. then, the standard time is guaranteed; the sda0 line is changed from low to high; and the stop condition is generated. set timing cautions when the master is receiving: setting is prohibited during a transfer. when acke0 = 0, the end of reception can be set only during the wait period after transmitting to the slave. when the master is transmitting: during the ack0 period, the stop condition may not be normally generated. set spt0 during the wait period. setting synchronized to stt0 is prohibited. resetting between setting spt0 and the generation of the clear condition is prohibited. set spt0 only by the master. note when wtim0 = 0 is set, be aware that if spt0 is set during the wait period after the eighth clock is output, the stop condition is generated during the high level of the ninth clock after the wait is released. when the ninth clock must be output, set wtim0 = 0 1 during the wait period after the eighth clock is output, and set spt0 during the wait period after the ninth clock is output. clear condition (spt0 = 0) set condition (spt0 = 1) cleared by an instruction set by an instruction iice0 = 0 lrel0 = 0 when arbitration failed automatically clear after the stop condition is detected when reset is input note set spt0 only by the master. however, spt0 must be set once, and the stop condition generated while the master is operating until the first stop condition is detected after operation is enabled. for details, refer to 19.5.15 additional cautions . cautions 1. when bit 3 (trc0) = 1 in the i 2 c bus status register (iics0), after wrel0 is set at the ninth clock and the wait is released, trc0 is cleared, and the sda0 line has a high impedance. 2. spt0 and stt0 are 0 when read after data has been set. remark std0: bit 1 in the i 2 c bus status register (iics0) ackd0: bit 2 in the i 2 c bus status register (iics0) trc0: bit 3 in the i 2 c bus status register (iics0) coi0: bit 4 in the i 2 c bus status register (iics0) exc0: bit 5 in the i 2 c bus status register (iics0) msts0: bit 7 in the i 2 c bus status register (iics0) 339 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (2) i 2 c bus status register (iics0) the iics0 register displays the status of the i 2 c bus. iics0 is set by a 1-bit or 8-bit memory manipulation instruction. iics0 can only be read. reset input sets iics0 to 00h. figure 19-4. i 2 c bus status register (iics0) format (1/3) address: 0ffb6h after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master state 0 slave state or communication wait state 1 master communication state clear condition (msts0 = 0) set condition (msts0 = 1) when the stop condition is detected when start condition is generated when ald0 = 1 cleared by lrel0 = 1 when iice0 = 1 0 when reset is input ald0 arbitration failed detection 0 no arbitration state or arbitration win state 1 arbitration failed state. msts0 is cleared. clear condition (ald0 = 0) set condition (ald0 = 1) automatically cleared after iics0 is read note when arbitration failed when iice0 = 1 0 when reset is input exc0 extended code reception detection 0 the extended code is not received. 1 the extended code is received. clear condition (exc0 = 0) set condition (exc0 = 1) when the start condition is detected when the most significant four bits of the received when the stop condition is detected address data are 0000 or 1111 (set by the rising cleared by lrel0 = 1 edge of the eighth clock) when iice0 = 1 0 when reset is input note this is cleared when a bit manipulation instruction is executed for a bit not in iics0. 340 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-4. i 2 c bus status register (iics0) format (2/3) coi0 address match detection 0 the address does not match. 1 the address matches. clear condition (coi0 = 0) set condition (coi0 = 1) during start condition detection when the received address matches the base during stop condition detection address (sva0) (set at the rising edge of the eighth cleared by lrel0 = 1 clock) when iice0 = 1 0 when reset is input trc0 transmission/reception state detection 0 reception state (not the transmission state). the sda0 line has high impedance. 1 transmission state. the value in the so latch can be output to the sda0 line (valid after the falling edge of the ninth clock of the first byte) clear condition (trc0 = 0) set condition (trc0 = 1) when the stop condition is detected in the master cleared by lrel0 = 1 when the start condition is generated when iice0 = 1 0 in the slave cleared by wrel0 = 1 note when 1 is input to the lsb of the first byte when ald0 = 0 1 (transfer direction specification bit) when reset is input in the master when 1 is output to the lsb of the first byte (transfer direction specification bit) in the slave when the start condition is detected when not participating in the communication ackd0 acknowledge detection 0 the acknowledge is not detected. 1 the acknowledge is detected. clear condition (ackd0 = 0) set condition (ackd0 = 1) when the stop condition is detected when the sda0 line is low at the rising edge of the at the rising edge of the first clock in the next byte ninth clock of scl0 cleared by lrel0 = 1 when iice0 = 1 0 when reset is input note if a wait is canceled by setting bit 5 (wrel0) of i 2 c bus control register 0 (iicc0) at the ninth clock while bit 3 (trc0) of i 2 c bus status register 0 (iics0) is 1, trc0 is cleared and the sda0 line becomes high impedance. 341 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-4. i 2 c bus status register (iics0) format (3/3) std0 start condition detection 0 the start condition is not detected. 1 the start condition is detected. this indicates the address transfer period. clear condition (std0 = 0) set condition (std0 = 1) when the stop condition is detected when the start condition is detected at the rising edge of the first clock of the next byte after transferring the address cleared by lrel0 = 1 when iice0 = 1 0 when reset is input spd0 stop condition detection 0 the stop condition is not detected. 1 the stop condition is detected. communication is ended by the master, and the bus is released. clear condition (spd0 = 0) set condition (spd0 = 1) after the bit is set, at the rising edge of the first when the stop condition is detected clock in the address transfer byte after detecting the start condition when iice0 = 1 0 when reset is input remark lrel0: bit 6 of the i 2 c bus control register (iicc0) iice0: bit 7 of the i 2 c bus control register (iicc0) 342 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (3) prescaler mode register for serial clock (sprm0) the sprm0 register sets the transfer clock of the i 2 c bus. sprm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sprm0 to 00h. figure 19-5. format of prescaler mode register for serial clock (sprm0) (1/2) address: 0ffb2h after reset: 00h r/w note symbol 7 6 <5> <4> 3210 sprm0 0 0 cld dad smc dfc cl1 cl0 cld scl0 line level detection (valid only when iice0 = 1) 0 detects a low scl0 line. 1 detects a high scl0 line. clear condition (cld = 0) set condition (cld = 1) when the scl0 line is low when the scl0 line is high when iice0 = 0 when reset is input dad sda0 line level detection (valid only when iice0 = 1) 0 detects a low sda0 line. 1 detects a high sda0 line. clear condition (dad = 0) set condition (dad = 1) when the sda0 line is low when the sda0 line is high when iice0 = 0 when reset is input note bits 4 and 5 are read only. 343 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-5. format of prescaler mode register for serial clock (sprm0) (2/2) smc note 1 dfc note 2 cl1 cl0 transfer clock f xx setting allowable range 0 1/0 0 0 f xx /44 2 to 4.19 mhz 0 1/0 0 1 f xx /86 4.19 to 8.38 mhz 0 1/0 1 0 f xx /172 8.38 to 12.5 mhz 0 1/0 1 1 tm2 output/66 1 1/0 0 1/0 f xx /24 4 to 8.38 mhz 1 1/0 1 0 f xx /48 8 to 12.5 mhz 1 1/0 1 1 tm2 output/18 notes 1. smc: bit to change operation mode 0: operates in normal mode 1: operates in high-speed mode 2. dfc: bit to control digital filter operation 0: digital filter off 1: digital filter on cautions 1. rewrite the sprm0 after clearing the iice0. 2. set the transfer clock as follows: when smc = 0: 100 khz or below when smc = 1: 400 khz or below remarks 1. iice0: bit 7 of i 2 c bus control register 0 (iicc0) 2. the transfer clock does not change due to the on/off setting of bit 2 (dfc) in high-speed mode. 3. iic clock: clock frequency when f xx /n is selected n t + t r + t f n/2 t n/2 t t r t f scln scln inverts scln inverts scln inverts iic clock frequency: f scl = 1/(n t + t r + t f ) example when f xx = 12.5 mhz, n = 172, t r = 200 ns, t f = 50 ns iic clock frequency: 1/(172 80 ns + 200 ns + 50 ns) ? 71.4 khz t = 1/f xx , t r : scln rise time, t f : scln fall time . . 344 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (4) serial shift register (iic0) this register performs serial communication (shift operation) synchronized to the serial clock. although this register can be read and written in 1-bit and 8-bit units, do not write data to iic0 during a data transfer. address: 0ffb8h after reset: 00h r/w symbol 76543210 iic0 (5) slave address register (sva0) this register stores the slave address of the i 2 c bus. it can be read and written in 8-bit units, but bit 0 is fixed at zero. address: 0ffb4h after reset: 00h r/w symbol 76543210 sva0 0 345 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud 19.4 i 2 c bus mode function 19.4.1 pin configuration the serial clock pin (scl0) and the serial data bus pin (sda0) have the following configurations. (1) scl0 ......... i/o pin for the serial clock the outputs to both the master and slave are n-channel open-drains. the input is a schmitt input. (2) sda0 ......... shared i/o pin for serial data the outputs to both the master and slave are n-channel open-drains. the input is a schmitt input. since the outputs of the serial clock line and serial data bus line are n-channel open-drains, external pull-up resistors are required. figure 19-6. pin configuration clock output (clock input) data output data input (clock output) clock input data output data input scl0 sda0 scl0 sda0 master device slave device v dd v dd 346 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud 19.5 i 2 c bus definitions and control method next, the serial data communication formats of the i 2 c bus and the meanings of the signals used are described. figure 19-7 shows the transfer timing of the start condition, data, and stop condition that are output on the serial data bus of the i 2 c bus. figure 19-7. serial data transfer timing of i 2 c bus scl0 sda0 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 start condition address r/w ack data ack data ack stop condition the master outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave (normally, this is output on side receiving 8-bit data). the serial clock (scl0) continues to the master output. however, the slave can extend the scl0 low-level period and insert waits. 19.5.1 start condition when the scl0 pin is high, the start condition is the sda0 pin changing from high to low. the start conditions for the scl0 and sda0 pins are the signals output when the master starts the serial transfer to the slave. the slave has hardware that detects the start condition. figure 19-8. start condition h sda0 scl0 the start condition is output when bit 1 (stt0) of the i 2 c bus control register (iicc0) is set to 1 in the stop condition detection state (spd0: when bit 0 in the i 2 c bus status register (iics0) = 1). in addition, when the start condition is detected, bit 1 (std0) in iics0 is set to 1. 347 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud 19.5.2 address the 7-bit data following the start condition defines the address. the address is 7-bit data that is output so that the master selects a specific slave from the multiple slaves connected to the bus line. therefore, the slaves on the bus line must have different addresses. the slave detects this condition by hardware, and determines whether the 7-bit data matches the slave address register (sva0). after the slave was selected when the 7-bit data matched the sva0 value, communication with the master continues until the master sends a start or stop condition. figure 19-9. address scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note when data other than base address or extended code was received during slave operation, intiic0 is not generated. the address is output by matching the slave address and the transfer direction described in 19.5.3 transfer direction specification to the serial shift register (iic0) in 8 bits. in addition, the received address is written to iic0. the slave address is allocated to the most significant seven bits of iic0. 19.5.3 transfer direction specification since the master specifies the transfer direction after the 7-bit address, 1-bit data is transmitted. a transfer direction specification bit of 0 indicates that the master transmits the data to the slave. a transfer direction specification bit of 1 indicates that the master receives the data from the slave. figure 19-10. transfer direction specification note when data other than base address or extended code is received during slave operation, intiic0 is not generated. scl0 sda0 intiic0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note 348 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.4 acknowledge signal (ack) the acknowledge signal verifies the reception of the serial data on the transmitting and receiving sides. the receiving side returns the acknowledge signal each time 8-bit data is received. usually, after transmitting 8- bit data, the transmitting side receives an acknowledge signal. however, if the master receives, the acknowledge signal is not output when the last data is received. after an 8-bit transmission, the transmitting side detects whether the receiving side returned an acknowledge signal. if an acknowledge signal is returned, the following processing is performed assuming that reception was correctly performed. since reception has not been performed correctly if the acknowledge signal is not returned from the slave, the master outputs the stop condition to stop transmission. if an acknowledge signal is not returned, the following two causes are considered. (1) the reception is not correct. (2) the last data has been received. when the receiving side sets the sda0 line low at the ninth clock, the acknowledge signal becomes active (normal reception response). if bit 2 (acke0) in the i 2 c bus control register (iicc0) = 1, the enable automatic generation of the acknowledge signal state is entered. bit 3 (trc0) in the i 2 c bus status register (iics0) is set by the data in the eighth bit following the 7-bit address information. however, set acke0 = 1 in the reception state when trc0 bit is 0. when the slave is receiving (trc0 = 0), the slave side receives multiple bytes and the next data is not required, when acke0 = 0, the master side cannot start the next transfer. similarly, the next data is not needed when the master is receiving (trc0 = 0), set acke0 = 0 so that the ack signal is not generated when you want to output a restart or stop condition. this prevents the output of msb data in the data on the sda0 line when the slave is transmitting (transmission stopped). figure 19-11. acknowledge signal scl0 sda0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when receiving the base address, the automatic output of the acknowledge is synchronized to the falling edge of the eighth clock of scl0 regardless of the acke0 value. when receiving at an address other than the base address, the acknowledge signal is not output. the output method of the acknowledge signal when receiving data is as follows based on the wait timing. 349 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud when 8 clock waits are selected: the acknowledge signal is synchronized to the falling edge of the eighth clock of scl output by setting acke0 = 1 before the wait is released. when 9 clock waits are selected: by setting acke0 = 1 beforehand, the acknowledge signal is synchronized to the falling edge of the eighth clock of scl0 and is automatically output. 19.5.5 stop condition when the scl0 pin is high and the sda0 pin changes from low to high, the stop condition results. the stop condition is the signal output by the master to the slave when serial transfer ends. the slave has hardware that detects the stop condition. figure 19-12. stop condition h sda0 scl0 the stop condition is generated when bit 0 (spt0) of the i 2 c bus control register (iicc0) is set to 1. and when the stop condition is detected, if bit 0 (spd0) in the i 2 c bus status register (iics0) is set to 1 and bit 4 (spie0) of iicc0 is also set to 1, intiic0 is generated. 350 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud 19.5.6 wait signal (wait) the wait signal notifies the other side that the master or slave is being prepared (wait state) for data communication. the wait state is notified to the other side by setting the scl0 pin low. when both the master and the slave are released from the wait state, the next transfer can start. figure 19-13. wait signal (1/2) (1) the master has a 9 clock wait, and the slave has an 8 clock wait (master: transmitting, slave: receiving, acke0 = 1) master slave transfer lines iic0 scl0 6789 123 the master returns to hi-z, but the slave waits (low level). wait after the ninth clock is output. iic0 data (wait release) wait after the eighth clock is output. iic0 ffh or wrel0 1 iic0 scl0 acke0 scl0 sda0 d2 d1 678 9 123 d0 ack d7 d6 d5 h 351 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud figure 19-13. wait signal (2/2) (2) both the master and slave have 9 clock waits (master: transmitting, slave: receiving, acke0 = 1) master slave transfer lines iic0 scl0 6789 23 both the master and slave wait after nine clocks are output. iic0 data (wait release) iic0 ffh or wrel0 1 iic0 scl0 scl0 sda0 d2 d1 6789 123 d0 ack d6 d5 acke0 h d7 output in accordance with the preset acke0 1 remark acke0: bit 2 in the i 2 c bus control register (iicc0) wrel0: bit 5 in the i 2 c bus control register (iicc0) a wait is automatically generated by setting bit 3 (wtim0) of the i 2 c bus control register (iicc0). normally, when bit 5 (wrel0) in iicc0 = 1 or ffh is written to the serial shift register (iic0), the receiving side releases the wait; when data is written to iic0, the transmitting side releases the wait. in the master, the wait can be released by the following methods. iicc0 bit 1 (stt0) = 1 iicc0 bit 0 (spt0) = 1 352 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud 19.5.7 i 2 c interrupt request (intiic0) this section describes the values of the i 2 c bus status register (iics0) at the intiic0 interrupt request generation timing and the intiic0 interrupt request timing. (1) master operation (a) start - address - data - data - stop (normal communication) <1> when wtim0 = 0 12 345 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st spt0 = 1 1: iics0 = 10 110b 2: iics0 = 10 000b 3: iics0 = 10 000b (wtim0 = 1) 4: iics0 = 10 00b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1234 spt0 = 1 1: iics0 = 10 110b 2: iics0 = 10 100b 3: iics0 = 10 00b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 353 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (b) start - address - data - start - address - data - stop (restart) <1> when wtim0 = 0 123 4567 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st spt0 = 1 stt0 = 1 1: iics0 = 10 110b 2: iics0 = 10 000b (wtim0 = 1) 3: iics0 = 10 00b (wtim0 = 0) 4: iics0 = 10 110b (wtim0 = 0) 5: iics0 = 10 000b (wtim0 = 1) 6: iics0 = 10 00b 7: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 12 345 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st spt0 = 1 stt0 = 1 1: iics0 = 10 110b 2: iics0 = 10 00b 3: iics0 = 10 110b 4: iics0 = 10 00b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 354 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (c) start - code - data - data - stop (extended code transmission) <1> when wtim0 = 0 12 345 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st spt0 = 1 1: iics0 = 1010 110b 2: iics0 = 1010 000b 3: iics0 = 1010 000b (wtim0 = 1) 4: iics0 = 1010 00b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 1234 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st spt0 = 1 1: iics0 = 1010 110b 2: iics0 = 1010 100b 3: iics0 = 1010 00b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 355 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (2) slave operation (when receiving slave address data (sva0 match)) (a) start - address - data - data - stop <1> when wtim0 = 0 12 34 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0001 000b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 1234 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 100b 3: iics0 = 0001 00b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 356 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (b) start - address - data - start - address - data - stop <1> when wtim0 = 0 (sva0 match after restart) 12 345 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0001 110b 4: iics0 = 0001 000b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 (sva0 match after restart) 12 345 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 00b 3: iics0 = 0001 110b 4: iics0 = 0001 00b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 357 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (c) start - address - data - start - code - data - stop <1> when wtim0 = 0 (extended code received after restart) 12 3 45 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0010 010b 4: iics0 = 0010 000b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 (extended code received after restart) 12 34 6 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 00b 3: iics0 = 0010 010b 4: iics0 = 0010 110b 5: iics0 = 0010 00b 6: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 358 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (d) start - address - data - start - address - data - stop <1> when wtim0 = 0 (no address match after restart (not extended code)) 12 3 4 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0000 10b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 (no address match after restart (not extended code)) 12 3 4 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 0001 110b 2: iics0 = 0001 00b 3: iics0 = 0000 10b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 359 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (3) slave operation (when receiving the extended code) (a) start - code - data - data - stop <1> when wtim0 = 0 234 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 0010 000b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 5 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 34 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 100b 4: iics0 = 0010 00b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 360 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (b) start - code - data - start - address - data - stop <1> when wtim0 = 0 (sva0 match after restart) 245 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 3 1 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 0001 110b 4: iics0 = 0001 000b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 (sva0 match after restart) 3456 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 2 1 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 00b 4: iics0 = 0001 110b 5: iics0 = 0001 00b 6: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 361 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (c) start - code - data - start - code - data - stop <1> when wtim0 = 0 (extended code received after restart) 245 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 3 1 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 0010 010b 4: iics0 = 0010 000b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 (extended code received after restart) 3567 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 4 2 1 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 00b 4: iics0 = 0010 010b 5: iics0 = 0010 110b 6: iics0 = 0010 00b 7: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 362 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (d) start - code - data - start - address - data - stop <1> when wtim0 = 0 (no address match after restart (not an extended code)) 24 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 3 1 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 00000 10b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 (no address match after restart (not an extended code)) 345 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 2 1 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 00b 4: iics0 = 00000 10b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care (4) not participating in communication (a) start - code - data - data - stop 1 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 00000001b remarks : generated only when spie0 = 1 363 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (5) arbitration failed operation (operates as the slave after arbitration fails) (a) when arbitration failed while transmitting slave address data <1> when wtim0 = 0 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 3 1: iics0 = 0101 110b ( example : read ald0 during interrupt servicing.) 2: iics0 = 0001 000b 3: iics0 = 0001 000b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 3 1: iics0 = 0101 110b ( example : read ald0 during interrupt servicing.) 2: iics0 = 0001 100b 3: iics0 = 0001 00b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 364 chapter 19 i 2 c bus mode ( user s manual u13570ej3v0ud (b) when arbitration failed while transmitting an extended code <1> when wtim0 = 0 1234 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 0110 010b ( example : read ald0 during interrupt servicing.) 2: iics0 = 0010 000b 3: iics0 = 0010 000b 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care <2> when wtim0 = 1 12 3 5 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 0110 010b ( example : read ald0 during interrupt servicing.) 2: iics0 = 0010 110b 3: iics0 = 0010 100b 4: iics0 = 0010 00b 5: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 365 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (6) arbitration failed operation (no participation after arbitration failed) (a) when arbitration failed while transmitting slave address data 12 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 01000110b ( example : read ald0 during interrupt servicing.) 2: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 (b) when arbitration failed while transmitting an extended code 12 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 0110 010b ( example : read ald0 during interrupt servicing.) set lrel0 = 1 from the software. 2: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 366 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (c) when arbitration failed during a data transfer <1> when wtim0 = 0 12 3 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 10001110b 2: iics0 = 01000000b ( example : read ald0 during interrupt servicing.) 3: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 <2> when wtim0 = 1 12 3 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1: iics0 = 10001110b 2: iics0 = 01000100b ( example : read ald0 during interrupt servicing.) 3: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 367 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (d) when failed in the restart condition during a data transfer <1> not an extended code (example: sva0 match) 123 rw ak ad6 to ad0 d7 to dn st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 1000 110b 2: iics0 = 01000110b ( example : read ald0 during interrupt servicing.) 3: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care dn = d6 to d0 <2> extended code 123 rw ak ad6 to ad0 d7 to dn st rw ak ad6 to ad0 sp ak d7 to d0 st 1: iics0 = 1000 110b 2: iics0 = 0110 010b ( example : read ald0 during interrupt servicing.) iicc0:lrel0 = 1 set by software. 3: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care dn = d6 to d0 368 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (e) when failed in the stop condition during a data transfer 12 rw ak ad6 to ad0 d7 to dn st sp 1: iics0 = 1000 110b 2: iics0 = 01000001b remarks : always generated. : generated only when spie0 = 1 : don t care dn = d6 to d0 (f) when arbitration failed at a low data level and the restart condition was about to be generated when wtim0 = 1 123 stt0 = 1 4 rw ak ad6 to ad0 d7 to d0 st ak sp ak d7 to d0 ak d7 to d0 1: iics0 = 1000 110b 2: iics0 = 1000 00b 3: iics0 = 01000100b ( example : read ald0 during interrupt servicing.) 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care (g) when arbitration failed in a stop condition and the restart condition was about to be generated when wtim0 = 1 stt0 = 1 123 rw ak ad6 to ad0 d7 to d0 st sp ak 1: iics0 = 1000 110b 2: iics0 = 1000 00b 3: iics0 = 01000001b remarks : always generated. : generated only when spie0 = 1 : don t care 369 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (h) when arbitration failed in the low data level and the stop condition was about to be generated when wtim0 = 1 123 spt0 = 1 4 rw ak ad6 to ad0 d7 to d0 st ak sp ak d7 to d0 ak d7 to d0 1: iics0 = 1000 110b 2: iics0 = 1000 00b 3: iics0 = 01000000b ( example : read ald0 during interrupt servicing) 4: iics0 = 00000001b remarks : always generated. : generated only when spie0 = 1 : don t care 370 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.8 interrupt request (intiic0) generation timing and wait control by setting the wtim0 bit in the i 2 c bus control register (iicc0), intiic0 is generated at the timing shown in table 19-2 and wait control is performed. table 19-2. intiic0 generation timing and wait control wtim0 during slave operation during master operation address data reception data transmission address data reception data transmission 09 notes 1, 2 8 note 2 8 note 2 988 19 notes 1, 2 9 note 2 9 note 2 999 notes 1. the intiic0 signal and wait of the slave are generated on the falling edge of the ninth clock only when the address set in the slave address register (sva0) matches. in this case, ack is output regardless of the acke0 setting. the slave that received the extended code generates intiic0 at the falling edge of the eighth clock. 2. when the address that received sva0 does not match, intiic0 and wait are not generated. remark the numbers in the table indicate the number of clocks in the serial clock. in addition, the interrupt request and wait control are both synchronized to the falling edge of the serial clock. (1) when transmitting and receiving an address when the slave is operating: the interrupt and wait timing are determined regardless of the wtim0 bit. when the master is operating: the interrupt and wait timing are generated by the falling edge of the ninth clock regardless of the wtim0 bit. (2) when receiving data when the master and slave are operating: the interrupt and wait timing are set by the wtim0 bit. (3) when transmitting data when the master and slave are operating: the interrupt and wait timing are set by the wtim0 bit. 371 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (4) releasing a wait the following four methods release a wait. wrel0 = 1 in the i 2 c bus control register (iicc0) writing to the serial shift register (iic0) setting the start condition (stt0 = 1 in iicc0) setting the stop condition (spt0 = 1 in iicc0) when eight clock waits are selected (wtim0 = 0), the output level of ack must be determined before releasing the wait. (5) stop condition detection intiic0 is generated when the stop condition is detected. 19.5.9 address match detection in the i 2 c bus mode, the master can select a specific slave device by transmitting the slave address. an address match is automatically detected by the hardware. when the base address is set in the slave address register (sva0), if the slave address transmitted from the master matches the address set in sva0, or if the extended code is received, an intiic0 interrupt request occurs. 19.5.10 error detection in the i 2 c bus mode, since the state of the serial bus (sda0) during transmission is introduced into the serial shift register (iic0) of the transmitting device, transmission errors can be detected by comparing the iic0 data before and after the transmission. in this case, if two data differ, the decision is that a transmission error was generated. 372 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.11 extended codes (1) if the most significant four bits of the receiving address are 0000 or 1111, an extended code is received and the extended code received flag (exc0) is set. the interrupt request (intiic0) is generated at the falling edge of the eighth clock. the base address stored in the slave address register (sva0) is not affected. (2) in 10-bit address transfers, the following occurs when 111110 is set in sva0 and 111110 0 is transferred from the master. however, intiic0 is generated at the falling edge of the eighth clock. most significant 4 bits of data match: exc0 = 1 note 7-bit data match: coi0 = 1 note note exc0: bit 5 of the i 2 c bus status register (iics0) coi0: bit 4 of the i 2 c bus status register (iics0) (3) since the processing after an interrupt request is generated differs depending on the data that follows the extended code, the software performs this processing. for example, when operation as a slave is not desired after an extended code is received, enter the next communication wait state by setting bit 6 (lrel0) of the i 2 c bus control register (iicc0) to 1. table 19-3. definitions of extended code bits slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 cbus address 0000 010 address reserved in the different bus format 1111 0 10-bit slave address setting 19.5.12 arbitration when multiple masters simultaneously output start conditions (when stt0 = 1 occurs before std0 = 1 note ), the master communicates while the clock is adjusted until the data differ. this operation is called arbitration. a master that failed arbitration sets the arbitration failed flag (ald0) of the i 2 c bus status register (iics0) at the timing of the failed arbitration. the scl0 and sda0 lines enter the high impedance state, and the bus is released. failed arbitration is detected when ald0 = 1 by software at the timing of the interrupt request generated next (eighth or ninth clock, stop condition detection, etc.). at the timing for generating the interrupt request, refer to 19.5.7 i 2 c interrupt request (intiic0) . note std0: bit 1 in the i 2 c bus status register (iics0) stt0: bit 1 in the i 2 c bus control register (iicc0) 373 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-14. example of arbitration timing scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 arbitration failed master 1 master 2 transfer lines table 19-4. arbitration generation states and interrupt request generation timing arbitration generation state interrupt request generation timing during address transmission falling edge of clock 8 or 9 after byte transfer note 1 read/write information after address transmission during extended code transmission read/write information after extended code transmission during data transmission during ack transfer period after data transmission restart condition detection during data transfer stop condition detection during data transfer when stop condition is output (spie0 = 1) note 2 data is low when the restart condition is about to be falling edge of clock 8 or 9 after byte transfer note 1 output. the restart condition should be output, but the stop stop condition is output (spie0 = 1) note 2 condition is detected. data is low when the stop condition is about to be output. falling edge of clock 8 or 9 after byte transfer note 1 scl0 is low when the restart condition is about to be output. notes 1. if wtim0 = 1 (bit 3 = 1 in the i 2 c bus control register (iicc0)), an interrupt request is generated at the timing of the falling edge of the ninth clock. if wtim0 = 0 and the slave address of the extended code is received, an interrupt request is generated at the timing of the falling edge of the eighth clock. 2. when arbitration is possible, use the master to set spie0 = 1. remark spie0: bit 5 in the i 2 c bus control register (iicc0) 374 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.13 wake-up function this is a slave function of the i 2 c bus and generates the interrupt request (intiic0) when the base address and extended code were received. when the address does not match, an unused interrupt request is not generated, and efficient processing is possible. when the start condition is detected, the wake-up standby function is entered. since the master can become a slave in an arbitration failure (when a start condition was output), the wake-up standby function is entered while the address is transmitted. however, when the stop condition is detected, the generation of interrupt requests is enabled or disabled based on the setting of bit 5 (spie0) in the i 2 c bus control register (iicc0) unrelated to the wake-up function. 375 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.14 communication reservation when you want the master to communicate after being in the not participating state in the bus, the start condition can be transmitted when a bus is released by reserving communication. the following two states are included when the bus does not participate. when there was no arbitration in the master and the slave when the extended code is received and operation is not as a slave (bus released when ack is not returned, and bit 6 (lrel0) = 1 in the i 2 c bus control register (iicc0)) when bit 1 (stt0) of iicc0 is set in the not participating state in the bus, after the bus is released (after stop condition detection), the start condition is automatically generated, and the wait state is entered. when the bus release is detected (stop condition detection), the address transfer starts as the master by the write operation of the serial shift register (iic0). in this case, set bit 4 (spie0) in iicc0. when stt0 is set, whether it operates as a start condition or for communication reservation is determined by the bus state. when the bus is released start condition generation when the bus is not released (standby state) communication reservation to verify whether stt0 operates as a communication reservation, set stt0 and use msts0 (bit 7 in the i 2 c bus status register (iics0)) after the wait time elapses. use the software to save the wait time which is a time listed in table 19-5. the wait time can be set by bits 3, 1, and 0 (smc, cl1, and cl0) in the prescaler mode register for the serial clock (sprm0). table 19-5. wait times smc cl1 cl0 wait time 0 0 0 26 clocks 1/f xx 0 0 1 46 clocks 1/f xx 0 1 0 92 clocks 1/f xx 0 1 1 37 clocks 1/tm2 output 1 0 0 16 clocks 1/f xx 10 1 1 1 0 32 clocks 1/f xx 1 1 1 13 clocks 1/tm2 output 376 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-15 shows the timing of communication reservation. figure 19-15. timing of communication reservation program processing hardware processing scl0 1 2 3 4 5 6 1 2 3 4 5 6 789 sda0 communi- cation reserva- tion stt0 = 1 iic0 write std0 setting spd0 and intiic0 settings output from the master that possessed the bus iic0: serial shift register stt0: bit 1 in the i 2 c bus control register (iicc0) std0: bit 1 in the i 2 c bus status register (iics0) spd0: bit 0 in the i 2 c bus status register (iics0) the communication reservation is accepted at the following timing. after bit 1 (std0) = 1 in the i 2 c bus status register (iics0), the communication is reserved by bit 1 (stt0) = 1 in the i 2 c bus control register (iicc0) until the stop condition is detected. figure 19-16. communication reservation acceptance timing scl0 sda0 std0 spd0 wait state 377 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-17 shows the communication reservation procedure. figure 19-17. communication reservation procedure note when the communication is being reserved, the serial shift register (iic0) is written by the stop condition interrupt. remark stt0: bit 1 in the i 2 c bus control register (iicc0) msts0: bit 7 in the i 2 c bus status register (iics0) iic0: serial shift register di set1 stt0 define communication reservation. communication reservation is released. mov iic0, # h ei wait msts0 = 0? ; set the stt0 flag (communication reservation). ; define that communication is being reserved. (defines and sets the user flag to any ram.) ; clear the user flag. ; iic0 write ; save the wait time by the software (see table 19-5 ). ; check communication reservation. yes (communication reservation) note no (start condition generated) 378 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.15 additional cautions after a reset, when the master is communicating from the state where the stop condition is not detected (bus is not released), perform master communication after the stop condition is first generated and the bus is released. the master cannot communicate in the state where the bus is not released (the stop condition is not detected) in the multi-master. the following procedure generates the stop condition. <1> set the prescaler mode register for the serial clock (sprm0). <2> set bit 7 (iice0) in the i 2 c bus control register (iicc0). <3> set bit 0 of iicc0. 379 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.5.16 communication operation (1) master operation the following example shows the master operating procedure. figure 19-18. master operating procedure iiccl0 h select the transfer clock start iic0 write transfer. iicc0 h iice0 = spie0 = wtim0 =1 stt0 = 1 intiic0 = 1? intiic0 = 1? start iic0 write transfer. stop condition generation (no slave with address match) intiic0 = 1? ackd0 = 1? ackd0 = 1? trc0 = 1? start yes no yes no yes no yes no yes no yes (transmission) no (reception) no yes no ; address transfer ends ; stop condition detection data processing wtim0 = 0 acke0 = 1 wrel0 = 1 start reception. intiic0 = 1? transfer ends? data processing acke0 = 0 generate restart condition or stop condition. 380 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud (2) slave operation the following example is the slave operating procedure. figure 19-19. slave operating procedure iicc0 h iice0 = 1 intiic0 = 1? exc0 = 1? intiic0 = 1? ackd0 = 1? coi0 = 1? trc0 = 1? start yes no no yes yes no yes no yes no yes no no yes no data processing wtim0 = 0 acke0 = 1 wrel0 = 1 start reception. intiic0 = 1? transfer ends? data processing acke0 = 0 detect restart condition or stop condition. participate in communication? yes no wtim0 = 1 start iic0 write transfer. lrel0 = 1 381 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud 19.6 timing charts in the i 2 c bus mode, the master outputs an address on the serial bus and selects one of the slave devices from multiple slave devices as the communication target. the master transmits the trc0 bit, bit 3 of the i 2 c bus status register (iics0), that indicates the transfer direction of the data after the slave address and starts serial communication with the slave. figures 19-20 and 19-21 are the timing charts for data communication. shifting of the shift register (iic0) is synchronized to the falling edge of the serial clock (scl0). the transmission data is transferred to the so0 latch and output from the sda0 pin with the msb first. the data input at the sda0 pin is received by iic0 at the rising edge of scl0. 382 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-20. master slave communication example (when master and slave select 9 clock waits) (1/3) (1) start condition - address note release the slave wait by either iic0 ffh or setting wrel0. iic0 address iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 h h l h h h l l l l receive send 1 a6 start condition a5 a4 a3 a2 a1 a0 w d7 note iic0 ffh note (when exc0 = 1) d6 d5 d4 ack 23456789 1234 iic0 data master device process slave device process transfer lines 383 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-20. master slave communication example (when master and slave select 9 clock waits) (2/3) (2) data note release the slave wait by either iic0 ffh or setting wrel0. iic0 data iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 scl0 sda0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 h h h l l l l l h h l l l l l l h send receive note note iic0 data master device process slave device process transfer lines 1 9 d0 8 d7 d6 d5 d4 d3 d2 d1 d0 d7 iic0 ffh note iic0 ffh note d6 d5 23456789 123 384 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-20. master slave communication example (when master and slave select 9 clock waits) (3/3) (3) stop condition note release the slave wait by either iic0 ffh or setting wrel0. iic0 data iic0 ffh note iic0 ffh note note note iic0 address iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 h h h h h l l l l receive send 12 1 a6 stop condition start condition d0 d1 d2 d3 d4 d5 d6 d7 a5 2 3456789 (when spie0 = 1) (when spie0 = 1) l master device process slave device process transfer lines 385 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-21. slave master communication example (when master and slave select 9 clock waits) (1/3) (1) start condition - address iic0 address iic0 ffh note iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 l h h l l l l note h h 1 a6 a5 a4 a3 a2 d6 d7 d5 d4 d3 d2 a1 a0 r iic0 data start condition 23456 123456 789 master device process slave device process transfer lines note release the slave wait by either iic0 ffh or setting wrel0. 386 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-21. slave master communication example (when master and slave select 9 clock waits) (2/3) (2) data iic0 ffh note iic0 ffh note iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 l l h h h l l l l l h h l l l l h send note note receive 1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack d7 d6 d5 ack iic0 data iic0 data 23 1 2 3 456789 89 master device process slave device process transfer lines note release the slave wait by either iic0 ffh or setting wrel0. 387 chapter 19 i 2 c bus mode ( pd784216ay, 784218ay subseries only) user s manual u13570ej3v0ud figure 19-21. slave master communication example (when master and slave select 9 clock waits) (3/3) (3) stop condition iic0 address iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 h h h h l l l note 1 d7 a6 a5 d6 d5 d4 d3 d2 d1 d0 n-ack iic0 ffh note iic0 data stop condition start condition (when spie0 = 1) (when spie0 = 1) 2 12 3456789 master device process slave device process transfer lines note release the slave wait by either iic0 ffh or setting wrel0. 388 user s manual u13570ej3v0ud chapter 20 clock output function 20.1 functions the clock output function is used to output the clock supplied to a peripheral lsi and carrier output during remote transmission. the clock selected by means of the clock output control register (cks) is output from the pcl/p23 pin. to output the clock pulse, follow the procedure described below. <1> select the output frequency of the clock pulse (while clock pulse output is disabled) with bits 0 to 3 (ccs0 to ccs3) of cks. <2> set 0 in output latch p23. <3> set bit 3 (pm23) of the port 2 mode register (pm2) to 0 (to set the output mode). <4> set bit 4 (cloe) of cks to 1. caution if the output latch of p23 is set to 1, clock output cannot be used. remark the clock output function is designed so that pulses with a narrow width are not output when clock output enable/disable is switched (see * ?in figure 20-1 ). figure 20-1. remote control output application example cloe pcl/p23 pin output ** 389 chapter 20 clock output function user s manual u13570ej3v0ud 20.2 configuration the clock output function consists of the following hardware. table 20-1. clock output function configuration item configuration control register clock output control register (cks) port 2 mode register (pm2) figure 20-2. clock output function block diagram 20.3 control registers the following two types of registers are used to control the clock output function. clock output control register (cks) port 2 mode register (pm2) (1) clock output control register (cks) this register sets the pcl output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets cks to 00h. remark cks provides a function for setting the buzzer output clock besides setting the pcl output clock. cloe ccs3 ccs2 ccs1 ccs0 internal bus synchronous circuit pcl/p23 clock output control register (cks) f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 4 f xx f xt f xx /2 f xx /2 2 port 2 mode register (pm2) pm23 p23 output latch selector 390 chapter 20 clock output function user s manual u13570ej3v0ud figure 20-3. clock output control register (cks) format address: 0ff40h after reset: 00h r/w symbol 76543210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buzzer output control (see figure 21-2 ) bcs1 bcs0 buzzer output frequency selection (see figure 21-2 ) cloe clock output control 0 clock output stop 1 clock output start ccs3 ccs2 ccs1 ccs0 clock output frequency selection 0000f xx (12.5 mhz) 0001f xx /2 (6.25 mhz) 0010f xx /4 (3.13 mhz) 0011f xx /8 (1.56 mhz) 0100f xx /16 (781 khz) 0101f xx /32 (391 khz) 0110f xx /64 (195 khz) 0111f xx /128 (97.7 khz) 1000f xt (32.768 khz) other than above setting prohibited remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. figures in parentheses apply to operation with f xx = 12.5 mhz or f xt = 32.768 khz. 391 chapter 20 clock output function user s manual u13570ej3v0ud (2) port 2 mode register (pm2) this register sets input/output for port 2 in 1-bit units. when using the p23/pcl pin for clock output, set the output latches of pm23 and p23 to 0. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 20-4. port 2 mode register (pm2) format address: 0ff22h after reset: ffh r/w symbol 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n p2n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 392 user s manual u13570ej3v0ud chapter 21 buzzer output functions 21.1 function this function outputs a square wave at the frequencies of 1.5 khz, 3.1 khz, 6.1 khz, and 12.2 khz. the buzzer frequency selected by the clock output control register (cks) is output from the buz/p24 pin. the following procedure outputs the buzzer frequency. <1> select the buzzer output frequency by using bits 5 to 7 (bcs0, bcs1, bzoe) of cks. <2> set the p24 output latch to 0. <3> set bit 4 (pm24) of the port 2 mode register (pm2) to 0 (set the output mode). caution when the output latch of p24 is set to 1, the buzzer output cannot be used. 21.2 configuration the buzzer output function consists of the following hardware. table 21-1. buzzer output function configuration item configuration control register clock output control register (cks) port 2 mode register (pm2) figure 21-1. buzzer output function block diagram f xx /2 10 f xx /2 11 3 buz/p24 bzoe bcs1 bcs0 p24 output latch pm24 selector port 2 mode register (pm2) internal bus f xx /2 12 f xx /2 13 clock output control register (cks) 393 chapter 21 buzzer output functions user s manual u13570ej3v0ud 21.3 control registers the buzzer output function is controlled by the following two registers. clock output control register (cks) port 2 mode register (pm2) (1) clock output control register (cks) this register sets the frequency of the buzzer output. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets cks to 00h. remark cks has the function of setting the clock for pcl output except for the buzzer output frequency setting. figure 21-2. clock output control register (cks) format address: 0ff40h after reset: 00h r/w symbol 76543210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buzzer output control 0 stop buzzer output 1 start buzzer output bcs1 bcs0 buzzer output frequency selection 00f xx /2 10 (12.2 khz) 01f xx /2 11 (6.1 khz) 10f xx /2 12 (3.1 khz) 11f xx /2 13 (1.5 khz) cloe clock output control (refer to figure 20-3 ) ccs3 ccs2 ccs1 ccs0 clock output frequency selection (refer to figure 20-3 ) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. figures in parentheses apply to operation with f xx = 12.5 mhz. 394 chapter 21 buzzer output functions user s manual u13570ej3v0ud (2) port 2 mode register (pm2) this register sets port 2 i/o in 1-bit units. when the p24/buz pin is used as the buzzer output function, set the output latches of pm24 and p24 to 0. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 21-3. port 2 mode register (pm2) format address: 0ff22h after reset: ffh r/w symbol 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n p2n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 395 user s manual u13570ej3v0ud chapter 22 edge detection function the p00 to p06 pins have an edge detection function that can be programmed to detect the rising edge or falling edge and sends the detected edge to on-chip hardware components. the edge detection function is always functioning, even in the stop mode and idle mode. 22.1 control registers external interrupt rising edge enable register (egp0), external interrupt falling edge enable register (egn0) the egp0 and egn0 registers specify the effective edge to be detected by the p00 to p06 pins. they can read/write with an 8-bit manipulation instruction or a bit manipulation instruction. reset input sets the egp0 and egn0 to 00h. figure 22-1. format of external interrupt rising edge enable register (egp0) and external interrupt falling edge enable register (egn0) address: 0ffa0h after reset: 00h r/w symbol 76543210 egp0 0 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: 0ffa2h after reset: 00h r/w symbol 76543210 egn0 0 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin effective edge (n = 0 to 6) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges 396 chapter 22 edge detection function user s manual u13570ej3v0ud 22.2 edge detection of p00 to p06 pins the p00 to p06 pins do not incorporate an analog delay-based noise eliminator. therefore, a valid edge is input to the pins and edge detection is performed (acknowledged) immediately after passing through the hysteresis-type input buffer. figure 22-2. block diagram of p00 to p06 pins p00 to p06 input mode (during input mode) edge detector intp0, intp1, intp2/nmi intp3 to intp6 (to interrupt controller) p00 to p06 output mode (during output mode) p00 to p06 397 user s manual u13570ej3v0ud chapter 23 interrupt functions the pd784218a is provided with three interrupt request service modes; vectored interrupt, context switching, and macro service (refer to table 23-1 ). these three service modes can be set as required in the program. however, interrupt service by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in table 23-2. context switching cannot be selected for non-maskable interrupts or operand error interrupts. multiple-interrupt control using 4 priority levels can easily be performed for maskable vectored interrupts. table 23-1. interrupt request service modes interrupt request servicing performed pc & psw contents service service mode vectored interrupts software saving to & restoration executed by branching to service program from stack at address note specified by vector table context switching saving to & restoration executed by automatic switching to register from fixed area in bank specified by vector table and register bank branching to service program at address note specified by fixed area in register bank macro service hardware retained execution of pre-set service such as data (firmware) transfers between memory and i/o note the start addresses of all interrupt service programs must be in the base area. if the body of a service program cannot be located in the base area, a branch instruction to the service program should be written in the base area. 398 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.1 interrupt request sources the pd784218a has 32 interrupt request sources as shown in table 23-2, with an interrupt vector table allocated to each. table 23-2. interrupt request sources (1/2) type of default interrupt request generating interrupt context macro macro vector interrupt priority generating source unit control switching service service table request register control address name word address software none brk instruction execution not not 003eh possible possible brkcs instruction execution possible not possible operand none invalid operand in mov stbc, not not 003ch error #byte instruction or mov wdm, possible possible (trap0) #byte instruction, and location instruction non- none nmi (pin input edge detection) edge not not 0002h maskable detection possible possible intwdt (watchdog timer watchdog not not 0004h overflow) timer possible possible 399 chapter 23 interrupt functions user s manual u13570ej3v0ud table 23-2. interrupt request sources (2/2) note pd784216ay, 784218ay subseries only type of default interrupt request generating interrupt context macro macro vector interrupt priority generating source unit control switching service service table request register control address name word address maskable 0 intwdtm ( watchdog timer overflow) watchdog wdtic possible possible 0fe06h 0006h timer 1 intp0 (pin input edge detection) edge pic0 0fe08h 0008h 2 intp1 (pin input edge detection) detection pic1 0fe0ah 000ah 3 intp2 (pin input edge detection) pic2 0fe0ch 000ch 4 intp3 (pin input edge detection) pic3 0fe0eh 000eh 5 intp4 (pin input edge detection) pic4 0fe10h 0010h 6 intp5 (pin input edge detection) pic5 0fe12h 0012h 7 intp6 (pin input edge detection) pic6 0fe14h 0014h 8 intiic0 (csi0 i 2 c bus transfer end) note clocked csiic0 0fe16h 0016h intcsi0 (csi0 3-wire transfer end) serial interface 9 intser1 (asi1 uart reception error) asynchronous seric1 0fe18h 0018h 10 intsr1 (asi1 uart reception end) serial interface/ sric1 0fe1ah 001ah intcsi1 (csi1 3-wire transfer end) clocked 11 intst1 (asi1 uart transmission end) serial interface 1 stic1 0fe1ch 001ch 12 intser2 (asi2 uart reception error) asynchronous seric2 0fe1eh 001eh 13 intsr2 (asi2 uart reception end) serial interface/ sric2 0fe20h 0020h intcsi2 (csi2 3-wire transfer end) clocked 14 intst2 (asi2 uart transmission end) serial interface 2 stic2 0fe22h 0022h 15 inttm3 (reference time interval watch tmic3 0fe24h 0024h signal from watch timer) timer 16 inttm00 (match signal generation timer/ tmic00 0fe26h 0026h of 16-bit timer register and capture/ counter compare register (cr00)) 17 inttm01 (match signal generation tmic01 0fe28h 0028h of 16-bit timer register and capture/ compare register (cr01)) 18 inttm1 (match signal generation timer/ tmic1 0fe2ah 002ah of 8-bit timer/counter 1) counter 1 19 inttm2 (match signal generation timer/ tmic2 0fe2ch 002ch of 8-bit timer/counter 2) counter 2 20 intad (a/d converter conversion end) a/d converter adic 0fe2eh 002eh 21 inttm5 (match signal generation timer/ tmic5 0fe30h 0030h of 8-bit timer/counter 5) counter 5 22 inttm6 (match signal generation timer/ tmic6 0fe32h 0032h of 8-bit timer/counter 6) counter 6 23 inttm7 (match signal generation timer/ tmic7 0fe34h 0034h of 8-bit timer/counter 7) counter 7 24 inttm8 (match signal generation timer/ tmic8 0fe36h 0036h of 8-bit timer/counter 8) counter 8 25 intwt (watch timer overflow) watch timer wtic 0fe38h 0038h 26 intkr (falling edge detection of port 8) edge detection kric 0fe3ah 003ah 400 chapter 23 interrupt functions user s manual u13570ej3v0ud remarks 1. the default priority is a fixed number. this indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously. 2. asi: asynchronous serial interface csi: clocked serial interface 3. the watchdog timer has two interrupt sources, a non-maskable interrupt (intwdt) and a maskable interrupt (intwdtm), either (but not both) of which can be selected. 23.1.1 software interrupts interrupts by software consist of the brk instruction which generates a vectored interrupt and the brkcs instruction which performs context switching. software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 23.1.2 operand error interrupts these interrupts are generated if there is an illegal operand in an mov stbc, #byte instruction or mov wdm, #byte instruction, and location instruction. operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 23.1.3 non-maskable interrupts a non-maskable interrupt is generated by nmi pin input or the watchdog timer. non-maskable interrupts are acknowledged unconditionally note , even in the interrupt disabled state. they are not subject to interrupt priority control, and are of higher priority than any other interrupt. note except during execution of the service program for the same non-maskable interrupt, and during execution of the service program for a higher-priority non-maskable interrupt 23.1.4 maskable interrupts a maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. in addition, acknowledgement enabling/disabling can be specified for all maskable interrupts by means of the ie flag in the program status word (psw). in addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro service (though some interrupts cannot use macro service: refer to table 23-2 ). the priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined (default priority) as shown in table 23-2. also, multiprocessing control can be performed with interrupt priorities divided into 4 levels. however, macro service requests are acknowledged without regard to priority control or the ie flag. 401 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.2 interrupt service modes there are three pd784218a interrupt service modes, as follows: vectored interrupt service macro service context switching 23.2.1 vectored interrupt service when an interrupt is acknowledged, the program counter (pc) and program status word (psw) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt service routine is executed. 23.2.2 macro service when an interrupt is acknowledged, cpu execution is temporarily suspended and a data transfer is performed by hardware. since macro service is performed without the intermediation of the cpu, it is not necessary to save or restore cpu statuses such as the program counter (pc) and program status word (psw) contents. this is therefore very effective in improving the cpu service time (refer to 23.8 macro service function ). 23.2.3 context switching when an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a pre-set vector address in the register bank, and at the same time the current program counter (pc) and program status word (psw) are saved in the register bank (refer to 23.4.2 brkcs instruction software interrupt (software context switching) acknowledgement operation and 23.7.2 context switching ). remark ?ontext?refers to the cpu registers that can be accessed by a program while that program is being executed. these registers include general registers, the program counter (pc), program status word (psw), and stack pointer (sp). 402 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3 interrupt processing control registers pd784218a interrupt processing is controlled for each interrupt request by various control registers that perform interrupt processing specification. the interrupt control registers are listed in table 23-3. table 23-3. control registers register name symbol function interrupt control registers wdtic, pic0, pic1, pic2, registers to record generation of interrupt request, control pic3, pic4, pic5, pic6, masking, specify vectored interrupt processing or macro csiic0, seric1, sric1, service processing, enable or disable context switching stic1, seric2, sric2, function, and specify priority. stic2, tmic3, tmic00, tmic01, tmic1, tmic2, adic, tmic5, tmic6, tmic7, tmic8, wtic, kric interrupt mask registers mk0 (mk0l, mk0h) control masking of maskable interrupt request. associated mk1 (mk1l, mk1h) with mask control flag in interrupt control register. can be accessed in word or byte units. in-service priority register ispr records priority of interrupt request currently acknowledged. interrupt mode control register imc controls nesting of maskable interrupt with priority specified to lowest level (level 3). interrupt selection control snmi selects whether to use input signal from p02 pin and register interrupt signal from watchdog timer as maskable interrupt or nmi. watchdog timer mode register wdm specifies priorities of interrupt by nmi pin input and overflow of watchdog timer. program status word psw enables or disables accepting maskable interrupt. an interrupt control register is allocated to each interrupt source. the flags of each register perform control of the contents corresponding to the relevant bit position in the register. the interrupt control register flag names corresponding to each interrupt request signal are shown in table 23-4. 403 chapter 23 interrupt functions user s manual u13570ej3v0ud table 23-4. flag list of interrupt control registers for interrupt requests default interrupt interrupt control register priority request interrupt interrupt macro service priority speci- context switching signal request flag mask flag enable flag fication flag enable flag 0 intwdtm wdtic wdtif wdtmk wdtism wdtpr0 wdtcse wdtpr1 1 intp0 pic0 pif0 pmk0 pism0 ppr00 pcse0 ppr01 2 intp1 pic1 pif1 pmk1 pism1 ppr10 pcse1 ppr11 3 intp2 pic2 pif2 pmk2 pism2 ppr20 pcse2 ppr21 4 intp3 pic3 pif3 pmk3 pism3 ppr30 pcse3 ppr31 5 intp4 pic4 pif4 pmk4 pism4 ppr40 pcse4 ppr41 6 intp5 pic5 pif5 pmk5 pism5 ppr50 pcse5 ppr51 7 intp6 pic6 pif6 pmk6 pism6 ppr60 pcse6 ppr61 8 intiic0 csiic0 csiif0 csimk0 csiism0 csipr00 csicse0 intcsi0 csipr01 9 intser1 seric1 serif1 sermk1 serism1 serpr10 sercse1 serpr11 10 intsr1 sric1 srif1 srmk1 srism1 srpr10 srcse1 intcsi1 srpr11 11 intst1 stic1 stif1 stmk1 stism1 stpr10 stcse1 stpr11 12 intser2 seric2 serif2 sermk2 serism2 serpr20 sercse2 serpr21 13 intsr2 sric2 srif2 srmk2 srism2 srpr20 srcse2 intcsi2 srpr21 14 intst2 stic2 stif2 stmk2 stism2 stpr20 stcse2 stpr21 15 inttm3 tmic3 tmif3 tmmk3 tmism3 tmpr30 tmcse3 tmpr31 16 inttm00 tmic00 tmif00 tmmk00 tmism00 tmpr000 tmcse00 tmpr001 17 inttm01 tmic01 tmif01 tmmk01 tmism01 tmpr010 tmcse01 tmpr011 18 inttm1 tmic1 tmif1 tmmk1 tmism1 tmpr10 tmcse1 tmpr11 19 inttm2 tmic2 tmif2 tmmk2 tmism2 tmpr20 tmcse2 tmpr21 20 intad adic adif admk adism adpr00 adcse adpr01 21 inttm5 tmic5 tmif5 tmmk5 tmism5 tmpr50 tmcse5 tmpr51 22 inttm6 tmic6 tmif6 tmmk6 tmism6 tmpr60 tmcse6 tmpr61 23 inttm7 tmic7 tmif7 tmmk7 tmism7 tmpr70 tmcse7 tmpr71 24 inttm8 tmic8 tmif8 tmmk8 tmism8 tmpr80 tmcse8 tmpr81 25 intwt wtic wtif wtmk wtism wtpr0 wtcse wtpr1 26 intkr kric krif krmk krism krpr0 krcse krpr1 404 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.1 interrupt control registers an interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc., for the corresponding interrupt request. the interrupt control register format is shown in figure 23-1. (1) priority specification flags ( pr1, pr0) the priority specification flags specify the priority on an individual interrupt source basis for the 27 maskable interrupts. up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. among maskable interrupt sources, level 0 is the highest priority. if multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they are acknowledged in default priority order. these flags can be manipulated bit-wise by software. reset input sets all bits to 1. (2) context switching enable flag ( cse) the context switching enable flag specifies that a maskable interrupt request is to be serviced by context switching. in context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector address stored beforehand in the register bank, and at the same time the current contents of the program counter (pc) and program status word (psw) are saved in the register bank. context switching is suitable for real-time processing, since execution of interrupt servicing can be started faster than with normal vectored interrupt servicing. this flag can be manipulated bit-wise by software. reset input sets all bits to 0. (3) macro service enable flag ( ism) the macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by vectored interruption or context switching, or by macro service. when macro service processing is selected, at the end of the macro service (when the macro service counter reaches 0) the macro service enable flag is automatically cleared (0) by hardware (vectored interrupt service/ context switching service). this flag can be manipulated bit-wise by software. reset input sets all bits to 0. (4) interrupt mask flag ( mk) an interrupt mask flag specifies enabling/disabling of vectored interrupt servicing and macro service processing for the interrupt request corresponding to that flag. the interrupt mask flag contents are not changed by the start of interrupt service, etc., and are the same as the interrupt mask register contents (refer to 23.3.2 interrupt mask registers (mk0, mk1) ). macro service processing requests are also subject to mask control, and macro service requests can also be masked with this flag. this flag can be manipulated by software. reset input sets all bits to 1. (5) interrupt request flag ( if) an interrupt request flag is set (1) by generation of the interrupt request that corresponds to that flag. when the interrupt is acknowledged, the flag is automatically cleared (0) by hardware. this flag can be manipulated by software. reset input sets all bits to 0. 405 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-1. interrupt control register ( icn) (1/3) wdtic wdtif <7> <6> <5> <4> 3 2 <1> pif0 wdtmk wdtism wdcse 0 0 wdtpr1 <0> wdtpr0 pic0 pic1 pic2 pic3 pic4 pic5 pic6 csiic0 pmk0 pism0 pcse0 0 0 ppr01 ppr00 pif1 pmk1 pism1 pcse1 0 0 ppr11 ppr10 pif2 pmk2 pism2 pcse2 0 0 ppr21 ppr20 pif3 pmk3 pism3 pcse3 0 0 ppr31 ppr30 pif4 pmk4 pism4 pcse4 0 0 ppr41 ppr40 pif5 pmk5 pism5 pcse5 0 0 ppr51 ppr50 pif6 pmk6 pism6 pcse6 0 0 ppr61 ppr60 csiif0 ifn 0 1 mkn 0 1 ismn 0 1 csen 0 1 prn1 0 0 1 1 prn0 0 1 0 1 csimk0 csiism0 csicse0 0 0 csipr01 csipr00 priority 3 address: 0ffe0h to 0ffe8h r/w after reset: 43h symbol interrupt request generation no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) interrupt processing enable/disable interrupt processing enable interrupt processing disable interrupt processing mode specification vectored interrupt processing/context switching processing macro service processing context switching processing specification processing with vectored interrupt processing with context switching interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 406 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-1. interrupt control register ( icn) (2/3) seric1 serif1 <7> <6> <5> <4> 3 2 <1> srif1 sermk1 serism1 sercse1 0 0 serpr11 <0> serpr10 sric1 stic1 seric2 sric2 stic2 tmic3 tmic00 tmic01 srmk1 srism1 srcse1 0 0 srpr11 srpr10 stif1 stmk1 stism1 stcse1 0 0 stpr11 stpr10 serif2 sermk2 serism2 sercse2 0 0 serpr21 serpr20 srif2 srmk2 srism2 srcse2 0 0 srpr21 srpr20 stif2 stmk2 stism2 stcse2 0 0 stpr21 stpr20 tmif3 tmmk3 tmism3 tmcse3 0 0 tmpr31 tmpr30 tmif00 tmmk00 tmism00 tmcse00 0 0 tmpr001 tmpr000 tmif01 ifn 0 1 mkn 0 1 ismn 0 1 csen 0 1 prn1 0 0 1 1 prn0 0 1 0 1 tmmk01 tmism01 tmcse01 0 0 tmpr011 tmpr010 priority 3 address: 0ffe9h to 0fff1h r/w after reset: 43h symbol interrupt request generation no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) interrupt processing enable/disable interrupt processing enable interrupt processing disable interrupt processing mode specification vectored interrupt processing/context switching processing macro service processing context switching processing specification processing with vectored interrupt processing with context switching interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 407 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-1. interrupt control register ( icn) (3/3) tmic1 tmif1 <7> <6> <5> <4> 3 2 <1> tmif2 tmmk1 tmism1 tmcse1 0 0 tmpr11 <0> tmpr10 tmic2 adic tmic5 tmic6 tmic7 tmic8 wtic kric tmmk2 tmism2 tmcse2 0 0 tmpr21 tmpr20 adif admk adism adcse 0 0 adpr01 adpr00 tmif5 tmmk5 tmism5 tmcse5 0 0 tmpr51 tmpr50 tmif6 tmmk6 tmism6 tmcse6 0 0 tmpr61 tmpr60 tmif7 tmmk7 tmism7 tmcse7 0 0 tmpr71 tmpr70 tmif8 tmmk8 tmism8 tmcse8 0 0 tmpr81 tmpr80 wtif wtmk wtism wtcse 0 0 wtpr1 wtpr0 krif ifn 0 1 mkn 0 1 ismn 0 1 csen 0 1 prn1 0 0 1 1 prn0 0 1 0 1 krmk krism krcse 0 0 krpr1 krpr0 address: 0fff2h to 0fffah r/w after reset: 43h symbol priority 3 interrupt request generation no interrupt request (interrupt signal is not generated) interrupt request (interrupt signal is generated) interrupt processing enable/disable interrupt processing enable interrupt processing disable interrupt processing mode specification vectored interrupt processing/context switching processing macro service processing context switching processing specification processing with vectored interrupt processing with context switching interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 408 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.2 interrupt mask registers (mk0, mk1) the mk0 and mk1 are composed of interrupt mask flags. mk0 and mk1 are 16-bit registers which can be manipulated as a 16-bit unit. mk0 can be manipulated in 8 bit units using mk0l and mk0h, and similarly mk1 can be manipulated using mk1l and mk1h. in addition, each bit of the mk0 and mk1 can be manipulated individually with a bit manipulation instruction. each interrupt mask flag controls enabling/disabling of the corresponding interrupt request. when an interrupt mask flag is set (1), acknowledgement of the corresponding interrupt request is disabled. when an interrupt mask flag is cleared (0), the corresponding interrupt request can be acknowledged as a vectored interrupt or macro service request. each interrupt mask flag in the mk0 and mk1 is the same flag as the interrupt mask flag in the interrupt control register. the mk0 and mk1 are provided for en bloc control of interrupt masking. after reset input, the mk0 and mk1 are set to ffffh, and all maskable interrupts are disabled. 409 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-2. format of interrupt mask registers (mk0, mk1) 410 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.3 in-service priority register (ispr) the ispr shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being processed. when a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (1), and remains set until the service program ends. when a non-maskable interrupt is acknowledged, the bit corresponding to the priority of that non-maskable interrupt is set (1), and remains set until the service program ends. when an reti instruction or retcs instruction is executed, the bit, among those set (1) in the ispr, that corresponds to the highest-priority interrupt request is automatically cleared (0) by hardware. the contents of the ispr are not changed by execution of an retb or retcsb instruction. reset input clears the ispr register to 00h. figure 23-3. format of in-service priority register (ispr) caution the in-service priority register (ispr) is a read-only register. the microcontroller may malfunction if this register is written. ispr nmis 76 5 4321 wdts 0 0 ispr3 ispr2 ispr1 0 ispr0 nmis 0 1 address: 0ffa8h r after reset: 00h symbol nmi processing status nmi interrupt is not accepted. nmi interrupt is accepted. wdts 0 1 watchdog timer interrupt processing status watchdog timer interrupt is not accepted. watchdog timer interrupt is accepted. isprn 0 1 priority level (n = 0 to 3) interrupt of priority level n is not accepted. interrupt of priority level n is accepted. 411 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.4 interrupt mode control register (imc) the imc contains the prsl flag. the prsl flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. when the imc is manipulated, the interrupt disabled state (di state) should be set first to prevent misoperation. the imc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. reset input sets the imc register to 80h. figure 23-4. format of interrupt mode control register (imc) imc prsl 76 5 4321 0 0 0000 0 0 prsl 0 1 address: 0ffaah r/w after reset: 80h symbol nesting control of maskable interrupt (lowest level) interrupts with level 3 (lowest level) can be nested. nesting of interrupts with level 3 (lowest level) is disabled. 412 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.5 watchdog timer mode register (wdm) the wdt4 bit of the wdm specifies the priority of nmi pin input non-maskable interrupts and watchdog timer overflow non-maskable interrupts. the wdm can be written to only by a dedicated instruction. this dedicated instruction, mov wdm, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual 1 s complements. if the 3rd and 4th bytes of the operation code are not mutual 1 s complements, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec electronics assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (mov wdm, a; and wdm, #byte; and set1 wdm.7) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. the wdm can be read at any time by a data transfer instruction. reset input clears the wdm register to 00h. figure 23-5. format of watchdog timer mode register (wdm) caution the watchdog timer mode register (wdm) can be written only by using a dedicated instruction (mov wdm, #byte). wdm run 76 5 4321 0 0 wdt4 0 wdt2 wdt1 0 0 run address: 0ffc2h r/w after reset: 00h symbol specifies operation of watchdog timer (refer to figure 13-2 ). wdt4 0 1 priority of watchdog timer interrupt request watchdog timer interrupt request < nmi pin input interrupt request watchdog timer interrupt request > nmi pin input interrupt request wdt2 wdt1 specifies count clock of watchdog timer (refer to figure 13-2 ). 413 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.6 interrupt selection control register (snmi) the snmi selects whether to use interrupt request signals from the watchdog timer and inputs from the p02 pin as maskable interrupt signals or non-maskable interrupts. since the bit of this register can be set (1) only once after reset, the bit should be cleared (0) by reset. the snmi is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the snmi to 00h. figure 23-6. format of interrupt selection control register (snmi) snmi 0 76 5 4321 0 0 0 0 0 swdt 0 snmi swdt 0 1 snmi 0 1 use as mni. interrupt processing cannot be disabled with interrupt mask register. at this time, release of the standby mode with the p02 pin is accomplished with nmi. address: 0ffa9h r/w after reset: 00h symbol watchdog timer interrupt selection use as non-maskable interrupt. interrupt processing cannot be disabled with interrupt mask register. use as maskable interrupt. vectored interrupts and macro service can be used. interrupt processing can be disabled with interrupt mask register. p02 pin function selection use as intp2. vectored interrupts and macro service can be used. interrupt processing can be disabled with interrupt mask register. at this time, release of the standby mode with the p02 pin is accomplished with a maskable interrupt. 414 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.3.7 program status word (psw) the psw is a register that holds the current status regarding instruction execution results and interrupt requests. the ie flag that sets enabling/disabling of maskable interrupts is mapped in the lower 8 bits of the psw (pswl). pswl can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (ei/di). when a vectored interrupt is acknowledged or a brk instruction is executed, pswl is saved to the stack and the ie flag is cleared (0). pswl is also saved to the stack by the push psw instruction, and is restored from the stack by the reti, retb and pop psw instructions. when context switching or a brkcs instruction is executed, pswl is saved to a fixed area in the register bank, and the ie flag is cleared (0). pswl is restored from the fixed area in the register bank by an retcsi or retcsb instruction. reset input sets pswl to 00h. figure 23-7. format of program status word (pswl) pswl s 76 5 4321 z rss ac ie p/v 0 0 cy s z rss ac after reset: 00h symbol used for normal instruction execution ie 0 1 enable or disable accepting interrupt disable enable p/v cy used for normal instruction execution 415 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.4 software interrupt acknowledgement operations a software interrupt is acknowledged in response to execution of a brk or brkcs instruction. software interrupts cannot be disabled. 23.4.1 brk instruction software interrupt acknowledgement operation when a brk instruction is executed, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (0), the vector table (003eh/003fh) contents are loaded into the lower 16 bits of the pc, and 0000b into the higher 4 bits, and a branch is performed (the start of the service program must be in the base area). the retb instruction must be used to return from a brk instruction software interrupt. caution the reti instruction must not be used to return from a brk instruction software interrupt. use the retb instruction. 23.4.2 brkcs instruction software interrupt (software context switching) acknowledgement operation the context switching function can be initiated by executing a brkcs instruction. the register bank to be used after context switching is specified by the brkcs instruction operand. when a brkcs instruction is executed, the program branches to the start address of the interrupt service program (which must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word (psw) and program counter (pc) are saved in the register bank. figure 23-8. context switching operation by execution of brkcs instruction the retcsb instruction is used to return from a software interrupt due to a brkcs instruction. the retcsb instruction must specify the start address of the interrupt service program for the next time context switching is performed by a brkcs instruction. this interrupt service program start address must be in the base area. caution the retcs instruction must not be used to return from a brkcs instruction software interrupt. use the retcsb instruction. register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 3 register bank switching (rbs0 to rbs2 n) 4 rss 0 ( ie 0 ) 1 save 2 save (bits 8 to 11 of temporary register) 6 exchange 5 save pc 15-0 pc 19-16 0000b temporary register psw 416 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-9. return from brkcs instruction software interrupt (retcsb instruction operation) pc 19-16 pc 15-0 1 restoration 3 transfer 4 restoration (to original register bank) 2 restoration psw vvp uup te wl retcsb instruction operand register bank n (n = 0 to 7) a r5 r7 d h b x r4 r6 c 23.5 operand error interrupt acknowledge an operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of an mov stbc, #byte instruction, location instruction, or an mov wdm, #byte instruction does not match the 4th byte of the operand. operand error interrupts cannot be disabled. when an operand error interrupt is generated, the program status word (psw) and the start address of the instruction that caused the error are saved to the stack, the ie flag is cleared (0), the vector table value is loaded into the program counter (pc), and a branch is performed (within the base area only). as the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an retb instruction at the end of the operand error interrupt service program will result in generation of another operand error interrupt. you should therefore either process the address in the stack or initialize the program by referring to 23.12 restoring interrupt function to initial state . 417 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.6 non-maskable interrupt acknowledge non-maskable interrupts are acknowledged even in the interrupt disabled state. non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non-maskable interrupt of higher priority. the relative priorities of non-maskable interrupts are set by the wdt4 bit of the watchdog timer mode register (wdm) (see 23.3.5 watchdog timer mode register (wdm) ). except in the cases described in 23.9 when interrupt requests and macro service are temporarily held pending , a non-maskable interrupt request is acknowledged immediately. when a non-maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (0), the in-service priority register (ispr) bit corresponding to the acknowledged non-maskable interrupt is set (1), the vector table contents are loaded into the pc, and a branch is performed. the ispr bit that is set (1) is the nmis bit in the case of a non-maskable interrupt due to edge input to the nmi pin, and the wdts bit in the case of watchdog timer overflow. when the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable interrupt currently being executed are held pending. a pending non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service program currently being executed (after execution of the reti instruction). however, even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service program. 418 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-10. non-maskable interrupt request acknowledgement operations (1/2) (a) when a new nmi request is generated during nmi service program execution main routine nmi request nmi request (nmis = 1) nmi request held pending since nmis = 1 pending nmi request is serviced (b) when a watchdog timer interrupt request is generated during nmi service program execution (when the watchdog timer interrupt priority is higher (when wdt4 in the wdm = 1)) main routine nmi request watchdog timer interrupt request 419 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-10. non-maskable interrupt request acknowledgement operations (2/2) (c) when a watchdog timer interrupt request is generated during nmi service program execution (when the nmi interrupt priority is higher (when wdt4 in the wdm = 0)) (d) when an nmi request is generated twice during nmi service program execution main routine nmi request nmi request held pending since nmi service program is being executed nmi request held pending since nmi service program is being executed nmi request was generated more than twice, but is only acknowledged once main routine nmi request watchdog timer interrupt request watchdog timer interrupt held pending since wdt4 = 0 pending watchdog timer interrupt is serviced 420 chapter 23 interrupt functions user s manual u13570ej3v0ud cautions 1. macro service requests are acknowledged and serviced even during execution of a non- maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. 2. the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgement will not be performed normally if a different instruction is used. if you restart a program from the initial state after a non-maskable interrupt acknowledgement, refer to 23.12 restoring interrupt function to initial state. 3. non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 23.9. therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (see table 3-6 in 3.9 special function registers (sfrs)), and the cpu becomes deadlocked, or an unexpected signal is output from a pin, or the pc and psw are written to an address in which ram is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a runaway occurs. therefore, the program following reset release must be as shown below. cseg at 0 dw strt cseg base strt: location 0fh; or location 0 movg sp, #imm24 421 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.7 maskable interrupt acknowledge a maskable interrupt can be acknowledged when the interrupt request flag is set (1) and the mask flag for that interrupt is cleared (0). when servicing is performed by macro service, the interrupt is acknowledged and serviced by macro service immediately. in the case of vectored interruption and context switching, an interrupt is acknowledged in the interrupt enabled state (when the ie flag is set (1)) if the priority of that interrupt is one for which acknowledgement is permitted. if maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by the priority specification flag is acknowledged. if the interrupts have the same priority specified, they are acknowledged in accordance with their default priorities. a pending interrupt is acknowledged when a state in which it can be acknowledged is established. the interrupt acknowledgement algorithm is shown in figure 23-11. 422 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-11. interrupt acknowledgement processing algorithm no if = 1 mk = 0 ism = 1 cse = 1 ie = 1 higher priority than interrupt currently being serviced? higher priority than other existing interrupt requests? highest default priority among interrupt requests of same priority? vectored interrupt generation interrupt request? yes no interrupt mask released? yes no yes yes yes yes no no interrupt enabled state? macro service? no no no interrupt request held pending yes context switching? context switching generation yes highest default priority among macro service requests? macro service processing execution interrupt request held pending no yes 423 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.7.1 vectored interrupt when a vectored interrupt maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (0) (the interrupt disabled state is set), and the in-service priority register (ispr) bit corresponding to the priority of the acknowledged interrupt is set (1). also, data in the vector table predetermined for each interrupt request is loaded into the pc, and a branch is performed. the return from a vectored interrupt is performed by means of the reti instruction. caution when a maskable interrupt is acknowledged by vectored interrupt, the reti instruction must be used to return from the interrupt. subsequent interrupt acknowledgement will not be performed normally if a different instruction is used. 23.7.2 context switching initiation of the context switching function is enabled by setting (1) the context switching enable flag of the interrupt control register. when an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified by 3 bits of the lower address (even address) of the corresponding vector table address is selected. the vector address stored beforehand in the selected register bank is transferred to the program counter (pc), and at the same time the contents of the pc and program status word (psw) up to that time are saved in the register bank and branching is performed to the interrupt service program. figure 23-12. context switching operation by generation of interrupt request register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 6 exchange 4 2 save (temporary register bits 8 to 11) 5 save 1 save pc 15-0 pc 19-16 0000b temporary register psw n 3 register bank switching (rbs0 to rbs2 n) vector table rss 0 ( ie 0 ) 424 chapter 23 interrupt functions user s manual u13570ej3v0ud the retcs instruction is used to return from an interrupt that uses the context switching function. the retcs instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next. this interrupt service program start address must be in the base area. caution the retcs instruction must be used to return from an interrupt serviced by context switching. subsequent interrupt acknowledgement will not be performed normally if a different instruction is used. figure 23-13. return from interrupt that uses context switching by means of retcs instruction pc 19-16 pc 15-0 2 restoration 4 restoration (to original register bank) psw retcs instruction operand 3 transfer register bank n (n = 0 to 7) vvp uup tde wh l ax r5 r4 r7 r6 bc 1 restoration 425 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.7.3 maskable interrupt priority levels the pd784218a performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt. multiple interrupts can be controlled by priority levels. there are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag. in priority control by means of default priority, interrupt service is performed in accordance with the priority preassigned to each interrupt request (default priority) (refer to table 23- 2 ). in programmable priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. interrupt requests for which multiple interruption is permitted are shown in table 23-5. since the ie flag is cleared (0) automatically when an interrupt is acknowledged, when multiple interruption is used, the ie flag should be set (1) to enable interrupts by executing an ie instruction in the interrupt service program, etc. table 23-5. multiple interrupt servicing priority of interrupt currently ispr value ie flag in psw prsl flag in acknowledgeable maskable interrupts being acknowledged imc no interrupt being 00000000 0 all macro service only acknowledged 1 all maskable interrupts 3 00001000 0 all macro service only 10 all maskable interrupts 11 all macro service maskable interrupts specified as priority 0/1/2 2 0000 100 0 all macro service only 1 all macro service maskable interrupts specified as priority 0/1 1 0000 10 0 all macro service only 1 all macro service maskable interrupts specified as priority 0 0 0000 1 all macro service only non-maskable interrupts 1000 all macro service only 0100 1100 426 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-14. examples of servicing when another interrupt request is generated during interrupt service (1/3) main routine ei ei ei interrupt request a (level 3) interrupt request b (level 2) interrupt request d (level 2) interrupt request e (level 2) interrupt request f (level 3) interrupt request g (level 1) a servicing b servicing c servicing d servicing e servicing f servicing g servicing h servicing since interrupt request b has a higher priority than interrupt request a, and interrupts are enabled, interrupt request b is acknowledged. the priority of interrupt request d is higher than that of interrupt request c, but since interrupts are disabled, interrupt request d is held pending. although interrupts are enabled, interrupt request f is held pending since it has a lower priority than interrupt request e. although interrupts are enabled, interrupt request h is held pending since it has the same priority as interrupt request g. interrupt request h (level 1) ei interrupt request c (level 3) 427 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-14. examples of servicing when another interrupt request is generated during interrupt service (2/3) main routine ei ei interrupt request i (level 1) interrupt request k (level 2) interrupt request n (level 2) macro service request j (level 2) i servicing j macro service k servicing l servicing m servicing n servicing o servicing p servicing the macro service request is serviced irrespective of interrupt enabling/disabling and priority. the interrupt request l is held pending since it has a lower priority than interrupt request k. interrupt request m generated after interrupt request l has a higher priority, and is therefore acknowledged first. since servicing of interrupt request n performed in the interrupt disabled state, interrupt requests o and p are held pending. after interrupt request n servicing, the pending interrupt requests are acknowledged. although interrupt request o was generated first, interrupt request p has a higher priority and is therefore acknowledged first. interrupt request l (level 3) interrupt request m (level 1) interrupt request o (level 3) interrupt request p (level 1) 428 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-14. examples of servicing when another interrupt request is generated during interrupt service (3/3) notes 1. low default priority 2. high default priority remarks 1. a to z in the figure above are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. main routine ei ei ei ei ei ei interrupt request q (level 3) interrupt request s (level 1) interrupt request u (level 0) interrupt request v (level 0) w macro service q servicing r servicing s servicing t servicing u servicing v servicing x servicing y servicing z servicing interrupt request x (level 1) interrupt request r (level 2) interrupt request t (level 0) interrupt request y note 1 (level 2) interrupt request w (level 3) multiple acknowledgement of levels 3 to 0. if the prsl bit of the imc register is set (1), only macro service requests and non- maskable interrupts generate nesting beyond this. if the prsl bit of the imc register is cleared (0), level 3 interrupts can also be nested during level 3 interrupt servicing (see figure 23-16 ). even though the interrupt enabled state is set during servicing of level 0 interrupt request u, the interrupt request is not acknowledged but held pending even though its priority is 0. however, the macro service request is acknowledged and serviced irrespective of its level and even though there is a pending interrupt with a higher priority level. pending interrupt requests y and z are acknowledged after servicing of interrupt request x. as interrupt requests y and z have the same priority level, interrupt request z which has the higher default priority is acknowledged first, irrespective of the order in which the interrupt requests were generated. interrupt request z note 2 (level 2) 429 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-15. examples of servicing of simultaneously generated interrupts remark a to f in the figure above are arbitrary names used to differentiate between the interrupt requests and macro service requests. main routine ei interrupt request a (level 2) macro service request b (level 3) macro service request c (level 1) interrupt request d (level 1) interrupt request e (level 1) macro service request f (level 1) default priority order a > b > c > d > e > f macro service request b servicing macro service request c servicing macro service request f servicing interrupt request d servicing interrupt request e servicing interrupt request a servicing when requests are generated simultaneously, they are acknowledged in order starting with macro service. macro service requests are acknowledged in default priority order (b/c/f) (not dependent upon the programmable priority order). as interrupt requests are acknowledged in high-to-low priority level order, d and e are acknowledged first. as d and e have the same priority level, the interrupt request with the higher default priority, d, is acknowledged first. 430 chapter 23 interrupt functions user s manual u13570ej3v0ud main routine ei ei interrupt request a (level 3) interrupt request b (level 3) a servicing b servicing interrupt request c (level 3) interrupt request d (level 3) c servicing d servicing interrupt request e note 1 (level 3) interrupt request f note 2 (level 3) f servicing e servicing imc 80h ei main routine imc 00h ei main routine ei ei the prsl bit of the imc is set to 1, and nesting between level 3 interrupts is disabled. even though interrupts are enabled, interrupt request b is held pending since it has the same priority as interrupt request a. the prsl bit of the imc is set to 0, so that a level 3 interrupt is acknowledged even during level 3 interrupt servicing (nesting is possible). since level 3 interrupt request c is being serviced in the interrupt enabled state and prsl = 0, interrupt request d, which is also level 3, is acknowledged. as interrupt request e and f are both of the same level, the one with the higher default priority, f, is acknowledged first. when the interrupt enabled state is set during servicing of interrupt request f, pending interrupt request e is acknowledged since prsl = 0. imc 00h figure 23-16. differences in level 3 interrupt acknowledgement according to imc register setting notes 1. low default priority 2. high default priority remarks 1. a to f in the figure above are arbitrary names used to differentiate the interrupt requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. 431 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8 macro service function 23.8.1 outline of macro service function macro service is one method of servicing interrupts. with a normal interrupt, the program counter (pc) and program status word (psw) are saved, and the start address of the interrupt service program is loaded into the pc, but with macro service, different processing (mainly data transfers) is performed instead of this processing. this enables interrupt requests to be responded to quickly, and moreover, since transfer processing is faster than processing by a program, the processing time can also be reduced. also, since a vectored interrupt is generated after processing has been performed the specified number of times, another advantage is that vectored interrupt programs can be simplified. figure 23-17. differences between vectored interrupt and macro service processing macro service context switching note 1 vectored interrupt note 1 vectored interrupt interrupt request generation main routine main routine main routine main routine macro service processing main routine note 2 note 4 note 4 note 3 interrupt servicing main routine sel rbn interrupt servicing restore pc, psw save general registers initialize general registers interrupt servicing restore general registers main routine restore pc & psw main routine notes 1. when register bank switching is used, and an initial value has been set in the register beforehand 2. register bank switching by context switching, saving of pc and psw 3. register bank, pc and psw restoration by context switching 4. pc and psw saved to the stack, vector address loaded into pc 23.8.2 types of macro service macro service can be used with the 27 kinds of interrupts shown in table 23-6. there are four kinds of operation, which can be used to suit the application. 432 chapter 23 interrupt functions user s manual u13570ej3v0ud table 23-6. interrupts for which macro service can be used default interrupt request generation source generating unit macro service control priority word address 0 intwdtm (watchdog timer overflow) watchdog timer 0fe06h 1 intp0 (pin input edge detection) edge detection 0fe08h 2 intp1 (pin input edge detection) 0fe0ah 3 intp2 (pin input edge detection) 0fe0ch 4 intp3 (pin input edge detection) 0fe0eh 5 intp4 (pin input edge detection) 0fe10h 6 intp5 (pin input edge detection) 0fe12h 7 intp6 (pin input edge detection) 0fe14h 8 intiic0 (csi0 i 2 c bus transfer end) note clocked serial 0fe16h intcsi0 (csi0 3-wire transfer end) interface 9 intser1 (asi1 uart reception error) asynchronous 0fe18h 10 intsr1 (asi1 uart reception end) serial interface/ 0fe1ah intcsi1 (csi1 3-wire transfer end) clocked serial 11 intst1 (asi1 uart transmission end) interface 1 0fe1ch 12 intser2 (asi2 uart reception error) asynchronous 0fe1eh 13 intsr2 (asi2 uart reception end) serial interface/ 0fe20h intcsi2 (csi2 3-wire transfer end) clocked serial 14 intst2 (asi2 uart transmission end) interface 2 0fe22h 15 inttm3 (reference time interval signal from watch timer) watch timer 0fe24h 16 inttm00 (match signal generation of 16-bit timer register timer/counter 0fe26h and capture/compare register (cr00)) 17 inttm01 (match signal generation of 16-bit timer register 0fe28h and capture/compare register (cr01)) 18 inttm1 (match signal generation of 8-bit timer/counter 1) timer/counter 1 0fe2ah 19 inttm2 (match signal generation of 8-bit timer/counter 2) timer/counter 2 0fe2ch 20 intad (a/d converter conversion end) a/d converter 0fe2eh 21 inttm5 (match signal generation of 8-bit timer/counter 5) timer/counter 5 0fe30h 22 inttm6 (match signal generation of 8-bit timer/counter 6) timer/counter 6 0fe32h 23 inttm7 (match signal generation of 8-bit timer/counter 7) timer/counter 7 0fe34h 24 inttm8 (match signal generation of 8-bit timer/counter 8) timer/counter 8 0fe36h 25 intwt (watch timer overflow) watch timer 0fe38h 26 intkr (falling edge detection of port 8) edge detection 0fe3ah note pd784216ay, 784218ay subseries only remarks 1. the default priority is a fixed number. this indicates the order of priority when macro service requests are generated simultaneously, 2. asi: asynchronous serial interface csi: clocked serial interface 433 chapter 23 interrupt functions user s manual u13570ej3v0ud there are four kinds of macro service, as shown below. (1) type a one byte or one word of data is transferred between a special function register (sfr) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. memory that can be used in the transfers is limited to internal ram addresses 0fe00h to 0feffh when the location 0h instruction is executed, and addresses 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the specification method is simple and is suitable for low-volume, high-speed data transfers. (2) type b as with type a, one byte or one word of data is transferred between a special function register (sfr) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. the sfr and memory to be used in the transfers is specified by the macro service channel (the entire 1 mb memory space can be used). this is a general version of type a, suitable for large volumes of transfer data. (3) type c data is transferred from memory to two special function registers (sfr) each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. with type c macro service, not only are data transfers performed to two locations in response to a single interrupt request, but it is also possible to add output data ring control and a function that automatically adds data to a compare register. the entire 1 mb memory space can be used. type c is mainly used with the inttm1 and inttm2 interrupts, and is used for stepping motor control, etc., by macro service, with rtbl or rtbh and cr10, cr1w used as the sfrs to which data is transferred. (4) counter mode this mode is to decrement the macro service counter (msc) when an interrupt occurs and is used to count the division operation of an interrupt and interrupt generator. when msc is 0, a vectored interrupt can be generated. to restart the macro service, msc must be set again. msc is fixed to 16 bits and cannot be used as an 8-bit counter. 434 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.3 basic macro service operation interrupt requests for which the macro service processing generated by the algorithm shown in figure 23-11 can be specified are basically serviced in the sequence shown in figure 23-18. interrupt requests for which macro service processing can be specified are not affected by the status of the ie flag, but are disabled by setting (1) an interrupt mask flag in the interrupt mask register (mk0). macro service processing can be executed in the interrupt disabled state and during execution of an interrupt service program. figure 23-18. macro service processing sequence the macro service type and transfer direction are determined by the value set in the macro service control word mode register. transfer processing is then performed using the macro service channel specified by the channel pointer according to the macro service type. the macro service channel is memory which contains the macro service counter which records the number of transfers, the transfer destination and transfer source pointers, and data buffers, and can be located at any address in the range fe00h to feffh when the location 0h instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed. no msc = 0? vcie = 1? msc msc ? 1 interrupt service mode bit 0 interrupt request flag 0 yes no yes macro service processing execution ; data transfer, real-time output port control ; decrement macro service counter (msc) interrupt request generation execute next instruction generation of interrupt request for which macro service processing can be specified 435 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.4 operation at end of macro service in macro service, processing is performed the number of times specified during execution of another program. macro service ends when the processing has been performed the specified number of times (when the macro service counter (msc) reaches 0). either of two operations may be performed at this point, as specified by the vcie bit (bit 7) of the macro service mode register for each macro service. (1) when vcie bit is 0 in this mode, an interrupt is generated as soon as the macro service ends. figure 23-18 shows an example of macro service and interrupt acknowledgement operations when the vcie bit is 0. this mode is used when a series of operations end with the last macro service processing performed, for instance. it is mainly used in the following cases: asynchronous serial interface receive data buffering (intsr1, intsr2) a/d conversion result fetch (intad) compare register update as the result of a match between a timer register and the compare register (inttm00, inttm01, inttm1, inttm2, inttm5 to inttm8) 436 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-19. operation at end of macro service when vcie = 0 main routine ei main routine ei macro service request last macro service request macro service processing macro service processing servicing of interrupt request due to end of macro service other interrupt request last macro service request servicing of other interrupt macro service processing servicing of interrupt request due to end of macro service at the end of macro service (msc = 0), an interrupt request is generated and acknowledged. if the last macro service is performed when the interrupt due to the end of macro service cannot be acknowledged while other interrupt servicing is being executed, etc., that interrupt is held pending until it can be acknowledged. 437 chapter 23 interrupt functions user s manual u13570ej3v0ud (2) when vcie bit is 1 in this mode, an interrupt is not generated after macro service ends. figure 23-20 shows an example of macro service and interrupt acknowledgement operations when the vcie bit is 1. this mode is used when the final operation is to be started by the last macro service processing performed, for instance. it is mainly used in the following cases: clocked serial interface data transfers (intcsi0, intcsi1, intcsi2) asynchronous serial interface data transmission (intst1, intst2) to stop a stepping motor in the case of stepping motor control by means of macro service type c using the real-time output port and timer/counter (inttm1, inttm2) figure 23-20. operation at end of macro service when vcie = 1 main routine ei macro service request last macro service request interrupt request due to the end of the hardware operation started by the last macro service processing macro service processing processing of last macro service interrupt servicing 438 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.5 macro service control registers (1) macro service control word the pd784218a s macro service function is controlled by the macro service mode register and macro service channel pointer. the macro service processing mode is set by means of the macro service mode register, and the macro service channel address is indicated by the macro service channel pointer. the macro service mode register and macro service channel pointer are mapped onto the part of the internal ram shown in figure 23-21 for each macro service as the macro service control word. when macro service processing is performed, the macro service mode register and channel pointer values corresponding to the interrupt requests for which macro service processing can be specified must be set beforehand. 439 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-21. macro service control word format note pd784216ay, 784218ay subseries only channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register intkr address 0fe3bh 0fe3ah 0fe39h 0fe38h 0fe37h 0fe36h 0fe35h 0fe34h 0fe33h 0fe32h source intwt inttm8 inttm7 inttm6 inttm5 intad inttm2 inttm1 inttm01 inttm00 inttm3 intst2 intsr2/intcsi2 intser2 intst1 intsr1/intcsi1 intser1 intiic0 note /intcsi0 intp6 intp5 intp4 intp3 intp2 intp1 intp0 intwdtm 0fe31h 0fe30h 0fe2fh 0fe2eh 0fe2dh 0fe2ch 0fe2bh 0fe2ah 0fe29h 0fe28h 0fe27h 0fe26h 0fe25h 0fe24h 0fe23h 0fe22h 0fe21h 0fe20h 0fe1fh 0fe1eh 0fe1dh 0fe1ch 0fe1bh 0fe1ah 0fe19h 0fe18h 0fe17h 0fe16h 0fe15h 0fe14h 0fe13h 0fe12h 0fe11h 0fe10h 0fe0fh 0fe0eh 0fe0dh 0fe0ch 0fe0bh 0fe0ah 0fe09h 0fe08h 0fe07h 0fe06h reserved word krchp krmmd wtchp wtmmd cchp8 cmmd8 cchp7 cmmd7 cchp6 cmmd6 cchp5 cmmd5 adchp admmd cchp2 cmmd2 cchp1 cmmd1 cchp01 cmmd01 cchp00 cmmd00 cchp3 cmmd3 stchp2 stmmd2 csichp2/srchp2 csimmd2/srmmd2 serchp2 sermmd2 stchp1 stmmd1 csichp1/srchp1 csimmd1/srmmd1 serchp1 sermmd1 csichp0/iicchp csimmd0/iicmmd pchp6 pmmd6 pchp5 pmmd5 pchp4 pmmd4 pchp3 pmmd3 pchp2 pmmd2 pchp1 pmmd1 pchp0 pmmd0 wdtchp wdtmmd 440 chapter 23 interrupt functions user s manual u13570ej3v0ud (2) macro service mode register the macro service mode register is an 8-bit register that specifies the macro service operation. this register is written in internal ram as part of the macro service control word (refer to figure 23-21 ). the format of the macro service mode register is shown in figure 23-22. figure 23-22. macro service mode register format (1/2) 7 vcie 6 mod2 5 mod1 4 mod0 3 cht3 2 cht2 1 cht1 0 cht0 cht0 0 1 0 cht1 0 0 0 cht2 0 0 0 cht3 1 0 0 mod2 mod1 mod0 000 001 010 011 100 101 110 111 vcie 0 1 type a counter mode counter decrement data transfer direction memory sfr data size: 1 byte data transfer direction sfr memory data transfer direction memory sfr data size: 1 byte data transfer direction sfr memory data transfer direction memory sfr data size: 2 bytes data transfer direction sfr memory data transfer direction memory sfr data size: 2 bytes data transfer direction sfr memory not generated (next interrupt processing is vectored interrupt) generated interrupt request when msc = 0 type b 441 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-22. macro service mode register format (2/2) 7 vcie 6 mod2 5 mod1 4 mod0 3 cht3 2 cht2 1 cht1 0 cht0 cht0 1 1 0 cht1 1 0 0 cht2 1 1 1 cht3 1 1 1 0 1 1 1 mod2 mod1 mod0 000 001 010 011 100 101 110 111 type c decrements mpd increments mpd retains mpt decrements mpt retains mpt increments mpt data size for timer specified by mpt: 1 byte no automatic addition no ring control ring control automatic addition no ring control ring control no ring control ring control no ring control ring control data size for timer specified by mpt: 2 bytes no automatic addition automatic addition vcie 0 1 generated not generated (next interrupt processing is vectored interrupt) interrupt request when msc = 0 (3) macro service channel pointer the macro service channel pointer specifies the macro service channel address. the macro service channel can be located in the 256-byte space from fe00h to feffh when the location 0h instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed, and the higher 16 bits of the address are fixed. therefore, the lower 8 bits of the data stored to the highest address of the macro service channel are set in the macro service channel pointer. 442 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.6 macro service type a (1) operation data transfers are performed between buffer memory in the macro service channel and an sfr specified in the macro service channel. with type a, the data transfer direction can be selected as memory-to-sfr or sfr-to-memory. data transfers are performed the number of times set beforehand in the macro service counter. one macro service processing transfers 8-bit or 16-bit data. type a macro service is useful when the amount of data to be transferred is small, as transfers can be performed at high speed. 443 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-23. macro service data transfer processing flow (type a) read contents of macro service mode register determine channel type read channel pointer contents (m) other to other macro service processing read msc contents (n) calculate buffer address* read sfr pointer contents determine transfer direction sfr memory memory sfr read buffer contents, then transfer read data to specified sfr read specified sfr contents, then transfer read data to buffer msc msc ? 1 msc = 0? no yes clear (0) interrupt service mode bit (ism) vcie = 1? (vectored interrupt request generation) type a yes no 1-byte transfer: m ? n ? 1 2-byte transfer: m ? n 2 ? 1 * macro service request acknowledgement clear (0) interrupt request flag (if) end end 444 chapter 23 interrupt functions user s manual u13570ej3v0ud (2) macro service channel configuration the channel pointer and 8-bit macro service counter (msc) indicate the buffer address in internal ram (fe00h to feffh when the location 0h instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed) which is the transfer source or transfer destination (refer to figure 23-24 ). in the channel pointer, the lower 8 bits of the address are written to the macro service counter in the macro service channel. the sfr involved with the access is specified by the sfr pointer (sfrp). the lower 8 bits of the sfr address are written to the sfrp. 445 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-24. type a macro service channel (a) 1-byte transfers (b) 2-byte transfers 70 macro service counter (msc) sfr pointer (sfrp) macro service buffer 1 macro service buffer 2 macro service buffer n channel pointer mode register macro service control word macro service channel high addresses low addresses macro service buffer address = (channel pointer) ? (macro service counter) ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msc = 1 msc = 2 msc = n 70 macro service counter (msc) sfr pointer (sfrp) macro service buffer 1 macro service buffer 2 macro service buffer n channel pointer mode register macro service control word macro service channel high addresses low addresses macro service buffer address = (channel pointer) ? (macro service counter) 2 ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msc = 1 msc = 2 msc = n (higher byte) (lower byte) (higher byte) (lower byte) (higher byte) (lower byte) 446 chapter 23 interrupt functions user s manual u13570ej3v0ud (3) example of use of type a an example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in ram. figure 23-25. asynchronous serial reception remark addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. (internal ram) 0fe7fh channel pointer 7fh mode register 11h note lower 8 bits of rxb1 address type a, sfr memory, 8-bit transfer, interrupt request generation when msc = 0 1 internal bus msc 0eh sfrp 74h note 0fe70h r x d1/p20 intsr1 macro service request receive buffer (rxb1) shift register 447 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.7 macro service type b (1) operation data transfers are performed between a data area in memory and an sfr specified by the macro service channel. with type b, the data transfer direction can be selected as memory-to-sfr or sfr-to-memory. data transfers are performed the number of times set beforehand in the macro service counter. one macro service processing transfers 8-bit or 16-bit data. this type of macro service is macro service type a for general purposes and is ideal for processing a large amount of data because up to 64 kb when 8-bit data is transferred or up to 128 kb when 16-bit data is transferred can be set in any 1 mb address space as data buffer area. 448 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-26. macro service data transfer processing flow (type b) read contents of macro service mode register determine channel type other to other macro service processing 1-byte transfer: +1 2-byte transfer: +2 determine transfer direction memory sfr sfr memory msc msc 1 msc = 0? no yes clear (0) interrupt service mode bit (ism) vcie = 1? (vectored interrupt request generation) type b yes no increment mp note read data from sfr, and write to memory addressed by mp read data from memory, and write to sfr specified by sfr pointer select transfer source memory with macro service pointer (ms) note select transfer source sfr with sfr pointer end end macro service request acknowledgement read channel pointer contents (m) clear (0) interrupt request flag (if) 449 chapter 23 interrupt functions user s manual u13570ej3v0ud (2) macro service channel configuration the macro service pointer (mp) indicates the data buffer area in the 1 mb memory space that is the transfer destination or transfer source. the lower 8 bits of the sfr that is the transfer destination or transfer source is written to the sfr pointer (sfrp). the macro service counter (msc) is a 16-bit counter that specifies the number of data transfers. the macro service channel that stores the mp, sfrp and msc is located in internal ram space addresses 0fe00h to 0feffh when the location 0h instruction is executed, or 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the macro service channel is indicated by the channel pointer as shown in figure 23-27. in the channel pointer, the lower 8 bits of the address are written to the macro service counter in the macro service channel. figure 23-27. type b macro service channel macro service counter (msc) sfr pointer (sfrp) (bits 8 to 15) (bits 0 to 7) (bits 16 to 23) note (bits 8 to 15) (bits 0 to 7) channel pointer mode register macro service pointer (mp) macro service control word low addresses macro service channel high addresses sfr buffer area macro service buffer address = macro service pointer note bits 20 to 23 must be set to 0. 450 chapter 23 interrupt functions user s manual u13570ej3v0ud (3) example of use of type b an example is shown below in which parallel data is input from port 3 in synchronization with an external signal. the intp4 external interrupt pin is used for synchronization with the external signal. figure 23-28. parallel data input synchronized with external interrupts remark macro service channel addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 64kb memory space macro service control word, macro service channel (internal ram) 0fe6eh buffer area * lower 8 bits of port 3 address 1 + 1 internal bus port 3 p37 p36 p35 p34 p33 p32 p31 p30 intp4 edge detection macro service request intp4 msc 00h 20h 03h * mp 00h a0h 00h sfrp type b, sfr 8-bit transfer, interrupt request generation when msc = 0 channel pointer 6eh mode register 18h 0a01fh 0a000h 451 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-29. parallel data input timing intp4 port 3 data fetch (macro service) 452 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.8 macro service type c (1) operation in type c macro service, data in the memory specified by the macro service channel is transferred to two sfrs, for timer use and data use, specified by the macro service channel in response to a single interrupt request (the sfrs can be freely selected). an 8-bit or 16-bit timer sfr can be selected. in addition to the basic data transfers described above, type c macro service, the following functions can be added to type c macro service to reduce the size of the buffer area and alleviate the burden on software. these specifications are made by using the mode register of the macro service control word. (a) updating of timer macro service pointer it is possible to choose whether the timer macro service pointer (mpt) is to be kept as it is or incremented/ decremented. the mpt is incremented or decremented in the same direction as the data macro service pointer (mpd). (b) updating of data macro service pointer it is possible to choose whether the data macro service pointer (mpd) is to be incremented or decremented. (c) automatic addition the current compare register value is added to the data addressed by the timer macro service pointer (mpt), and the result is transferred to the compare register. if automatic addition is not specified, the data addressed by the mpt is simply transferred to the compare register. (d) ring control an output data pattern of the length specified beforehand is automatically output repeatedly. 453 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-30. macro service data transfer processing flow (type c) (1/2) read contents of macro service mode register determine channel type read channel pointer contents (m) other to other macro service processing note transfer data to compare register automatic addition specified? no increment mpt? no increment mpd? type c yes read memory addressed by mpt retain mpt? no increment mpd (+1) no yes yes yes increment mpt note 1 1-byte transfer: +1 2-byte transfer: +2 add data to compare register decrement mpd ( 1) decrement mpt transfer data to buffer register read memory addressed by mpd macro service request acknowledgement 454 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-30. macro service data transfer processing flow (type c) (2/2) no no yes no no yes yes yes no yes 1 end ring control? ring counter = 0? increment mpd? msc = 0? vcie = 1? subtract modulo register contents from data macro service pointer (mpd), and return pointer to start address add modulo register contents to data macro service pointer (mpd), and return pointer to start address msc msc 1 clear (0) interrupt service mode bit (ism) clear (0) interrupt request flag (if) load modulo register contents into ring counter end decrement ring counter (vectored interrupt request generation) 455 chapter 23 interrupt functions user s manual u13570ej3v0ud (2) macro service channel configuration there are two kinds of type c macro service channel, as shown in figure 23-31. the timer macro service pointer (mpt) mainly indicates the data buffer area in the 1 mb memory space to be transferred or added to the timer/counter compare register. the data macro service pointer (mpd) indicates the data buffer area in the 1 mb memory space to be transferred to the real-time output port. the modulo register (mr) specifies the number of repeat patterns when ring control is used. the ring counter (rc) holds the step in the pattern when ring control is used. when initialization is performed, the same value as in the mr is normally set in this counter. the macro service counter (msc) is a 16-bit counter that specifies the number of data transfers. the low-order 8 bits of the sfr that is the transfer destination is written to the timer sfr pointer (tsfrp) and data sfr pointer (dsfrp). the macro service channel that stores these pointers and counters is located in internal ram space addresses 0fe00h to 0feffh when the location 0h instruction is executed, or 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the macro service channel is indicated by the channel pointer as shown in figure 23-31. in the channel pointer, the lower 8 bits of the address are written to the macro service counter in the macro service channel. 456 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-31. type c macro service channel (1/2) (a) no ring control note bits 20 to 23 must be set to 0. macro service counter (msc) timer sfr pointer (tsfrp) (bits 8 to 15) (bits 0 to 7) (bits 8 to 15) (bits 8 to 15) (bits 0 to 7) (bits 0 to 7) (bits 16 to 23) note (bits 16 to 23) note channel pointer mode register timer macro service pointer (mpt) data macro service pointer (mpd) data sfr pointer (dsfrp) macro service control word low addresses macro service channel high addresses tsfr dsfr timer buffer area data buffer area macro service buffer address = macro service pointer 457 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-31. type c macro service channel (2/2) (b) with ring control note bits 20 to 23 must be set to 0. (3) examples of use of type c (a) basic operation an example is shown below in which the output pattern to the real-time output port and the output interval are directly controlled. update data is transferred from the two data storage areas set in the 1 mb space beforehand to the real- time output function buffer register (rtbl) and the compare register (cr10). macro service counter (msc) timer sfr pointer (tsfrp) (bits 8 to 15) (bits 8 to 15) (bits 8 to 15) (bits 0 to 7) (bits 0 to 7) (bits 0 to 7) (bits 16 to 23) note (bits 16 to 23) note ring counter (rc) channel pointer mode register timer macro service pointer (mpt) data sfr pointer (dsfrp) data macro service pointer (mpd) modulo register (mr) macro service control word low addresses macro service channel high addresses tsfr dsfr timer buffer area data buffer area macro service buffer address = macro service pointer 458 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-32. stepping motor open loop control by real-time output port remark internal ram addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 1 mb memory space macro service control word, macro service channel (internal ram) timer/ counter1 tm1 output latch p120 0fe5eh 123408h 123400h output data area lower 8 bits of cr10 address type c, mpt/mpd incremented, 1-byte timer data, no automatic addition, no ring control, interrupt request generation at msc = 0 lower 8 bits of rtbl address inttm1 match real-time output trigger/ macro service start 1 +1 123411h 123409h output timing data area t9 ... t2 t1 d9 d2 d1 ... msc 00h 09h 52h mpt 12h 34h dsfrp 09h 98h 12h mpd channel pointer 34h 00h 5eh tsfrp mode register 0fh stepping motor internal bus compare register cr10 buffer register rtbl p120 p121 p122 p123 +1 459 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-33. data transfer control timing tm1 count value count start 0h compare register (cr10) t1 buffer register rtbl inttm1 timer interrupt p120 p122 p123 p121 t1 t2 t7 t8 t9 d1 d2 d3 d4 d5 d6 d7 d9 t3 t4 t5 t6 t8 t7 t3 t2 t4 t5 t6 d8 460 chapter 23 interrupt functions user s manual u13570ej3v0ud (b) examples of use of automatic addition control and ring control (i) automatic addition control the output timing data ( ? t) specified by the macro service pointer (mpt) is added to the contents of the compare register, and the result is written back to the compare register. use of this automatic addition control eliminates the need to calculate the compare register setting value in the program each time. (ii) ring control with ring control, the predetermined output patterns is prepared for one cycle only, and the one-cycle data patterns are output repeatedly in order in ring form. when ring control is used, only the output patterns for one cycle need be prepared, allowing the size of the data rom area to be reduced. the macro service counter (msc) is decremented each time a data transfer is performed. with ring control, too, an interrupt request is generated when msc = 0. when controlling a stepping motor, for example, the output patterns will vary depending on the configuration of the stepping motor concerned, and the phase excitation method (single-phase excitation, two-phase excitation, etc.), but repeat patterns are used in all cases. examples of single- phase excitation and 1-2-phase excitation of a 4-phase stepping motor are shown in figures 23-34 and 23-35. 461 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-34. single-phase excitation of 4-phase stepping motor phase a phase b phase c phase d 1 cycle (4 patterns) 1 2 3 4 1 2 3 figure 23-35. 1-2-phase excitation of 4-phase stepping motor phase a phase b phase c phase d 1 cycle (8 patterns) 1 2 3 4 5 6 7 8 1 2 3 4 8 5 462 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-36. automatic addition control + ring control block diagram 1 (when output timing varies with 1-2-phase excitation) remark internal ram addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. . d1 p120 p120 p122 p121 p123 0fe5ah 1237fch 123402h 1237feh 123007h 123000h output data (8 items) d7 d0 msc macro service control word, macro service channel (internal ram) 1 mb memory space 01h 00h 12h mpt 12h 34h dsfrp 00h 98h 12h mpd 30h mr 00h rc channel pointer mode register buffer regist (rtbl) 16-bit capture/ compare register 00 (cr00) 08h 08h 5ah . . . . . . tsfrp 7fh lower 8 bits of cr00 lower 8 bits of rtbl type c, mpt/mpd incremented, 2-byte timer data, automatic addition, ring control, interrupt request generation at msc = 0 intp2 to stepping motor t256 t ? 1 + 2 + 1 ? 1 t t1 output timing: 123400h to0 match addition output latch 16-bit timer counter 0 (tm0) external connection 463 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-37. automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) note for the intp2 high-/low-level width, refer to the data sheet. tm0 count value count starts 0h ffffh compare register (cr00) t0 t1 t2 t3 t4 t7 t8 t9 t5 t6 buffer register rtbl intp2 (to0) t1 p120 p122 p123 p121 t3 t4 t5 t6 t9 t0 t7 t8 d1 d2 d3 d4 d5 d6 d7 d0 d0 d7 t2 t t1 t2 t3 t4 t5 t6 t7 t0+ t t1+ t t2+ t t3+ t t4+ t t5+ t t6+ t t7+ t t8+ t t9 + t 464 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-38. automatic addition control + ring control block diagram 2 (1-2-phase excitation constant-velocity operation) remark internal ram addresses in the figure are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 1mb memory space macro service control word, macro service channel (internal ram) 16-bit capture/ compare register 00 (cr00) 16-bit timer counter 0 (tm0) addition buffer register (rtbl) output latch p120 p120 p122 p121 p123 0fe7ah 123007h output timing: 1233ffh 123000h output data (8 items) d7 d6 d0 . . . msc ffh ffh 12h mpt 12h 33h dsfrp ffh 98h 12h mpd 30h mr 07h rc 08h 08h channel pointer 7ah tsfrp mode register 3ch lower 8 bits of cr00 address type c, mpt retained, mpd decremented, 1-byte timer data, automatic addition, ring control, interrupt request generation at msc = 0 lower 8 bits of rtbl address to stepper motor match intp2 to0 t external connection 465 chapter 23 interrupt functions user s manual u13570ej3v0ud figure 23-39. automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant-velocity operation) note for the intp2 high-/low-level width, refer to the data sheet. tm0 count value 0h ffffh compare register (cr10) t0 buffer register rtbl d6 d5 d4 d3 d2 d1 d0 d7 d6 d7 d0 intp2 (to0) ? t p120 p122 p123 p121 count starts t1 t2 t3 t4 t5 t6 t7 t8 t9 t0+ ? t t1 t2 t3 t4 t5 t6 t7 t8 t9 t1+ ? t t2+ ? t t3+ ? t t4+ ? t t5+ ? t t6+ ? t t7+ ? t t8+ ? t t9+ ? t 466 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.8.9 counter mode (1) operation msc is decremented the number of times set in advance to the macro service counter (msc). because the number of times an interrupt occurs can be counted, this function can be used as an event counter where the interrupt generation cycle is long. figure 23-40. macro service data transfer processing flow (counter mode) macro service request acknowledged reads contents of macro service mode register identifies channel type msc msc ? 1 others to other macro service processing msc is 16 bits wide counter mode msc = 0? no yes vcie = 1? no yes clears interrupt service mode bit (ism) to 0 clears interrupt request flag (if) to 0 end end (vectored interrupt request is generated) 467 chapter 23 interrupt functions user s manual u13570ej3v0ud (2) configuration of macro service channel the macro service channel consists of only a 16-bit macro service counter (msc). the lower 8 bits of the address of the msc are written to the channel pointer. figure 23-41. counter mode ? ? ? ? ? macro service channel macro service counter (msc) higher 8 bytes lower 8 bytes high addresses low addresses channel pointer mode register 70 (3) example of using counter mode here is an example of counting the number of edges input to external interrupt pin intp5. figure 23-42. counting number of edges remark the internal ram addresses in the figure above are the values when the location 0h instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. (internal ram) intp5 macro service request msc 0eh higher 8 bytes lower 8 bytes 7eh channel pointer 00h mode register counter mode interrupt request is generated when msc = 0. internal bus 0fe7eh 1 intp5/p05 468 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.9 when interrupt requests and macro service are temporarily held pending when the following instructions are executed, interrupt acknowledgement and macro service processing are temporarily held pending for 8 system clock cycles. however, software interrupts are not held pending. ei di brk brkcs retcs retcsb !addr16 reti retb location 0h or location 0fh pop psw popu post mov pswl, a mov pswl, #byte movg sp, #imm24 write instruction and bit manipulation instruction (excluding bt and bf) to interrupt control registers note , mk0, mk1, imc, ispr, and snmi psw bit manipulation instruction (excluding the bt pswl.bit, $addr20 instruction, bf pswl.bit, $addr20 instruction, bt pswh.bit, $addr20 instruction, bf pswh.bit, $addr20 instruction, set1 cy instruction, not1 cy instruction, and clr1 cy instruction) note interrupt control registers: wdtic, pic0, pic1, pic2, pic3, pic4, pic5, pic6, csiic0, seric1, sric1, stic1, seric2, sric2, stic2, tmic3, tmic00, tmic01, tmic1, tmic2, adic, tmic5, tmic6, tmic7, tmic8, wtic, kric caution if problems are caused by a long pending period for interrupts and macro servicing when the corresponding instructions are used in succession, a time during which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. 469 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.10 instructions whose execution is temporarily suspended by interrupt or macro service execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. the suspended instruction is resumed after completion of the interrupt service program or macro service processing. temporarily suspended instructions: movm, xchm, movbk, xchbk cmpme, cmpmne, cmpmc, cmpmnc cmpbke, cmpbkne, cmpbkc, cmpbknc sacw 23.11 interrupt and macro service operation timing interrupt requests are generated by hardware. the generated interrupt request sets (1) an interrupt request flag. when the interrupt request flag is set (1), a time of 8 clocks (0.64 s: f xx = 12.5 mhz) is taken to determine the priority, etc. following this, if acknowledgement of that interrupt or macro service is enabled, interrupt request acknowledgement processing is performed when the instruction being executed ends. if the instruction being executed is one which temporarily holds interrupts and macro service, the interrupt request is acknowledged after the following instruction (refer to 23.9 when interrupt requests and macro service are temporarily held pending for pending instructions). figure 23-43. interrupt request generation and acknowledgement (unit: clock = 1/f clk ) interrupt request flag 8 clocks instruction interrupt request acknowledgement processing/macro service processing 470 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.11.1 interrupt acknowledge processing time the time shown in table 23-7 is required to acknowledge an interrupt request. after the time shown in this table has elapsed, execution of the interrupt processing program is started. table 23-7. interrupt acknowledge processing time (unit: clock = 1/f clk ) vector table irom emem branch irom, pram emem pram emem destination stack iram pram emem iram pram emem iram pram emem iram pram emem vectored 26 29 37 + 4n 27 30 38 + 4n 30 33 41 + 4n 31 34 42 + 4n interrupts context 22 23 22 23 switching remarks 1. irom: internal rom (with high-speed fetch specified) pram: peripheral ram of internal ram (only when location 0h instruction is executed in the case of branch destination) iram: internal high-speed ram emem: internal rom when external memory and high-speed fetch are not specified 2. n is the number of wait states per byte necessary for writing data to the stack (the number of wait states is the sum of the number of address wait states and the number of access wait states). 3. if the vector table is emem, and if wait states are inserted in reading the vector table, add 2 m to the value of the vectored interrupt in the above table, and add m to the value of context switching, where m is the number of wait states per byte necessary for reading the vector table. 4. if the branch destination is emem and if wait states are inserted in reading the instruction at the branch destination, add that number of wait states. 5. if the stack is occupied by pram and if the value of the stack pointer (sp) is odd, add 4 to the value in the above table. 6. the number of wait states is the sum of the number of address wait states and the number of access wait states. 471 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.11.2 processing time of macro service macro service processing time differs depending on the type of the macro service, as shown in table 23-8. table 23-8. macro service processing time (units: clock = 1/f clk ) processing type of macro service data area iram others type a sfr memory 1 byte 24 2 bytes 25 memory sfr 1 byte 24 2 bytes 26 type b sfr memory 33 35 memory sfr 34 36 type c 49 53 counter mode msc 017 usc = 0 25 remarks 1. iram: internal high-speed ram 2. in the following cases in the other data areas, add the number of clocks specified below. if the data size is 2 bytes with irom or pram, and the data is located at an odd address: 4 clocks if the data size is 1 byte with emem: number of wait states for data access if the data size is 2 bytes with emem: 4 + 2n (where n is the number of wait states per byte) 3. if msc = 0 with type a, b, or c, add 1 clock. 4. with type c, add the following value depending on the function to be used and the status at that time. ring control: 4 clocks. adds 7 more clocks if the ring counter is 0 during ring control. 472 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.12 restoring interrupt function to initial state if an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, nmi pin input, etc., the entire system must be restored to its initial state. in the pd784218a, interrupt acknowledgement related priority control is performed by hardware. this interrupt acknowledgement related hardware must also be restored to its initial state, otherwise subsequent interrupt acknowledgement control may not be performed normally. a method of initializing interrupt acknowledegement related hardware in the program is shown below. the only way of performing initialization by hardware is by reset input. example movw mk0, #0ffffh ; mask all maskable interrupts mov mk1l, #0ffh iresl : cmp ispr, #0 ; no interrupt service programs running? bz $next movg sp, #retval ; forcibly change sp location reti ; forcibly terminate running interrupt service program, return address = iresl retval : dw loww (iresl) ; stack data to return to iresl with reti instruction db 0 db highw (iresl) ; loww and highw are assembler operators for calculating lower 16 bits and higher 16 bits respectively of symbol next : it is necessary to ensure that a non-maskable interrupt request is not generated via the nmi pin during execution of this program. after this, on-chip peripheral hardware initialization and interrupt control register initialization are performed. when interrupt control register initialization is performed, the interrupt request flags must be cleared (0). 473 chapter 23 interrupt functions user s manual u13570ej3v0ud 23.13 cautions (1) the in-service priority register (ispr) is read-only. writing to this register may result in misoperation. (2) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). (3) the reti instruction must not be used to return from a software interrupt caused by a brk instruction. use the retb instruction. (4) the retcs instruction must not be used to return from a software interrupt caused by a brkcs instruction. use the retcsb instruction. (5) when a maskable interrupt is acknowledged by vectored interruption, the reti instruction must be used to return from the interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (6) the retcs instruction must be used to return from a context switching interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (7) macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. (8) the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgement will not be performed normally if a different instruction is used. if you restart a program from the initial state after a non-maskable interrupt acknowledgement, refer to 23.12 restoring interrupt function to initial state . (9) non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 23.9 . therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (refer to table 3-6 in 3.9 special function registers (sfrs) ), and the cpu becomes deadlocked, or an unexpected signal output from a pin, or pc and psw are written to an address is which ram is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a runaway occurs. therefore, the program following reset release must be as follows. cseg at 0 dw strt cseg base strt: location 0fh; or location 0 movg sp, #imm24 474 chapter 23 interrupt functions user s manual u13570ej3v0ud (10) when the following instructions are executed, interrupt acknowledgement and macro service processing are held pending for 8 system clocks. however, software interrupts are not held pending. ei di brk brkcs retcs retcsb !addr16 reti retb location 0h or location 0fh pop psw popu post mov pswl, a mov pswl, #byte movg sp, #imm24 write instruction and bit manipulation instruction to interrupt control registers note , mk0, mk1, imc, ispr, or snm1 register (excluding bt, bf instructions) psw bit manipulation instructions (excluding bt pswl.bit, $addr20 instruction, bf pswl.bit, $addr20 instruction, bt pswh.bit, $addr20 instruction, bf pswh.bit, $addr20 instruction, set1 cy instruction, not1 cy instruction, clr1 cy instruction) note interrupt control registers: wdtic, pic0, pic1, pic2, pic3, pic4, pic5, pic6, csiic0, seric1, sric1, stic1, seric2, sric2, stic2, tmic3, tmic00, tmic01, tmic1, tmic2, adic, tmic5, tmic6, tmic7, tmic8, wtic, kric caution if problems are caused by a long pending period for interrupts and macro servicing when the corresponding instructions are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. 475 user s manual u13570ej3v0ud chapter 24 local bus interface functions 24.1 external memory expansion function the external memory expansion function connects external memory to the areas other than the internal rom, ram, and sfr. the external memory expansion function has the following two modes. multiplexed bus mode separate bus mode (1) multiplexed bus mode a time-divided address/data bus is used to connect external memory. when external memory is connected, the number of ports used can be reduced. when external memory is connected, ports 4 to 6 are used. ports 4 to 6 control the address/data, read/write strobe, wait signal, and address strobe. table 24-1. pin functions in multiplexed bus mode pin functions in multiplexed bus mode alternate name function functions ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 middle address bus p50 to p57 a16 to a19 high address bus p60 to p63 rd read strobe p64 wr write strobe p65 wait wait signal p66 astb address strobe p67 table 24-2. pin states in ports 4 to 6 in multiplexed bus mode port port 4 port 5 port 6 external expansion mode 0 to 7 0123456701234567 single-chip mode port port port 256 kb expansion mode address/data address address port rd, wr, wait, astb 1 mb expansion mode address/data address address rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as the port in all of the modes. 476 chapter 24 local bus interface functions user s manual u13570ej3v0ud (2) separate bus mode an independent address bus and data bus are used to connect external memory. since an external latch circuit is not used, this mode is useful in reducing the number of parts and the mounting area. ports 4, 5, 6, and 8 are used to connect to the external memory. ports 4, 5, 6, and 8 control the address/data, read/write strobe, and wait signal. table 24-3. pin functions in separate bus mode pin functions in separate bus mode alternate name function functions ad0 to ad7 data bus p40 to p47 a0 to a7 low address bus p80 to p87 a8 to a15 middle address bus p50 to p57 a16 to a19 high address bus p60 to p63 rd read strobe p64 wr write strobe p65 wait wait signal p66 caution in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from pin astb/p67. see figures 24-10 to 24-13 for the output timing. table 24-4. pin states of ports 4, 5, 6, and 8 in separate bus mode port port 4 port 8 port 5 port 6 external expansion mode 0 to 7 012345670123456701234567 single-chip mode port port port port 256 kb expansion data address address address port rd, wr, mode wait, (astb) 1 mb expansion data address address address rd, wr, mode wait, (astb) cautions 1. when the external wait function is not used, the wait pin can be used as a port in all of the modes. 2. in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from the pin astb/p67. see figures 24-10 to 24-13 for the output timing. 477 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.2 control registers (1) memory expansion mode register (mm) mm is an 8-bit register that controls the external expanded memory, sets the number of address waits, and controls the internal fetch cycle. mm can be read or written by a 1-bit or 8-bit memory manipulation instruction. figure 24-1 shows the mm format. reset input sets mm to 20h. figure 24-1. memory expansion mode register (mm) format address: 0ffc4h after reset: 20h r/w symbol 76543210 mm ifch 0 aw 0 mm3 mm2 mm1 mm0 ifch internal rom fetch 0 fetch at the same speed as from external memory. all of the wait control settings are valid. 1 high-speed fetch the wait control settings are invalid. aw address wait setting 0 an address wait is not inserted. 1 a one-clock address wait is inserted in the address output timing. mm3 mm2 mm1 mm0 mode port 4 port 5 p60 to p63 p64 p65 p66 (p40 to p47) (p50 to p57) 0000 single-chip mode port 1000 256 kb expansion ad0 to ad7 a8 to a15 a16, port rd wr astb mode a17 10011 mb expansion a16 to a19 mode other than above setting prohibited 478 chapter 24 local bus interface functions user s manual u13570ej3v0ud (2) external bus type selection register (ebts) ebts is an 8-bit register that sets the operating mode of the external memory expansion function. when the multiplexed bus mode is selected, the p80/a0 to p87/a7 pins can be used as an i/o port. ebts is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets ebts to 00h. figure 24-2. external bus type selection register (ebts) format address: 0ff8ch after reset: 00h r/w symbol 76543210 ebts 0000000 ebts0 ebts0 selection of operating mode of external memory expansion function 0 multiplexed bus mode 1 separate bus mode (3) programmable wait control register (pwc1) pwc1 is an 8-bit register that sets the number of waits. the insertion of wait cycles is controlled by pwc1 over the entire space. pwc1 can be read and written by a 1-bit or 8-bit manipulation instruction. reset input sets pwc1 to aah. figure 24-3. programmable wait control register (pwc1) format address: 0ffc7h after reset: aah r/w symbol 76543210 pwc1 pw01 pw00 pw01 pw00 insertion wait cycles data access cycles, fetch cycles 00 0 3 01 1 4 10 2 5 1 1 low level period that is input at the wait pin remarks 1. the insertion of wait cycles is controlled by the entire address space (except for the peripheral ram area). 2. : don? care 479 chapter 24 local bus interface functions user s manual u13570ej3v0ud caution note that the configuration of the registers used for wait control of the in-circuit emulator differs as follows. if an external wait cycle is set in the internal rom area, the cpu is deadlocked. the deadlock status can be cleared only by reset input. (a) programmable wait control register 1 (pwc1) of in-circuit emulator (b) programmable wait control register 2 (pwc2) of in-circuit emulator remark insertion of wait cycles is controlled on the entire address space (except the peripheral ram area). address: 0ffc7h after reset: aah r/w symbol 7 (n = 0 to 3) wait address pwn1 0 0 1 1 pwn0 0 1 0 1 00c000h to 00ffffh no access wait cycles inserts 1 access wait cycle inserts 2 access wait cycles i nserts access wait state for duration of low level input to wait pin 008000h to 00bfffh 004000h to 007fffh 000000h to 003fffh 65 4 321 0 pw31 pw30 pw21 pw20 pw11 pw10 pw01 pw00 pwc1 7 (n = 4 to 7) wait address pwn1 0 0 1 1 pwn0 0 1 0 1 080000h to 0fffffh no access wait cycles inserts 1 access wait cycle inserts 2 access wait cycles i nserts access wait state for duration of low level input to wait pin 040000h to 07ffffh 020000h to 03ffffh 010000h to 01ffffh 65 4 321 0 pw71 pw70 pw61 pw60 pw51 pw50 pw41 pw40 address: 0ffc8h after reset: aaaah w symbol 15 14 13 12 11 10 9 8 1010 101 0 pwc2 480 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.3 memory map for external memory expansion figures 24-4 to 24-8 show the memory map during memory expansion. even during memory expansion, an external device at the same address as the internal rom area, internal ram area, or sfr area (except for the external sfr area (0ffd0h to 0ffdfh)) cannot be accessed. if these areas are accessed, the memory and sfr in pd784218a are accessed with priority, and the astb, rd, and wd signals are not output (remaining at the inactive level). the output level of the address bus remains at the previous output level. the output of the address/data bus has a high impedance. except in the 1 mb expansion mode, an address for external output is output in the state that masked the high order side of the address set by the program. 481 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-4. pd784214a memory map (1/2) (a) when executing the location 0h instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory external memory note 2 internal rom internal rom internal rom 17fffh fffffh 0ffe0h 0ffcfh 0f100h 00000h 10000h 0ffffh notes 1. area having any expansion size in the unshaded parts 2. external sfr area 482 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-4. pd784214a memory map (2/2) (b) when executing the location 0fh instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory external memory note 2 fffffh fffcfh ff100h 17fffh 00000h fffe0h notes 1. area having any expansion size in the unshaded parts 2. external sfr area 483 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-5. pd784215a memory map (1/2) (a) when executing the location 0h instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory note 2 external memory internal rom internal rom internal rom fffffh 1ffffh 0ffe0h 0ffcfh 0eb00h 00000h 10000h 0ffffh notes 1. area having any expansion size in the unshaded parts 2. external sfr area 484 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-5. pd784215a memory map (2/2) (b) when executing the location 0fh instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory external memory note 2 external memory note 1 fffffh fffe0h fffcfh feb00h 1ffffh 00000h notes 1. area having any expansion size in the unshaded parts 2. external sfr area 485 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-6. pd784216a memory map (1/2) (a) when executing the location 0h instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory external memory note 2 internal rom internal rom internal rom fffffh 1ffffh 0ffe0h 0ffcfh 0df00h 00000h 10000h 0ffffh notes 1. area having any expansion size in the unshaded parts 2. external sfr area 486 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-6. pd784216a memory map (2/2) (b) when executing the location 0fh instruction fffffh fffe0h fffcfh fdf00h 1ffffh 00000h single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory external memory note 2 notes 1. area having any expansion size in the unshaded parts 2. external sfr area 487 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-7. pd784217a memory map (1/2) (a) when executing the location 0h instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory external memory note 2 internal rom internal rom internal rom 2ffffh fffffh 0ffe0h 0ffcfh 0cd00h 00000h 10000h 0ffffh notes 1. area having any expansion size in the unshaded parts 2. external sfr area 488 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-7. pd784217a memory map (2/2) (b) when executing the location 0fh instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory external memory note 2 fffffh fffcfh fcd00h 2ffffh 00000h fffe0h notes 1. area having any expansion size in the unshaded parts 2. external sfr area 489 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-8. pd784218a memory map (1/2) (a) when executing the location 0h instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory note 1 external memory note 2 external memory internal rom internal rom internal rom fffffh 3ffffh 0ffe0h 0ffcfh 0cd00h 00000h 10000h 0ffffh notes 1. area having any expansion size in the unshaded parts 2. external sfr area 490 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-8. pd784218a memory map (2/2) (b) when executing the location 0fh instruction single-chip mode 256 kb expansion mode 1 mb expansion mode internal rom sfr internal ram sfr internal rom sfr internal ram sfr internal rom sfr internal ram sfr note 2 external memory external memory note 2 external memory note 1 fffffh fffe0h fffcfh fcd00h 3ffffh 00000h notes 1. area having any expansion size in the unshaded parts 2. external sfr area 491 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.4 timing of external memory expansion functions 24.4.1 multiplexed bus mode timing next, the timing control signal output pins in the multiplexed bus mode are described below. (1) rd pin (shared by: p64) this pin outputs the read strobe during an instruction fetch or a data access from external memory. during an internal memory access, the read strobe is not output (held at the high level) (2) wr pin (shared by: p65) this pin outputs the write strobe during a data access to external memory. during an internal memory access, the write strobe is not output (held at the high level). (3) wait pin (shared by: p66) this pin inputs the external wait signal. when the external wait is not used, wait pin can be used as an i/o port. during an internal memory access, the external wait signal is ignored. (4) astb pin (shared by: p67) this pin always outputs the address strobe in any instruction fetch or data access from external memory. during an internal memory access, the address strobe is not output (keeps low level). (5) ad0 to ad7, a8 to a15, a16 to a19 pins (shared by: p40 to p47, p50 to p57, p60 to p63) these pins output the address and data signals. when an instruction is fetched or data is accessed from external memory, valid signals are output or input. during an internal memory access, the signals do not change. figures 24-9 to 24-12 are the timing charts. 492 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-9. instruction fetch from external memory in multiplexed bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) astb rd ad0 to ad7 a8 to a19 low address instruction code high address (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb rd ad0 to ad7 a8 to a19 low address instruction code high address internal wait signal (1 clock wait) (c) setting an external wait (pw01, pw00 = 1, 1) astb rd ad0 to ad7 a8 to a19 instruction code high address low address wait 493 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-10. read timing for external memory in multiplexed bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) astb rd ad0 to ad7 a8 to a19 low address read data high address (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb rd ad0 to ad7 a8 to a19 low address high address internal wait signal (1 clock wait) read data (c) setting an external wait (pw01, pw00 = 1, 1) astb rd ad0 to ad7 a8 to a19 high address wait low address read data 494 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-11. write timing for external memory in multiplexed bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) astb ad0 to ad7 a8 to a19 low address write data high address wr hi-z (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb wr ad0 to ad7 a8 to a19 low address write data high address internal wait signal (1 clock wait) hi-z (c) setting an external wait (pw01, pw00 = 1, 1) astb wr ad0 to ad7 a8 to a19 low address write data high address wait hi-z 495 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-12. read modify write timing for external memory in multiplexed bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb ad0 to ad7 a8 to a19 internal wait signal (1 clock wait) rd wr hi-z low address low address read data high address high address write data hi-z (c) setting an external wait (pw01, pw00 = 1, 1) wait astb ad0 to ad7 a8 to a19 rd wr hi-z low address low address write data read data high address high address hi-z astb ad0 to ad7 a8 to a19 rd hi-z hi-z low address high address high address low address read data write data wr 496 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.4.2 separate bus mode timing the timing control signal output pins in the separate bus mode are described next. (1) rd pin (shared by: p64) this pin outputs the read strobe during an instruction fetch or a data access from external memory. during an internal memory access, the read strobe signal is not output (held at the high level). (2) wr pin (shared by: p65) this pin outputs the write strobe during a data access to external memory. during an internal memory access, the write strobe is not output (held at the high level). (3) wait pin (shared by: p66) this pin inputs the external wait signal. when external waits are not used, the wait pin can be used as an i/o port. during an internal memory access, the external wait signal is ignored. (4) ad0 to ad7, a0 to a7, a8 to a15, a16 to a19 pins (shared by: p40 to p47, p80 to p87, p50 to p57, p60 to p63) these pins output the address and data signals. during a instruction fetch or a data access from external memory, valid signals are output or input. the signals of the ad0 to ad7, a8 to a15, and a16 to a19 pins do not change while the internal memory is being accessed. the a0 to a7 pins output the status of the internal bus when the internal memory is accessed. figures 24-13 to 24-16 are the timing charts. caution in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from pin astb/p67. see figures 24-13 to 24-16 for the output timing. 497 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-13. instruction fetch from external memory in separate bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) astb note rd ad0 to ad7 a0 to a7 a8 to a19 low address instruction code high address low address (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb note rd ad0 to ad7 a0 to a7 a8 to a19 low address instruction code high address low address internal wait signal (1 clock wait) (c) setting an external wait (pw01, pw00 = 1, 1) astb note rd ad0 to ad7 a0 to a7 a8 to a19 low address instruction code high address low address wait note in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from the astb/p67 pin. 498 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-14. read timing for external memory in separate bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) astb note rd ad0 to ad7 a0 to a7 a8 to a19 low address read data high address low address (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb note rd ad0 to ad7 a0 to a7 a8 to a19 low address high address low address internal wait signal (1 clock wait) read data (c) setting an external wait (pw01, pw00 = 1, 1) astb note rd ad0 to ad7 a0 to a7 a8 to a19 low address high address wait low address read data note in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from the astb/p67 pin. 499 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-15. write timing for external memory in separate bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) astb note ad0 to ad7 a0 to a7 a8 to a19 low address write data low address high address wr hi-z (b) setting 1 wait cycle (pw01, pw00 = 0, 1) astb note wr ad0 to ad7 a0 to a7 a8 to a19 low address write data low address high address internal wait signal (1 clock wait) hi-z (c) setting an external wait (pw01, pw00 = 1, 1) astb note wr ad0 to ad7 a0 to a7 a8 to a19 low address write data low address high address wait hi-z note in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from the astb/p67 pin. 500 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-16. read modify write timing for external memory in separate bus mode (a) setting 0 wait cycles (pw01, pw00 = 0, 0) (b) setting 1 wait cycle (pw01, pw00 = 0, 1) (c) setting an external wait (pw01, pw00 = 1, 1) note in the separate bus mode, the address strobe does not have to be used. however, the address strobe is output from the astb/p67 pin. write data astb note ad0 to ad7 a0 to a7 read data low address low address a8 to a19 high address high address rd hi-z hi-z low address low address wr astb note ad0 to ad7 a0 to a7 low address low address rd low address wr a8 to a19 high address high address internal wait signal (1 clock wait) write data read data hi-z hi-z low address read data wait astb note ad0 to ad7 a8 to a19 rd wr high address low address write data hi-z hi-z low address high address a0 to a7 low address low address 501 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.5 wait functions if slow memory and i/o are connected externally to the pd784218a, waits can be inserted in the external memory access cycle. during the wait cycle, there is an address wait to guarantee the address decoding time and an access wait to guarantee the access time. 24.5.1 address wait an address wait guarantees the address decoding time. by setting the aw bit in the memory expansion mode register (mm) to 1, an address wait is inserted into the entire memory access time note . when the address wait is inserted, the high level period of the astb signal is lengthened by one system clock (80 ns, f xx = 12.5 mhz). note this excludes the internal ram, internal sfr, and internal rom during a high-speed fetch. when the internal rom access is set to have the same cycle as an external rom access, an address wait is inserted during an internal rom access. figure 24-17. read/write timing by address wait function (1/3) (a) read timing when an address wait is not inserted f xx note high address astb ad0 to ad7 a8 to a19 hi-z hi-z rd input data low address hi-z note f xx : main system clock frequency. this signal is only in the pd784218a. 502 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-17. read/write timing by address wait function (2/3) (b) read timing when an address wait is inserted f xx note astb ad0 to ad7 a8 to a19 hi-z hi-z rd hi-z low address input data high address note f xx : main system clock frequency. this signal is only in the pd784218a. 503 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-17. read/write timing by address wait function (3/3) (c) write timing when an address wait is not inserted f xx note high address astb ad0 to ad7 a8 to a19 hi-z hi-z wr output data low address hi-z (d) write timing when an address wait is inserted f xx note high address astb ad0 to ad7 a8 to a19 hi-z hi-z wr output data low address hi-z note f xx : main system clock frequency. this signal is only in the pd784218a. 504 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.5.2 access wait an access wait is inserted during low rd and wr signals. the low level is lengthened by 1/f xx (80 ns, f xx = 12.5 mhz) per cycle. the wait insertion methods are the programmable wait function that automatically inserts a preset number of cycles and the external wait function that is controlled from the outside by the wait signal. wait cycle insertion control is set by the programmable wait control register (pwc1) for the 1 mb memory space. if an internal rom or internal ram is accessed during a high-speed fetch, a wait is not inserted. if accessing an internal sfr, a wait is inserted based on required timing unrelated to this setting. if set so that an access has the same number of cycles as for an external rom, a wait is also inserted in an internal rom access in accordance with the pwc1 setting. if there is space that was externally selected to be controlled by the wait signal by pwc1, pin p66 acts as the wait signal input pin. reset input makes pin p66 act as an ordinary i/o port. figures 24-18 to 24-20 show the bus timing when an access wait is inserted. 505 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-18. read timing by access wait function (1/2) (a) setting 0 wait cycles (pw01, pw00 = 0, 0) f xx note high address astb (output) ad0 to ad7 a8 to a19 (output) hi-z hi-z rd (output) data (input) low address hi-z (b) setting 1 wait cycle (pw01, pw00 = 0, 1) f xx note high address astb (output) ad0 to ad7 a8 to a19 (output) hi-z hi-z rd (output) data (input) low address hi-z note f xx : main system clock frequency. this signal is only in the pd784218a. 506 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-18. read timing by access wait function (2/2) (c) setting 2 wait cycles (pw01, pw00 = 1, 0) high address astb (output) ad0 to ad7 a8 to a19 (output) hi-z rd (output) data (input) low address hi-z f xx note note f xx : main system clock frequency. this signal is only in the pd784218a. 507 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-19. write timing by access wait function (1/2) (a) setting 0 wait cycles (pw01, pw00 = 0, 0) f xx note high address astb (output) ad0 to ad7 (output) a8 to a19 (output) hi-z hi-z wr (output) data low address hi-z (b) setting 1 wait cycle (pw01, pw00 = 0, 1) f xx note high address astb (output) ad0 to ad7 (output) a8 to a19 (output) hi-z hi-z wr (output) data low address hi-z note f xx : main system clock frequency. this signal is only in the pd784218a. 508 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-19. write timing by access wait function (2/2) (c) setting 2 wait cycles (pw01, pw00 = 1, 0) high address astb (output) ad0 to ad7 (output) a8 to a19 (output) hi-z wr (output) data low address hi-z f xx note hi-z note f xx : main system clock frequency. this signal is only in the pd784218a. 509 chapter 24 local bus interface functions user s manual u13570ej3v0ud figure 24-20. timing by external wait signal (a) read timing (pw01, pw00 = 1, 1) high address astb (output) ad0 to ad7 a8 to a19 (output) hi-z rd (output) data (input) low address hi-z f xx note wait (input) (b) write timing (pw01, pw00 = 1, 1) high address astb (output) ad0 to ad7 (output) a8 to a19 (output) hi-z wr (output) data low address hi-z f xx note wait (input) note f xx : main system clock frequency. this signal is only in the pd784218a. 510 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.6 external access status output function ( pd784218a, 784218ay subseries only) 24.6.1 overview the external access status signal is output from the p37/exa pin. this signal is output at the moment of external access when use of the external bus interface function has been enabled. this signal detected the external access status of other devices connected to the external bus, prohibits other devices from outputting data to the external bus, and enables reception. 24.6.2 configuration of external access status output function figure 24-21. configuration of external access status output function pm3.7 p3.7 exae register (exae) external access control signal stop and idle status signals exa signal generator external access status output circuit (exa) external input p37 port p37/exa 511 chapter 24 local bus interface functions user s manual u13570ej3v0ud address p4, p5, p60 to p63 p67/astb p64/rd p65/wr h p37/exa 24.6.3 external access status enable register the external access status enable register (exae) controls the exa signal output indicated during external access. exae are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets exae to 00h. figure 24-22. external access status enable register (exae) format address: 0ff8dh after reset: 00h symbol 76543210 exae 0000000 exae0 exae0 p37 function 0 port function 1 external access status output function 24.6.4 external access status signal timing a timing chart for the p37/exa and external bus interface pin is shown below. the exa signal is set at low active, and indicates the external access status when at 0 . (a) data fetch timing 512 chapter 24 local bus interface functions user s manual u13570ej3v0ud address p4, p5, p60 to p63 p67/astb p64/rd p65/wr h p37/exa address data p4, p5, p60 to p63 p67/astb p64/rd p65/wr h p37/exa (b) data read timing (c) data write timing 24.6.5 exa pin status during each mode p37/exa pin status during each mode is shown in table 24-5. table 24-5. p37/exa pin status during each mode mode p37/exa functions after reset hi-z after reset is released hi-z immediately after the reset is released (input mode, pm37 = 1) port operations when exae = 00h with pm37 = 0 exa signal output enabled when exae = 01h with pm37 and p37 = 0 when in the halt mode hold when in the idle mode hi-z when in the stop mode hi-z 513 chapter 24 local bus interface functions user s manual u13570ej3v0ud 24.7 external memory connection example figure 24-23. example of local bus interface (a) multiplexed bus mode pd784218a rd wr a8 to a19 astb ad0 to ad7 v dd address latch le q0 to q7 d0 to d7 oe sram cs oe we i/o1 to i/o8 a0 to a19 data bus address bus (b) separate bus mode pd784218a rd wr a0 to a19 ad0 to ad7 v dd address bus sram data bus oe we a0 to a19 cs i/o1 to i/o8 514 user s manual u13570ej3v0ud chapter 25 standby function 25.1 configuration and function the pd784218a has a standby function that can decrease the system? power consumption. the standby function has the following six modes. table 25-1. standby function modes halt mode stops the cpu operating clock. the average power consumption can be reduced by intermittent operation during normal operation. stop mode stops the main system clock. all of the operations in the chip are stopped, and the extremely low power consumption state of only a leakage current is entered. idle mode in this mode, the oscillator continues operating while the rest of the system stops. normal program operation can return to power consumption near that of the stop mode and for the same time as the halt mode. low power consumption mode the subsystem clock is used as the system clock, and the main system clock is stopped. since reduced power consumption is designed, the cpu can operate with the subsystem clock. low power consumption halt mode the cpu operating clock is stopped by the standby function in the low power consumption mode. power consumption for the entire system is decreased. low power consumption idle mode the oscillator continues operating while the rest of the system is stopped by the standby function in the low power consumption mode. power consumption for the entire system is decreased. these modes are programmable. macro service can be started from the halt mode and the low power consumption halt mode. after macro service execution, the device is returned to the halt mode. figure 25-1 shows the standby function state transitions. 515 chapter 25 standby function user s manual u13570ej3v0ud figure 25-1. standby function state transitions notes 1 . only unmasked interrupt requests 2. when intp0 to intp6 and watch timer interrupt (intwt) are not masked remark nmi is only valid with external input. the watchdog timer cannot be used for the release of standby (halt mode/stop mode/idle mode.) wait for stable oscillation normal operation (main system clock operation) macro service halt (standby) idle (standby) low power consumption mode (subsystem clock operation) low power consumption halt mode (standby) low power consumption idle mode (standby) stop (standby) macro service request one-time processing ends macro service ends macro service request one-time processing ends interrupt request note 1 halt set idle set reset input reset input sto p set reset input oscillation stabilization time ends nmi, intp0 to intp6 input, intwt note 2 input low power consumption idle mode set reset input low power consumption mode set return to normal operation low power consumption halt mode set interrupt request note 1 interrupt request for masked interrupt interrupt request for masked interrupt interrupt request for masked interrupt interrupt request for masked interrupt interrupt request for masked interrupt macro service macro service request macro service request one-time processing ends macro service ends one-time processing ends nmi, intp0 to intp6 input, intwt note 2 nmi, intp0 to intp6 input, intw t note 2 reset input reset input 516 chapter 25 standby function user s manual u13570ej3v0ud 25.2 control registers (1) standby control register (stbc) the stbc register sets the stop mode and selects the internal system clock. to prevent the standby mode from accidentally being entered due to a runaway program, this register can only be written by a special instruction. this special instruction is mov stbc, #byte which has a special code structure (4 bytes). this register can only be written when the third and fourth byte op codes are mutual 1 s complements. if the third and fourth byte op codes are not mutual 1 s complements, the register is not written and an operand error interrupt is generated. in this case, the return address that is saved on the stack is the address of the instruction that caused the error. therefore, the address that caused the error can be determined from the return address saved on the stack. if the retb instruction is used to simply return from an operand error, an infinite loop occurs. since an operand error interrupt is generated only when the program runs wild (only the correct instruction is generated when mov stbc, #byte is specified in ra78k4 nec electronics assembler), make the program initialize the system. other write instructions (i.e., mov stbc, a; stbc, #byte; and set1 stbc.7) are ignored and nothing happens. in other words, stbc is not written, and an interrupt, such as an operand error interrupt, is not generated. stbc can always be read by a data transfer instruction. reset input sets stbc to 30h. figure 25-2 shows the stbc format. 517 chapter 25 standby function user s manual u13570ej3v0ud figure 25-2. standby control register (stbc) format address: 0ffc0h after reset: 30h r/w symbol 76543210 stbc sbk ck2 ck1 ck0 0 mck stp hlt sbk oscillation control for subsystem clock 0 oscillator operation (use internal feedback resistors.) 1 oscillator stop (do not use internal feedback resistors.) ck2 ck1 ck0 cpu clock selection 000f xx 001f xx /2 010f xx /4 011f xx /8 111f xt (recommended) 1 f xt mck main system clock oscillation control 0 oscillator operation (use internal feedback resistors.) 1 oscillator stop (do not use internal feedback resistors.) stp hlt operation setting flag 0 0 normal operating mode 0 1 halt mode (automatically cleared when the halt mode is released) 1 0 stop mode (automatically cleared when the stop mode is released) 1 1 idle mode (automatically cleared when the idle mode is released) cautions 1. if the stop mode is used when an external clock is input, set the stop mode after setting bit extc in the oscillation stabilization time specification register (osts) to 1. using the stop mode in the state where bit extc of osts is cleared while the external clock is input may destroy the pd784218a or reduce reliability. when the extc bit of osts is set to 1, always input at pin x2 the clock that has the inverse phase of the clock input at pin x1. 2. execute three nop instructions after the standby instruction (after releasing the standby). if this is not done, when the execution of a standby instruction competes with an interrupt request, the standby instruction is not executed, and interrupts are acknowledged after executing multiple instructions that follow a standby instruction. the instruction that is executed before acknowledging the interrupt starts executing within a maximum of six clocks after the standby instruction is executed. 518 chapter 25 standby function user s manual u13570ej3v0ud example mov stbc, #byte nop nop nop : 3. when ck2 = 0, even if mck = 1, the oscillation of the main system clock does not stop (refer to 4.5.1 main system clock operations). remarks 1. f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 2. : don t care (2) clock status register (pcs) pcs is a read-only 8-bit register that shows the operating state of the cpu clock. when bits 2, and 4 to 7 in pcs are read, the corresponding bits in the standby control register (stbc) can be read. pcs is read by a 1-bit or 8-bit memory manipulation instruction. reset input sets pcs to 32h. 519 chapter 25 standby function user s manual u13570ej3v0ud figure 25-3. clock status register (pcs) format address: 0ffceh after reset: 32h r symbol 76543210 pcs sbk ck2 ck1 ck0 0 mck 1 cst sbk feedback resistor state for subsystem clock 0 use internal feedback resistors. 1 do not use internal feedback resistors. ck2 ck1 ck0 cpu clock operating frequency 000f xx 001f xx /2 010f xx /4 011f xx /8 111f xt (recommended) 1 f xt mck main system clock oscillation control 0 oscillator operation. 1 oscillator stop. cst cpu clock state 0 main system clock operation 1 subsystem clock operation caution bit 1 of the clock status register (pcs) of the device is fixed to 1, but is fixed to 0 in the in- circuit emulator. keep this in mind when using the in-circuit emulator. remark : don t care 520 chapter 25 standby function user s manual u13570ej3v0ud (3) oscillation stabilization time specification register (osts) the osts register sets the oscillator operation and the oscillation stabilization time when the stop mode is released. whether a crystal/ceramic resonator or an external clock will be used is set in the extc bit of osts. if only the extc bit is set to 1, the stop mode can also be set when the external clock is input. bits osts0 to osts2 in osts select the oscillation stabilization time when the stop mode is released. generally, select an oscillation stabilization time of at least 40 ms when using a crystal resonator and at least 4 ms when using a ceramic resonator. the time until the stabilization oscillation is affected by the crystal/ceramic resonator that is used and the capacitance of the connected capacitor. therefore, if you want a short oscillation stabilization time, consult the manufacturer of the crystal/ceramic resonator. osts is set by a 1-bit or 8-bit transfer instruction. reset input sets osts to 00h. figure 25-4 shows the osts format. 521 chapter 25 standby function user s manual u13570ej3v0ud figure 25-4. oscillation stabilization time specification register (osts) format address: 0ffcfh after reset: 00h r/w symbol 76543210 osts extc 0000 osts2 osts1 osts0 extc external clock selection 0 use crystal/ceramic oscillation 1 use an external clock extc osts2 osts1 osts0 oscillation stabilization time selection 00002 19 /f xx (42.0 ms) 00012 18 /f xx (21.0 ms) 00102 17 /f xx (10.5 ms) 00112 16 /f xx (5.3 ms) 01002 15 /f xx (2.6 ms) 01012 14 /f xx (1.3 ms) 01102 13 /f xx (0.7 ms) 01112 12 /f xx (0.4 ms) 1 512/f xx (41.0 s) cautions 1. when using crystal/ceramic oscillation, always clear the extc bit to 0. when the extc bit is set to 1, oscillation stops. 2. if the stop mode is used when an external clock is input, always set the extc bit to 1 and then set the stop mode. using the stop mode in the state where the extc bit is cleared while the external clock is input may destroy the pd784218a or reduce reliability. 3. when the extc bit is set to 1 when an external clock is input, input to pin x2 a clock that has the inverse phase of the clock input to pin x1. if the extc bit is set to 1, the pd784218a only operates with the clock that is input to the x2 pin. remarks 1. figures in parentheses apply to operation with f xx = 12.5 mhz. 2. : don t care 522 chapter 25 standby function user s manual u13570ej3v0ud 25.3 halt mode 25.3.1 settings and operating states of halt mode the halt mode is set by setting the hlt bit in standby control register (stbc) to 1. stbc can be written in with 8-bit data by a special instruction. therefore, the halt mode is specified by the mov stbc, #byte instruction. when enable interrupts is set (ie flag in psw is set to 1), specify three nop instructions after the halt mode setting instruction (after the halt mode is released). if this is not done, after the halt mode is released, multiple instructions may execute before interrupts are acknowledged. unfortunately, the order relationship between the interrupt process and instruction execution changes. since problems caused by the changes in the execution order are prevented, the measures described earlier are required. the system clock when setting can be set to either the main system clock or the subsystem clock. the operating states in the halt mode are described next. 523 chapter 25 standby function user s manual u13570ej3v0ud table 25-2. operating states in halt mode halt mode setting halt mode setting during halt mode setting during main system clock operation subsystem clock operation no subsystem clock subsystem clock when the main system when the main system item note 1 note 2 clock continues oscillating clock stops oscillating clock oscillator both the main system clock and subsystem clock can oscillate. the clock supply to the cpu stops. cpu operation disabled port (output latch) holds the state before the halt mode is set. 16-bit timer/counter operation enabled operation enabled when the watch timer output is selected as the count clock (select f xt as the count clock of the watch timer.) 8-bit timer/counters 1, 2 operation enabled operation enabled when ti1 and ti2 are selected as the count clocks 8-bit timer/counters 5, 6 operation enabled operation enabled when ti5 and ti6 are selected as the count clocks 8-bit timer/counters 7, 8 operation enabled operation enabled when ti7 and ti8 are selected as the count clocks watch timer operation enabled operation enabled operation enabled when f xx /2 7 is selected when f xt is selected as as the count clock the count clock watchdog timer operation disabled (initializing counter) a/d converter operation enabled operation disabled d/a converter operation enabled real-time output port operation enabled serial interface operation enabled operation enabled during an external sck. external interrupt intp0 to intp6 operation enabled key return interrupt p80 to p87 operation enabled bus lines during ad0 to ad7 high impedance external expansion a0 to a19 holds the state before the halt mode is set astb low level wr, rd high level wait holds input status exa holds the state before the halt mode is set notes 1. this includes not supplying the external clock. 2. this includes supplying the external clock. 524 chapter 25 standby function user s manual u13570ej3v0ud 25.3.2 releasing halt mode the halt mode can be released by the following three sources. nmi pin input maskable interrupt request (vectored interrupt, context switching, macro service) reset input table 25-3 lists the release source and describes the operation after release. 525 chapter 25 standby function user s manual u13570ej3v0ud table 25-3. releasing halt mode and operation after release mk note 1 0 0 1 0 1 ie note 2 1 0 release source reset input nmi pin input maskable interrupt request (except for a macro service request) macro service request state during release not executing a non-maskable interrupt service program executing a low-priority non-maskable interrupt service program executing the service program for the nmi pin input executing a high-priority non-maskable interrupt service program not executing an interrupt service program executing a low-priority maskable interrupt service program the prsl bit note 4 is cleared to 0 while executing an interrupt service program at priority level 3. executing a maskable interrupt service program with the same priority (this excludes executing an interrupt service program in priority level 3 when the prsl bit note 4 is cleared to 0.) executing a high-priority interrupt service program operation after release normal reset operation acknowledges interrupt requests the instruction following the mov stbc, #byte instruction is executed. (the interrupt request that released the halt mode is held note 3 .) acknowledges interrupt requests the instruction following the mov stbc, #byte instruction is executed. (the interrupt request that released the halt mode is held note 3 .) holds the halt mode macro service process execution end condition is not satisfied halt mode end condition is satisfied again when vcie note 5 = 1: halt mode again when vcie note 5 = 0: same as a release by the maskable interrupt request holds the halt mode notes 1. interrupt mask bit in each interrupt request source 2. interrupt enable flag in the program status word (psw) 3. the held interrupt request is acknowledged when acknowledgement is enabled. 4. bit in the interrupt mode control register (imc) 5. bit in the macro service mode register of the macro service control word that is in each macro service request source 526 chapter 25 standby function user s manual u13570ej3v0ud figure 25-5. operation after halt mode release (1/4) (1) interrupt after halt mode (2) reset after halt mode main routine mov stbc, #byte halt mode normal reset operation reset input main routine mov stbc, #byte halt mode ? halt mode release ? interrupt processing interrupt request 527 chapter 25 standby function user s manual u13570ej3v0ud figure 25-5. operation after halt mode release (2/4) (3) halt mode during interrupt processing routine whose priority is higher than or equal to release source interrupt (4) halt mode during interrupt processing routine whose priority is lower than release source interrupt main routine mov stbc, #byte halt mode ? halt mode release ? hold on halt mode release source interrupt ? execution of interrupt in being held int main routine mov stbc, #byte halt mode ? halt mode release ? interrupt execution of halt mode release source int 528 chapter 25 standby function user s manual u13570ej3v0ud figure 25-5. operation after halt mode release (3/4) (5) macro service request during halt mode (a) immediately after macro service end condition is satisfied, interrupt request is issued. (vcie = 0) (b) macro service end condition is not satisfied, or after macro service end condition is satisfied, interrupt request is not issued. (vcie = 1) main routine mov stbc, #byte halt mode ? halt mode release ? interrupt request processing with macro service end ? macro service processing last macro service request main routine mov stbc, #byte halt mode back to halt mode ? halt mode release int (other than macro service) ? macro service processing last macro service request 529 chapter 25 standby function user s manual u13570ej3v0ud figure 25-5. operation after halt mode release (4/4) (6) halt mode which the interrupt is held, which is enabled in an instruction that interrupt requests are temporarily held. (7) contention between halt instruction and interrupt main routine mov stbc, #byte ei ? halt mode release ? interrupt processing interrupt is held for duration of 8 blocks interrupt request main routine mov stbc, #byte execute instruction at most 6 clocks ? interrupt processing ? halt mode not executed interrupt request 530 chapter 25 standby function user s manual u13570ej3v0ud (1) released by nmi pin input when a non-maskable interrupt is generated by nmi pin input, the halt mode is released regardless of the enable state (ei) and disable state (di) for interrupt acknowledgement. if the non-maskable interrupt that released the halt mode by nmi pin input can be acknowledged when released from the halt mode, and execution branches to the nmi interrupt service program. if it cannot be acknowledged, the instruction following the instruction that set the halt mode (mov stbc, #byte instruction) is executed. the non-maskable interrupt that released the halt mode is acknowledged when acceptance is possible. for details about non-maskable interrupts acknowledgement, refer to 23.6 non-maskable interrupt acknowledge . caution the halt mode cannot be released by watchdog timer. (2) released by a maskable interrupt request the halt mode released by a maskable interrupt request can only be released by an interrupt where the interrupt mask flag is 0. if an interrupt can be acknowledged when the halt mode is released and the interrupt request enable flag (ie) is set to 1, execution branches to the interrupt service program. if the ie flag is cleared to 0 when acknowledgement is not possible, execution restarts from the next instruction that sets the halt mode. for details about interrupt acknowledgement, refer to 23.7 maskable interrupt acknowledge . a macro service temporarily releases the halt mode, performs the one-time processing, and returns again to the halt mode. if the macro service is only specified several times, the halt mode is released when the vcie bit in the macro service mode register in the macro service control word is cleared to 0. the operation after this release is identical to the release by the maskable interrupt described earlier. also when the vcie bit is set to 1, the halt mode is entered again, and the halt mode is released by the next interrupt request. 531 chapter 25 standby function user s manual u13570ej3v0ud table 25-4. releasing halt mode by maskable interrupt request mk note 1 0 0 1 0 1 ie note 2 1 0 release source maskable interrupt request (except for a macro service request) macro service request state during release not executing an interrupt service program executing a low-priority maskable interrupt service program the prsl bit note 4 is cleared to 0 while executing an interrupt service program at priority level 3. executing a maskable interrupt service program with the same priority (this excludes executing an interrupt service program in priority level 3 when the prsl bit note 4 is cleared to 0.) executing a high-priority interrupt service program operation after release acknowledges interrupt requests the instruction following the mov stbc, #byte instruction is executed. (the interrupt request that released the halt mode is held note 3 .) holds the halt mode macro service process execution end condition is not satisfied halt mode end condition is satisfied again when vcie note 5 = 1: halt mode again when vcie note 5 = 0: same as a release by a maskable interrupt request holds the halt mode notes 1. interrupt mask bit in each interrupt request source 2. interrupt enable flag in the program status word (psw) 3. the held interrupt request is acknowledged when acknowledgement is possible. 4. bit in the interrupt mode control register (imc) 5. bit in the macro service mode register of the macro service control word that is in each macro service request source (3) released by reset input after branching to the reset vector address as in a normal reset, the program executes. however, the contents of the internal ram hold the value before the halt mode was set. 532 chapter 25 standby function user s manual u13570ej3v0ud 25.4 stop mode 25.4.1 settings and operating states of stop mode the stop mode is set by setting the stp bit in the standby control register (stbc) to 1. stbc can be written with 8-bit data by a special instruction. therefore, the stop mode is set by the mov stbc, #byte instruction. when enable interrupt is set (ie flag in psw is set to 1), specify three nop instructions after the stop mode setting instruction (after the stop mode is released) . if this is not done, after the stop mode is released, multiple instructions can be executed before interrupts are acknowledged. unfortunately, the order relationship between the interrupt process and instruction execution changes. since the problems caused by changes in the execution order are prevented, the measures described earlier are required. the system clock during setting can only be set to the main system clock. caution since an interrupt request signal is used when releasing the standby mode, when there is an interrupt source that sets the interrupt request flag or resets the interrupt mask flag, even though the standby mode is entered, it is immediately released. when the stop mode setting instruction conflicts with the setting of an unmasked interrupt request flag or a non-maskable interrupt request, either of following two statuses are entered. (1) status in which stop mode is set once, and then released (2) status in which stop mode is not set the oscillation stabilization time after releasing stop mode is inserted only for the status in which stop mode is set once and then released. next, the operating states during the stop mode are described. 533 chapter 25 standby function user s manual u13570ej3v0ud table 25-5. operating states in stop mode stop mode setting when there is a subsystem clock when there is no subsystem clock item clock generator only main system clock stops oscillating. cpu operation disabled port (output latch) holds the state before the stop mode was set. 16-bit timer/event counter operation enabled when the watch timer operation disabled output is selected as the count clock (select f xt as the count clock of the watch timer) 8-bit timer/counters 1, 2 operation enabled only when ti1 and ti2 are selected as the count clocks 8-bit timer/counters 5, 6 operation enabled only when ti5 and ti6 are selected as the count clocks 8-bit timer/counters 7, 8 operation enabled only when ti7 and ti8 are selected as the count clocks watch timer operation enabled only when f xt is operation disabled selected as the count clock watchdog timer operation disabled (initializing counter) a/d converter operation disabled d/a converter operation enabled real-time output port operation enabled when an external trigger is used or ti1 and ti2 are selected as the count clocks of the 8-bit timer/counters 1 and 2 serial interface other than operation enabled only when an external input clock is selected as the serial clock i 2 c bus mode i 2 c bus mode operation disabled external interrupt intp0 to intp6 operation enabled key return interrupt p80 to p87 operation enabled bus lines during ad0 to ad7 high impedance external expansion a0 to a7 outputs c0h a8 to a19 high impedance astb high impedance wr, rd high impedance wait holds input status exa high impedance caution in the stop mode, only external interrupts (intp0 to intp6), watch timer interrupt (intwt), and key return interrupts (p80 to p87) can release the stop mode and be acknowledged as interrupt requests. all other interrupt requests are pended, and acknowledged after the stop mode has been released through nmi input, intp0 to intp6 input, intwt, or key return interrupt. 534 chapter 25 standby function user s manual u13570ej3v0ud 25.4.2 releasing stop mode the stop mode is released by nmi input, intp0 to intp6 input, watch timer interrupt (intwt), key return interrupt, or reset input. table 25-6. releasing stop mode and operation after release mk note 1 0 0 1 ism note 2 0 0 0 1 release source reset input nmi pin input intp0 to intp6 pin input, watch timer interrupt note 6 , key return interrupt state during release not executing a non-maskable interrupt service program executing a low-priority non-maskable interrupt service program executing the service program for the nmi pin input executing a high-priority non-maskable interrupt service program not executing an interrupt service program executing a low-priority maskable interrupt service program the prsl bit note 5 is cleared to 0 while an interrupt service program at priority level 3 is executing. executing a maskable interrupt service program with the same priority (this excludes executing an interrupt service program in priority level 3 when the prsl bit note 5 is cleared to 0.) executing a high-priority interrupt service program operation after release normal reset operation acknowledges interrupt requests the instruction following the mov stbc, #byte instruction is executed. (the interrupt request that released the stop mode is held note 4 .) acknowledges interrupt requests the instruction following the mov stbc, #byte instruction is executed. (the interrupt request that released the stop mode is held note 4 .) holds the stop mode ie note 3 1 0 notes 1. interrupt mask bit in each interrupt request source 2. macro service enable flag that is in each interrupt request source 3. interrupt enable flag in the program status word (psw) 4. the held interrupt request is acknowledged when acknowledgement is possible. 5. bit in the interrupt mode control register (imc) 6. the stop mode is released only when the subsystem clock is selected as the count clock. it is not released when the main system clock is selected. 535 chapter 25 standby function user s manual u13570ej3v0ud figure 25-6. operation after stop mode release (1/3) (1) interrupt after stop mode (2) reset after stop mode main routine mov stbc, #byte stop mode ? interrupt processing int (oscillation stabilization time wait) ? stop mode release main routine mov stbc, #byte normal reset operation (including oscillation stabilization time wait) reset input stop mode 536 chapter 25 standby function user s manual u13570ej3v0ud figure 25-6. operation after stop mode release (2/3) (3) stop mode during interrupt processing routine whose priority is higher than or equal to release source interrupt (4) stop mode during interrupt processing routine whose priority is lower than release source interrupt main routine mov stbc, #byte stop mode ? stop mode release ? hold on stop mode release source interrupt ? execution of interrupt in being held int (oscillation stabilization time wait) main routine mov stbc, #byte stop mode ? stop mode release ? interrupt execution of stop mode release source int (oscillation stabilization time wait) 537 chapter 25 standby function user s manual u13570ej3v0ud figure 25-6. operation after stop mode release (3/3) (5) contention between stop mode setting instruction and interrupt ? interrupt servicing ? stop mode not executed main routine mov stbc, #byte execute instruction up to 6 clocks int interrupt request 538 chapter 25 standby function user s manual u13570ej3v0ud (1) releasing the stop mode by nmi input when the valid edge specified in the external interrupt edge enable registers (egp0, egn0) is input by the nmi input, the oscillator starts oscillating again. then the stop mode is released after the oscillation stabilization time set in the oscillation stabilization time specification register (osts) elapses. when the stop mode is released and non-maskable interrupts from the nmi pin input can be acknowledged, execution branches to the nmi interrupt service program. if acknowledgement is not possible (such as when set in the stop mode in the nmi interrupt service program), execution starts again from the instruction following the instruction that set the stop mode. when acknowledgement is enabled, execution branches to the nmi interrupt service program (by executing the reti instruction). for details about nmi interrupt acknowledgement, refer to 23.6 non-maskable interrupt acknowledge . figure 25-7. releasing stop mode by nmi input oscillator f xx /2 stp f/f1 nmi input when the rising edge is set stp f/f2 oscillator stops stop timer count time for oscillation stabilization time until clock starts oscillating 539 chapter 25 standby function user s manual u13570ej3v0ud (2) releasing the stop mode by intp0 to intp6 input, watch timer interrupt, and key return interrupt if interrupt masking is released through intp0 to intp6 input and macro service is disabled, the oscillator restarts oscillating when a valid edge specified in the external interrupt edge enable registers (egp0, egn0) is input to intp0 to intp6. if the mask of watch timer interrupt is released and macro service is disabled, an overflow of watch timer occurs and stop mode is released. if key return interrupt masking is released and macro service is disabled, the oscillator restarts oscillating when a falling edge is input to the port 8 pins (p80 to p87). then the stop mode is released after the oscillation stabilization time specified in the oscillation stabilization time specification register (osts) elapses. if interrupts can be acknowledged when released from the stop mode and the interrupt enable flag (ie) is set to 1, execution branches to the interrupt service program. if the ie flag is cleared to 0 when acknowledgement is not possible, execution starts again from the instruction following the instruction that set the stop mode. for details on interrupt acknowledgement, refer to 23.7 maskable interrupt acknowledge . figure 25-8. example of releasing stop mode by intp0 to intp6 inputs intp0 to intp6 inputs when the rising edge is specified oscillator f xx /2 stp f/f1 stp f/f2 oscillator stops stop timer count time for oscillation stabilization time until clock starts oscillating (3) releasing the stop mode by reset input when reset input rises from low to high and the reset is released, the oscillator starts oscillating. the oscillation stops for the reset active period. after the oscillation stabilization time has elapsed, normal operation starts. the difference from the normal reset operation is the data memory saves the contents before setting the stop mode. 540 chapter 25 standby function user s manual u13570ej3v0ud 25.5 idle mode 25.5.1 settings and operating states of idle mode the idle mode is set by setting both bits stp and hlt in the standby control register (stbc) to 1. stbc can only be written with 8-bit data by using a special instruction. therefore, the idle mode is set by the mov stbc, #byte instruction. when enable interrupts is set (the ie flag in psw is set to 1), specify three nop instructions after the idle mode setting instruction (after the idle mode is released). if this is not done, after the idle mode is released, multiple instructions can be executed before interrupts are acknowledged. unfortunately, the order relationship between the interrupt processing and the instruction execution changes. to prevent the problems caused by the change in the execution order, the measures described earlier are required. the system clock when setting can be set to either the main system clock or the subsystem clock. the operating states in the idle mode are described next. 541 chapter 25 standby function user s manual u13570ej3v0ud table 25-7. operating states in idle mode idle mode setting when there is a subsystem clock when there is not a subsystem clock item clock generator the oscillator in both the main system clock and subsystem clock continue operating. the clock supply to both the cpu and peripherals is stopped. cpu operation disabled port (output latch) holds the state before the idle mode is set 16-bit timer/counter operation enabled when the watch timer operation disabled output is selected as the count clock (select f xt as the count clock of the watch timer.) 8-bit timer/counters 1, 2 operation enabled only when ti1 and ti2 are selected as the count clocks 8-bit timer/counters 5, 6 operation enabled only when ti5 and ti6 are selected as the count clocks 8-bit timer/counters 7, 8 operation enabled only when ti7 and ti8 are selected as the count clocks watch timer operation enabled only when f xt is operation disabled selected as the count clock watchdog timer operation disabled a/d converter operation disabled d/a converter operation enabled real-time output port operation enabled when an external trigger is used or ti1 and ti2 are selected as the count clocks of the 8-bit timer/counters 1 and 2 serial interface other than operation enabled only when an external input clock is selected as the serial clock i 2 c bus mode i 2 c bus mode operation disabled external interrupt intp0 to intp6 operation enabled key return interrupt p80 to p87 operation enabled bus lines during ad0 to ad7 high impedance external expansion a0 to a7 outputs c0h a8 to a19 high impedance astb high impedance wr, rd high impedance wait holds input status exa high impedance caution in the idle mode, only external interrupts (intp0 to intp6), watch timer interrupt (intwt), and key return interrupts (p80 to p87) can release the idle mode and be acknowledged as interrupt requests. all other interrupt requests are pended, and acknowledged after the idle mode has been released through nmi input, intp0 to intp6 input, intwt, or key return interrupt. 542 chapter 25 standby function user s manual u13570ej3v0ud 25.5.2 releasing idle mode the idle mode is released by nmi input, intp0 to intp6 input, watch timer interrupt (intwt), key return interrupt, or reset input. table 25-8. releasing idle mode and operation after release mk note 1 0 0 1 ism note 2 0 0 0 1 release source reset input nmi pin input intp0 to intp6 pin input, watch timer interrupt note 6 , key return interrupt state during release not executing a non-maskable interrupt service program executing a low-priority non-maskable interrupt service program executing the service program for the nmi pin input executing a high-priority non-maskable interrupt service program not executing an interrupt service program executing a low-priority maskable interrupt service program the prsl bit note 5 is cleared to 0 while executing an interrupt service program at priority level 3. executing the maskable interrupt service program with the same priority (this excludes executing an interrupt service program in priority level 3 when the prsl bit note 5 is cleared to 0.) executing a high-priority interrupt service program operation after release normal reset operation acknowledges interrupt requests executes the instruction following the mov stbc, #byte instruction (the interrupt request that released the idle mode is held note 4 .) acknowledges interrupt requests execute the instruction following the mov stbc, #byte instruc- tion. (the interrupt request that released the idle mode is held note 4 .) holds the idle mode ie note 3 1 0 notes 1. interrupt mask bit in each interrupt request source 2. macro service enable flag that is in each interrupt request source 3. interrupt enable flag in the program status word (psw) 4. the held interrupt request is acknowledged when acknowledgement is possible. 5. bit in the interrupt mode control register (imc) 6. the idle mode is released only when the subsystem clock is selected as the count clock. it is not released when the main system clock is selected. 543 chapter 25 standby function user s manual u13570ej3v0ud figure 25-9. operation after idle mode release (1/3) (1) interrupt after idle mode (2) reset after idle mode main routine mov stbc, #byte idle mode normal reset operation reset input main routine mov stbc, #byte ? idle mode release ? interrupt processing idle mode interrupt request 544 chapter 25 standby function user s manual u13570ej3v0ud figure 25-9. operation after idle mode release (2/3) (3) idle mode during interrupt processing routine whose priority is higher than or equal to release source interrupt (4) idle mode during interrupt processing routine whose priority is lower than release source interrupt main routine mov stbc, #byte idle mode ? idle mode release ? hold on idle mode release source interrupt ? execution of interrupt in being held int main routine mov stbc, #byte idle mode ? idle mode release ? interrupt execution of idle mode release source int 545 chapter 25 standby function user s manual u13570ej3v0ud figure 25-9. operation after idle mode release (3/3) (5) contention between idle mode setting instruction and interrupt ? interrupt servicing ? idle mode not executed main routine mov stbc, #byte execute instruction up to 6 clocks int 546 chapter 25 standby function user s manual u13570ej3v0ud (1) releasing the idle mode by nmi input when the valid edge specified in the external interrupt edge enable registers (egp0, egn0) is input by the nmi input, the idle mode is released. when the idle mode is released and the non-maskable interrupt from the nmi pin input can be acknowledged, execution branches to the nmi interrupt service program. if acknowledgement is not possible (such as when set in the idle mode in the nmi interrupt service program), execution starts again from the instruction following the instruction that set the idle mode. when acknowledgement is enabled, execution branches to the nmi interrupt service program (by executing the reti instruction). for details about nmi interrupt acknowledgement, refer to 23.6 non-maskable interrupt acknowledge . (2) releasing the idle mode by intp0 to intp6 input, watch timer interrupt and key return interrupt if interrupt masking by intp0 to intp6 input is released and macro service is disabled and the valid edge specified with the external interrupt edge enable register (egp0, egn0) is input to intp0 to intp6, the idle mode is released. if the mask of watch timer interrupt is released and macro service is disabled, an overflow of watch timer occurs and idle mode is released. if key return interrupt masking is released and macro service is disabled, and a falling edge is input to port 8 (p80 to p87), the idle mode is released. if interrupts can be acknowledged when released from the idle mode and the interrupt enable flag (ie) is set to 1, execution branches to the interrupt service program. if the ie flag is cleared to 0 when acknowledgement is not possible, execution starts again from the instruction following the instruction that set the idle mode. for details on interrupt acknowledgement, refer to 23.7 maskable interrupt acknowledge . (3) releasing the idle mode by reset input when reset input rises from low to high and the reset is released, the oscillator starts oscillating. the oscillation stops for the reset active period. after the oscillation stabilization time has elapsed, normal operation starts. the difference from the normal reset operation is the data memory saves the contents before setting the idle mode. 547 chapter 25 standby function user s manual u13570ej3v0ud 25.6 check items when using stop or idle mode the checks required to decrease the current consumption when using the stop mode or idle mode are described below. (1) is the output level of each output pin appropriate? the appropriate output level of each pin differs with the circuit in the next stage. select the output level so that the current consumption is minimized. if a high level is output when the input impedance of the circuit in the next stage is low, current flows from the power source to the port, and the current consumption increases. this occurs when the circuit in the next stage is, for example, a cmos ic. when the power supply is turned off, the input impedance of a cmos ic becomes low. to suppress the current consumption and not negatively affect the reliability of the cmos ic, output a low level. if a high level is output, latch-up results when the power supply is applied again. depending on the circuit in the next stage, the current consumption sometimes increases when a low level is input. in this case, output a high level or high impedance to eliminate the current consumption. when the circuit in the next stage is a cmos ic, if the output is high impedance when power is supplied to the cmos ic, the current consumption of the cmos ic sometimes increases (in this case, the cmos ic overheats and is sometimes destroyed). in this case, output a suitable level or pull-up or pull-down resistors. the setting method for the output level differs with the port mode. since the output level is determined by the state of the internal hardware when the port is in the control mode, the output level must be set while considering the state of the internal hardware. the output level can be set by writing to the output latch of the port and the port mode register by the software when in the port mode. when the port enters the control mode, the output level setting is simplified by switching to the port mode. 548 chapter 25 standby function user s manual u13570ej3v0ud (2) is the input level to each input pin appropriate? set the voltage level input to each pin within the range from the v ss voltage to the v dd voltage. if a voltage outside of this range is applied, not only does the current consumption increase, but the reliability of the pd784218a is negatively affected. in addition, do not increase the middle voltage. (3) are internal pull-up resistors needed? unnecessary pull-up resistors increase the current consumption and are another cause of device latch-up. set the pull-up resistors to the mode in which they are used only in the required parts. when the parts needing pull-up resistors and the parts not needing them are mixed together, externally connect the pull-up resistors where they are needed and set the mode in which the internal pull-up resistors are not used. (4) are the address bus, the address/data bus, etc. handled appropriately? the address bus, address/data bus, and rd and wr pins have high impedances in the stop and idle modes. normally, these pins are pulled up by pull-up resistors. if the pull-up resistors are connected to the power supply that is backed up, the current flows through the pull-up resistors when the low input impedance of the circuit connected to the power supply that is not backed up, and the current consumption increases. therefore, connect the pull-up resistors on the power supply side that is not backed up as shown in figure 25-10. the astb pin has a high impedance in both the stop and idle modes. handle in the manner described in (1) above. figure 25-10. example of handling address/data bus set the input voltage level applied to the wait pin in the range from the v ss voltage to the v dd voltage. if a voltage outside of this range is applied, not only does the current consumption increase, but the reliability of the pd784218a is negatively affected. v dd in/out cmos ic, etc. v ss power supply that is not backed up v dd adn (n = 0 to 7) v ss power supply that is backed up pd784218a 549 chapter 25 standby function user s manual u13570ej3v0ud (5) a/d converter the current flowing through pins av dd and av ref0 can be reduced by clearing the adcs bit, that is bit 7 in the a/d converter mode register (adm), to 0. furthermore, if you want to decrease the current, disconnect the current supplied to av ref0 by an externally attached circuit. the av dd pin must always have the same voltage as the v dd pin. if current is not supplied to the av dd pin in the stop mode, not only does the current consumption increase, but the reliability of the pd784218a is negatively affected. (6) d/a converter the d/a converter consumes a constant current in the stop and idle modes. by clearing the dacen (n = 0, 1) bits in the d/a converter mode registers (dam0, dam1) to 0, the output of anon (n = 0, 1) has high impedance, and the current consumption can be decreased. do not apply an external voltage to the anon pins. if an external voltage is applied, not only is the current consumption increased, but the pd784218a may be destroyed or the reliability decreased. 550 chapter 25 standby function user s manual u13570ej3v0ud 25.7 low power consumption mode 25.7.1 setting low power consumption mode note when the low power consumption mode is entered, set 70h in the standby control register (stbc). this setting switches the system clock from the main system clock to the subsystem clock. whether the system clock switched to the subsystem clock can be verified from the data read from bit cst in the clock status register (pcs) (refer to figure 25-3 ). to check whether switching has ended, set 74h in stbc to stop the oscillation of the main system clock. then switch to the backup power supply from the main power supply. note the low power consumption mode is the state where the subsystem clock is used as the system clock, and the main system clock is stopped. figure 25-11 shows the flow for setting subsystem clock operation. figure 25-12 shows the setting timing diagram. figure 25-11. flow for setting subsystem clock operation normal operation using the main system clock write stbc = 70h. cst bit = 1 write stbc = 74h. switch to the backup power supply. end execute the instruction to switch to the subsystem clock. verify the switch to the subsystem clock. stop the oscillation of the main system clock. 551 chapter 25 standby function user s manual u13570ej3v0ud figure 25-12. setting timing for subsystem clock operation main system clock subsystem clock system clock stbc cst bit power supply stop main system clock oscillation. 00h 70h 74h subsystem clock main power supply backup power supply power supply switching 25.7.2 returning to main system clock operation when returning to main system clock operation from subsystem clock operation, the system power supply first switches to the main power supply and enables the oscillation of the main system clock (set stbc = 70h). then the software waits the oscillation stabilization time of the main system clock, and the system clock switches to the main system clock (set stbc to 00h). cautions 1. when returning from subsystem clock operation (stopped oscillation of the main system clock) to main system clock operation, do not simultaneously specify bit mck = 0 and bit ck2 = 0 by write instructions to stbc. 2. the oscillation stabilization time specification register (osts) specifies the oscillation stabilization time after the stop mode is released, except when released by reset, when the system clock is the main system clock. this cannot be used when the system clock is restored from the subsystem clock to the main system clock. figure 25-13 is the flow for restoring main system clock operation, and figure 25-14 is the restore timing diagram. 552 chapter 25 standby function user s manual u13570ej3v0ud figure 25-13. flow to restore main system clock operation switch to the main power supply. write stbc = 70h has the oscillation stabilization time elapsed? write stbc = 00h end no yes operating with the backup power supply execute the instruction that starts the main system clock. software wait execute the instruction that switches to the main system clock. normal operation using the subsystem clock figure 25-14. timing for restoring main system clock operation main system clock subsystem clock system clock stbc cst bit 74h 70h oscillation stabilization time 00h switch to main system clock main power supply backup power supply power supply 25.7.3 standby function in low power consumption mode the standby function in the low power consumption mode has a halt mode and an idle mode. 553 chapter 25 standby function user s manual u13570ej3v0ud (1) halt mode (a) halt mode settings and the operating states when set in the halt mode in the low power consumption mode, set 75h in stbc. table 25-9 shows the operating states in the halt mode. table 25-9. operating states in halt mode item operating state clock generator the clock supplied to the cpu stops, and only the main system clock stops oscillating. cpu operation disabled port (output latch) holds the state before the halt mode is set 16-bit timer/counter operation enabled when the watch timer output is selected as the count clock (select f xt as the count clock of the watch timer) 8-bit timer/counters 1, 2 operation enabled when ti1 and ti2 are selected as the count clocks 8-bit timer/counters 5, 6 operation enabled when ti5 and ti6 are selected as the count clocks 8-bit timer/counters 7, 8 operation enabled when ti7 and ti8 are selected as the count clocks watch timer operation enabled only when f xt is selected as the count clock watchdog timer operation disabled (initializing counter) a/d converter operation disabled d/a converter operation enabled real-time output port operation enabled when an external trigger is used or ti1 and ti2 are selected as the count clocks of the 8-bit timer/counters 1 and 2 serial interface other than operation enabled only when an external input clock is selected as the serial clock i 2 c bus mode i 2 c bus mode operation disabled external interrupt intp0 to intp6 operation enabled key return interrupt p80 to p87 operation enabled bus lines during ad0 to ad7 high impedance external expansion a0 to a19 holds the state before the halt mode is set astm low level wr, rd high level wait holds input status exa holds the state before the halt mode is set 554 chapter 25 standby function user s manual u13570ej3v0ud (b) releasing the halt mode (i) releasing the halt mode by nmi input when the valid edge specified by the external interrupt edge enable registers (egp0, egn0) is input to the nmi input, the idle mode is released. when released from the halt mode, if non-maskable interrupts by the nmi pin input can be acknowledged, execution branches to the nmi interrupt service program. if interrupts cannot be acknowledged (when set in the halt mode by the nmi interrupt service program), execution starts again from the instruction following the instruction that set the halt mode. when interrupts can be acknowledged (by executing the reti instruction), execution branches to the nmi interrupt service program. for details about nmi interrupts acknowledgement, refer to 23.6 non-maskable interrupt acknowl- edge . (ii) releasing the halt mode by a maskable interrupt request an unmasked maskable interrupt request is generated to release the halt mode. when the halt mode is released and the interrupt enable flag (ie) is set to 1, if the interrupt can be acknowledged, execution branches to interrupt service program. when interrupts cannot be acknowledged and when the ie flag is cleared to 0, execution restarts from the instruction following the instruction that set the halt mode. for details about interrupt acknowledgement, refer to 23.7 maskable interrupt acknowledge . (iii) releasing the halt mode by reset input when reset input rises from low to high and the reset is released, the oscillator starts oscillating. the oscillation stops for the reset active period. after the oscillation stabilization time has elapsed, normal operation starts. the difference from the normal reset operation is the data memory saves the contents before setting the halt mode. 555 chapter 25 standby function user s manual u13570ej3v0ud (2) idle mode (a) setting the idle mode and the operating states when the low power consumption mode is set in the idle mode, set 77h in stbc. table 25-10 shows the operating states in the idle mode. table 25-10. operating states in idle mode item operating state clock generator the main system clock stops oscillating. the oscillator of the subsystem clock continues operating. the clock supplied to the cpu and the peripherals stops. cpu operation disabled port (output latch) holds the state before the idle mode is set 16-bit timer/counter operation enabled when the watch timer output is selected as the count clock (select f xt as the count clock of the watch timer.) 8-bit timer/counters 1, 2 operation enabled when ti1 and ti2 are selected as the count clocks 8-bit timer/counters 5, 6 operation enabled when ti5 and ti6 are selected as the count clocks 8-bit timer/counters 7, 8 operation enabled when ti7 and ti8 are selected as the count clocks watch timer operation enabled only when f xt is selected as the count clock watchdog timer operation disabled a/d converter operation disabled d/a converter operation enabled real-time output port operation enabled when an external trigger is used or ti1 and ti2 are selected as the count clocks of the 8-bit timer/counters 1 and 2 serial interface other than operation enabled only when an external input clock is selected as the serial clock i 2 c bus mode i 2 c bus mode operation disabled external interrupt intp0 to intp6 operation enabled key return interrupt p80 to p87 operation enabled bus lines during ad0 to ad7 high impedance external expansion a0 to a7 outputs c0h a8 to a19 high impedance astb high impedance wr, rd high impedance wait holds input status exa high impedance caution in the idle mode, only external interrupts (intp0 to intp6), watch timer interrupt (intwt), and key return interrupts (p80 to p87) can release the idle mode and be acknowledged as interrupt requests. all other interrupt requests are pended, and acknowledged after the idle mode has been released through nmi input, intp0 to intp6 input, intwt, or key return interrupt. 556 chapter 25 standby function user s manual u13570ej3v0ud (b) releasing the idle mode (i) releasing the idle mode by nmi input when the valid edge set in the external interrupt edge enable registers (egp0, egn0) is input to the nmi input, the idle mode is released. when the idle mode is released and non-maskable interrupts by the nmi pin input can be acknowledged, execution branches to the nmi interrupt service program. when interrupts cannot be acknowledged (when set to the idle mode in the nmi interrupt service program), execution restarts from the instruction following the instruction that set the idle mode. when interrupts can be acknowledged (by executing the reti instruction), execution branches to the nmi interrupt service program. for details about nmi interrupts acknowledgement, refer to 23.6 non-maskable interrupt acknowl- edge . (ii) releasing idle mode by intp0 to intp6 inputs, watch timer interrupt, and key return interrupt if interrupt masking is released through intp0 to intp6 input and macro service is disabled, the idle mode is released when a valid edge specified in the external interrupt edge enable registers (egp0, egpn0) is input to intp0 to intp6. if the mask of watch timer interrupt is released and macro service is disabled, an overflow of watch timer occurs and idle mode is released. if key return interrupt masking is released and macro service is disabled, the idle mode is released when a falling edge is input to the port 8 pins (p80 to p87). when the idle mode is released and the interrupt enable flag (ie) is set to 1, if interrupts can be acknowledged, execution branches to interrupt service program. when interrupts cannot be acknowl- edged and when the ie flag is cleared to 0, execution restarts from the instruction following the instruction that set the idle mode. for details about interrupt acknowledgement, refer to 23.7 maskable interrupt acknowledge . (iii) releasing the idle mode by reset input when reset input rises from low to high and the reset is released, the oscillator starts oscillating. the oscillation stops for the reset active period. after the oscillation stabilization time has elapsed, normal operation starts. the difference from the normal reset operation is the data memory saves the contents before setting the idle mode. 557 user s manual u13570ej3v0ud chapter 26 reset function when a low level is input to the reset pin, a system reset is performed. the hardware enters the states listed in figure 26-1. since the oscillation of the main system clock unconditionally stops during the reset period, the current consumption of the entire system can be reduced. when reset input goes from low to high, the reset state is released. after the count time of the timer for oscillation stabilization (84.0 ms: at 12.5 mhz operation), the content of the reset vector table is set in the program counter (pc). execution branches to the address set in the pc, and program execution starts from the branch destination address. therefore, the reset can start from any address. figure 26-1. oscillation of main system clock in reset period main system clock oscillator f clk reset input timer count time for oscillation stabilization time until clock starts oscillating oscillation is unconditionally stopped during the reset period. to prevent erroneous operation caused by noise, a noise eliminator based on an analog delay is incorporated at the reset input pin. 558 chapter 26 reset function user s manual u13570ej3v0ud figure 26-2. accepting reset signal reset input internal reset signal internal clock analog delay analog delay analog delay oscillation stabilizaion time time until clock starts oscillating table 26-1. state after reset for all hardware resets hardware state during reset (reset = l) state after reset (reset = h) main system clock oscillator oscillation stops oscillation starts subsystem clock oscillator not affected by the reset program counter (pc) undefined set a value in the reset vectored table. stack pointer (sp) undefined program status word (psw) initialize to 0000h. internal ram this is undefined. however, when the standby state is released by a reset, the value is saved before setting standby. i/o lines the input and output buffers turn off. high impedance other hardware initialize to the fixed state note . note see after reset in table 3-6 special function register (sfr) list . 559 user s manual u13570ej3v0ud chapter 27 rom correction ( pd784218a, 784218ay subseries only) 27.1 rom correction functions the pd784218a converts part of the program within the mask rom into the program within the peripheral rom. the use of rom correction enables command bugs discovered in the mask rom to be repaired, and change the flow of the program. rom correction can be used in a maximum of four locations within the internal rom (program). cautions 1. note that rom correction cannot perform emulation in the in-circuit emulator (ie-784000-r, ie-784000-r-em). 2. the rom correction function is not provided for the pd784216a, 784216ay subseries. in more detail, the command addresses that require repair from the inactive memory connected to an external microcomputer by a user program and the repair command codes are loaded into the peripheral ram. the above addresses and the internal rom access addresses are compared by the comparator built into the microcomputer during execution of internal rom programs (during command fetch), and internal rom? output data is then converted to call command (callt) codes and output when a match is determined. when the callt command codes are executed as valid commands by the cpu, the callt table is referenced, and the process routine and other peripheral ram are branched. at this point, a callt table is prepared for each repair address for referencing purposes. four repair address can be set for the pd784218a. match-ups with address pointer 0: callt table (0078h) conversion command code: fch match-ups with address pointer 1: callt table (007ah) conversion command code: fdh match-ups with address pointer 2: callt table (007ch) conversion command code: feh match-ups with address pointer 3: callt table (007eh) conversion command code: ffh caution as it is necessary to reserve four locations for the callt tables when the rom correction function is used (0078h, 007ah, 007ch, 007eh), ensure that these are not used for other applications. however, the callt tables can be used if the rom correction function is not being used. the differences between 78k/iv rom correction and 78k/0 rom correction are shown in table 27-1. 560 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud table 27-1. differences between 78k/iv rom correction and 78k/0 rom correction difference 78k/iv 78k/0 generated command codes callt instruction branch instruction to peripheral ram (1-byte instruction: (3-byte instruction) fch, fdh, feh, ffh) change of the stack pointer yes (3-byte save) none address comparison conditions instruction fetch only instruction fetch only correction status flag none yes as there is a possibility that the addresses match owing to an invalid fetch, the status is not necessary jump destination address during callt table fixed address on the peripheral ram correction 0078h, 007ah, 007ch, 007eh 561 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud 27.2 rom correction configuration rom correction is composed of the following hardware. table 27-2. rom correction configuration item configuration register rom correction address register h, l (corah, coral) control register rom correction control register (corc) a rom correction block diagram is shown in figure 27-1, and figure 27-2 shows an example of memory mapping. figure 27-1. rom correction block diagram remark n = 0 to 3, m = 0, 1 internal bus program counter (pc) comparator correction address pointer n rom correction address register (corah, coral) match correction branch process request signal (callt command) rom correction control register (corc) corenn corchm 562 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud figure 27-2. memory mapping example ( pd784218a) vector table area internal rom high-speed internal ram peripheral ram (correction program) sfr internal ram internal rom (reference table 3) (reference table 2) (reference table 1) (reference table 0) callt table area 03ffffh 00ffffh 00ff00h 00feffh 00cd00h 00ccffh 000000h 000000h 00003fh 000040h 00007fh 00cd00h 00fd00h 00feffh 00fcffh 563 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud (1) rom correction address register (corah, coral) the register that sets the start address (correction address) of the command within the mask rom that needs to be repaired. a maximum of four program locations can be repaired with rom correction. first of all, the channel is selected with bit 0 (corch0) and bit 1 (corch1) of the rom correction control register (corc), and the address is then set in the specified channel s address pointer when the address is written in corah and coral. figure 27-3. rom correction address register (corah, coral) format 7 0 address after reset r/w corah ff89h 00h r/w 15 0 address after reset r/w coral ff8ah 0000h r/w (2) comparator rom correction address registers h and l (corah, coral) normally compare the corrected address value with the fetch register value. if any of the rom correction control register (corc) bits between bit 4 and bit 7 (coren0 to 3) are 1 and the correct address matches the fetch address value, a table reference instruction (callt) is issued from the rom correction circuit. 27.3 control register for rom correction rom correction is controlled by the rom correction control register (corc). (1) rom correction control register (corc) the register that controls the issuance of the table reference instruction (callt) when the correct address set in rom correction address registers h and l (corah, coral) match the value of the fetch address. this is composed of a correction enable flag (coren0 to 3) that enables or disables match detection with the comparator, and four-channel correction pointers. corc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets corc to 00h. 564 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud figure 27-4. rom correction control register (corc) format remark n = 0 to 3 corc coren3 76 5 4321 coren2 coren1 coren0 0 0 corch1 0 corch0 address: 0ff88h r/w after reset: 00h symbol corenn 0 1 controls the match detection for the rom correction address register and the fetch address. disabled enabled corch1 corch0 0 0 address pointer channel 0 address pointer channel 1 address pointer channel 2 address pointer channel 3 01 10 11 channel selection 565 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud 27.4 usage of rom correction <1> the correct address and post-correction instruction (correction program) are stored in the microcontroller external inactive memory (eeprom ). <2> a substitute instruction is read from the inactive memory with the use of a serial interface when the initialization program is running after being reset, and this is stored in the peripheral ram and external memory. the correction channel is then selected, the address for the command that requires correction is read and set in the rom correction address registers (corah, coral), and the correction enable flag (coren0 to 3) is set at 1. a maximum of four locations can be set. <3> execute the callt instruction during execution of the corrected address. callt execution program execution (internal rom) correct address executed? no yes <4> callt routine branch when matched with address pointer 0: callt table (0078h) when matched with address pointer 1: callt table (007ah) when matched with address pointer 2: callt table (007ch) when matched with address pointer 3: callt table (007eh) <5> execute substitute instruction <6> add +3 to the stack pointer (sp) <7> restore to any addresses with the branch instruction (br) 566 chapter 27 rom correction ( pd784218a, 784218ay subseries only) user s manual u13570ej3v0ud 27.5 conditions for executing rom correction in order to use the rom correction function, it is necessary for the external environment and program to satisfy the following conditions. (1) external environment must be connected externally to an inactive memory, and be configured to read that data. (2) target program the data setting instruction for corc, corah and coral will be previously annotated in the target program (program stored in the rom). the setup data (the items written in lowercase in the setup example below) must be read from the external inactive memory, and the correct number of required correction pointers must be set. example of four pointer settings mov corc, #00h ; specified channel 0 movw coral, #ch0_datal ; sets the channel 0 matching address mov corah, #ch0_datah ; sets the channel 0 matching address mov corc, #01h ; specified channel 1 movw coral, #ch1_datal ; sets the channel 1 matching address mov corah, #ch1_datah ; sets the channel 1 matching address mov corc, #02h ; specified channel 2 movw coral, #ch2_datal ; sets the channel 2 matching address mov corah, #ch2_datah ; sets the channel 2 matching address mov corc, #03h ; specified channel 3 mov coral, #ch3_datal ; sets the channel 3 matching address mov corah, #ch3_datah ; sets the channel 3 matching address mov corc, #romcor_en ; sets 00h when correction is disabled ; sets f0h when correction is operated br $normal br ! ! c or_addr0 ; specifies the address of the correction program (channel 0) br ! ! c or_addr1 ; specifies the address of the correction program (channel 1) br ! ! c or_addr2 ; specifies the address of the correction program (channel 2) br ! ! c or_addr3 ; specifies the address of the correction program (channel 3) ; (two-level branch) nomal instruction ; next instruction (3) setting the branch instruction in the callt table in the case of the above program, the start address for the br!!cor_addr instruction is specified (cor_addr indicates the address where the correction program is located). the reason for this branching into two levels, the callt instruction and br instruction, is that only the base area can be branched with callt. there is no necessity to branch into two levels when ram is to be allocated to the base area with the location instruction. 567 user s manual u13570ej3v0ud chapter 28 flash memory programming the flash memory can be written when installed in the target system (on board). the dedicated flash programmer (flashpro iii (part no.: fl-pr3, pg-fp3)) is connected to the host machine and target system. writing to the flash memory can be performed using the flash memory write adapter connected to flashpro iii. remark fl-pr3 is a product of naitou densei machida mfg. co., ltd. 28.1 selecting communication protocol flashpro iii writes to flash memory by serial communication. the communication protocol is selected from table 28-1 then writing is performed. the selection of the communication protocol has the format shown in figure 28-1. each communication protocol is selected by the number of v pp pulses shown in table 28-1. table 28-1. communication protocols communication protocol no. of channels pins used no. of v pp pulses 3-wire serial i/o 3 sck0/p27/scl0 note 2 0 so0/p26 si0/p25/sda0 note 2 sck1/asck1/p22 1 so1/txd1/p21 si1/rxd1/p20 sck2/asck2/p72 2 so2/txd2/p71 si2/rxd2/p70 3-wire serial i/o 1 sck0/p27/scl0 note 2 3 (handshake note 3 ) so0/p26 si0/p25/sda0 note 2 p24/buz uart 2 txd1/so1/p21 8 rxd1/si1/p20 txd2/so2/p71 9 rxd2/si2/p70 notes 1. shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. therefore, if the external device connected to each port do not acknowledge the port state immediately after reset, handling such as connecting to v dd via a resistor or connecting to v ss via a resistor is required. 2. pd78f4216ay, 78f4218ay only 3. pd78f4216a, 78f4216ay (other than k, e standards) pd78f4218a, 78f4218ay (all standards) caution select the communication protocol by using the number of v pp pulses given in table 28-1. 568 chapter 28 flash memory programming user s manual u13570ej3v0ud figure 28-1. communication protocol selection format 28.2 flash memory programming functions by transmitting and receiving various commands and data by the selected communication protocol, operations such as writing to the flash memory are performed. table 28-2 shows the major functions. table 28-2. major functions in flash memory programming function description area erase erase the contents of the specified memory area. area blank check checks the erase state of the specified area. data write writes to the flash memory based on the start write address and the number of data written (number of bytes). area verify compares the data input to the contents of the specified memory area. 10 v v pp pulse flash writing mode v dd v ss v dd v ss v pp reset 12 n 569 chapter 28 flash memory programming user s manual u13570ej3v0ud 28.3 connecting flashpro iii the connection between the flashpro iii and the pd78f4218a differs with the communication protocol. figures 28-2 to 28-4 are the connection diagrams in each case. figure 28-2. connection of flashpro iii in 3-wire serial i/o mode (when using 3-wire serial i/o) figure 28-3. connection of flashpro iii in 3-wire serial i/o mode (when using handshake) v pp clk x1 v dd reset sck so si v ss v pp v dd , av dd reset sck0 si0 so0 v ss , av ss flashpro iii pd78f4218a v pp v dd reset sck si v ss v pp clk x1 v dd , av dd reset sck0 so0 hs/v pp2 p24 so si0 v ss , av ss flashpro iii pd78f4218a 570 chapter 28 flash memory programming user s manual u13570ej3v0ud figure 28-4. connection of flashpro iii in uart mode (when using uart) caution connect the v pp pin directly to v ss or pull down. for the pull-down connection, use of resistors with a resistance between 470 ? and 10 k ? is recommended. pd78f4218a v pp v dd reset so si v ss v pp clk x1 v dd , av dd reset rxd1 txd1 v ss , av ss flashpro iii 571 user s manual u13570ej3v0ud chapter 29 instruction operation 29.1 examples (1) operand expression format and description (1/2) expression format description r, r note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7, r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r1 note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7 r2 r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r3 v, u, t, w rp, rp note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5), de(rp6), hl(rp7) rp1 note 2 ax(rp0), bc(rp1), rp2, rp3 rp2 vp(rp4), up(rp5), de(rp6), hl(rp7) rg, rg vvp(rg4), uup(rg5), tde(rg6), whl(rg7) sfr special function register symbol (see table 3-6 special function register (sfr) list ) sfrp special function register symbol (16-bit manipulation register: see table 3-6 special function register (sfr) list ) post note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5)/psw, de(rp6), hl(rp7) multiple descriptions are possible. however, up is restricted to the push/pop instruction, and psw is restricted to the pushu/popu instruction. mem [tde], [whl], [tde+], [whl+], [tde?, [whl?, [vvp], [uup]: register indirect addressing [tde+byte], [whl+byte], [sp+byte], [uup+byte], [vvp+byte]: based addressing imm24[a], imm24[b], imm24[de], imm24[hl]: indexed addressing [tde+a], [tde+b], [tde+c], [whl+a], [whl+b], [whl+c], [vvp+de], [vvp+hl]: based indexed addressing mem1 everything under mem except [whl+] and [whl? mem2 [tde], [whl] mem3 [ax], [bc], [rp2], [rp3], [vvp], [uup], [tde], [whl] notes 1. by setting the rss bit to 1, r4 to r7 can be used as x, a, c, and b. use this function only when 78k/ iii series programs are also used. 2. by setting the rss bit to 1, rp2 and rp3 can be used as ax and bc. use this function only when 78k/iii series programs are also used. 572 chapter 29 instruction operation user s manual u13570ej3v0ud (1) operand expression format and description (2/2) expression format description note saddr, saddr fd20h to ff1fh immediate data or label saddr1 fe00h to feffh immediate data or label saddr2 fd20h to fdffh, ff00h to ff1fh immediate data or label saddrp fd20h to ff1eh immediate data or label (when manipulating 16 bits) saddrp1 fe00h to feffh immediate data or label (when manipulating 16 bits) saddrp2 fd20h to fdffh, ff00h to ff1eh immediate data or label (when manipulating 16 bits) saddrg fd20h to fefdh immediate data or label (when manipulating 24 bits) saddrg1 fe00h to fefdh immediate data or label (when manipulating 24 bits) saddrg2 fd20h to fdffh immediate data or label (when manipulating 24 bits) addr24 0h to ffffffh immediate data or label addr20 0h to fffffh immediate data or label addr16 0h to ffffh immediate data or label addr11 800h to fffh immediate data or label addr8 0fe00h to 0feffh note immediate data or label addr5 40h to 7eh immediate data or label imm24 24-bit immediate data or label word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label n 3-bit immediate data locaddr 00h or 0fh note when 00h is set by the location instruction, these addresses become the addresses shown here. when 0fh is set by the location instruction, the values of the addresses shown here added to f0000h become the addresses. 573 chapter 29 instruction operation user s manual u13570ej3v0ud (2) operand column symbols symbol description + auto increment auto decrement # immediate data ! 16-bit absolute address !! 24-bit/20-bit absolute address $ 8-bit relative address $! 16-bit relative address / bit reversal [ ] indirect addressing [%] 24-bit indirect addressing (3) flag column symbols symbol description (blank) not changed 0 clear to zero. 1 set to one. set or clear based on the result. p operate with the p/v flag as the parity flag. v operate with the p/v flag as the overflow flag. r restore the previously saved value. (4) operation column symbols symbol description jdisp8 two? complement data (8 bits) of the relative address distance between the start address of the next instruction and the branch address jdisp16 two? complement data (16 bits) of the relative address distance between the start address of the next instruction and the branch address pc hw pc bits 16 to 19 pc lw pc bits 0 to 15 574 chapter 29 instruction operation user s manual u13570ej3v0ud (5) number of bytes in instruction that has mem in operand mem mode register indirect addressing based addressing indexed addressing based indexed addressing no. of bytes 1 2 note 35 2 note this becomes a 1-byte instruction only when [tde], [whl], [tde+], [tde?, [whl+], or [whl? is described in mem in the mov instruction. (6) number of bytes in instruction that has saddr, saddrp, r, or rp in operand the number of bytes in an instruction that has saddr, saddrp, r, or rp in the operand is described in two parts divided by a slash (/). the following table shows the number of bytes in each one. description no. of bytes on left side no. of bytes on right side saddr saddr2 saddr1 saddrp saddrp2 saddrp1 rr1 r2 rp rp1 rp2 (7) descriptions of instructions with mem in operand and string instructions the tde, whl, vvp, and uup (24-bit registers) operands can be described by de, hl, vp, and up. however, when de, hl, vp, and up are described, they are handled as tde, whl, vvp, and uup (24-bit registers). 575 chapter 29 instruction operation user s manual u13570ej3v0ud 29.2 list of operations (1) 8-bit data transfer instruction: mov mnemonic operand bytes operation flags s z ac p/v cy mov r, #byte 2/3 r byte saddr, #byte 3/4 (saddr) byte sfr, #byte 3 sfr byte !addr16,, #byte 5 (saddr16) byte !!addr24, #byte 6 (addr24) byte r, r' 2/3 r r' a, r 1/2 a r a, saddr2 2 a (saddr2) r, saddr 3 r (saddr) saddr2, a 2 (saddr2) a saddr, r 3 (saddr) r a, sfr 2 a sfr r, sfr 3 r sfr sfr, a 2 sfr a sfr, r 3 sfr r saddr, saddr' 4 (saddr) (saddr') r, !addr16 4 r (addr16) !addr16, r 4 (addr16) r r, !!addr24 5 r (addr24) !!addr24, r 5 (addr24) r a, [saddrp] 2/3 a ((saddrp)) a, [%saddrg] 3/4 a ((saddrg)) a, mem 1-5 a (mem) [saddrp], a 2/3 ((saddrp)) a [%saddrg], a 3/4 ((saddrg)) a mem, a 1-5 (mem) a pswl #byte 3 psw l byte pswh #byte 3 psw h byte pswl, a 2 psw l a pswh, a 2 psw h a a, pswl 2 a psw l a, pswh 2 a psw h r3, #byte 3 r3 byte a, r3 2 a r3 r3, a 2 r3 a 576 chapter 29 instruction operation user s manual u13570ej3v0ud (2) 16-bit data transfer instruction: movw mnemonic operand bytes operation flags s z ac p/v cy movw rp, #word 3 rp word saddrp, #word 4/5 (saddrp) word sfrp, #word 4 sfrp word !addr16, #word 6 (addr16) word !!addr24, #word 7 (addr24) word rp, rp' 2 rp rp' ax, saddrp2 2 ax (saddrp2) rp, saddrp 3 rp (saddrp) saddrp2, ax 2 (saddrp2) ax saddrp, rp 3 (saddrp) rp ax, sfrp 2 ax sfrp rp, sfrp 3 rp sfrp sfrp, ax 2 sfrp ax sfrp, rp 3 sfrp rp saddrp, saddrp' 4 (saddrp) (saddrp') rp, !addr16 4 rp (addr16) !addr16, rp 4 (addr16) rp rp, !!addr24 5 rp (addr24) !!addr24, rp 5 (addr24) rp ax, [saddrp] 3/4 ax ((saddrp)) ax, [%saddrg] 3/4 ax ((saddrg)) ax, mem 2-5 ax (mem) [saddrp], ax 3/4 ((saddrp)) ax [%saddrg], ax 3/4 ((saddrg)) ax mem, ax 2-5 (mem) ax 577 chapter 29 instruction operation user s manual u13570ej3v0ud (3) 24-bit data transfer instruction: movg mnemonic operand bytes operation flags s z ac p/v cy movg rg, #imm24 5 rg imm24 rg, rg' 2 rg rg' rg, !!addr24 5 rg (addr24) !!addr24, rg 5 (addr24) rg rg, saddrg 3 rg (saddrg) saddrg, rg 3 (saddrg) rg whl, [%saddrg] 3/4 whl ((saddrg)) [%saddrg], whl 3/4 ((saddrg)) whl whl, mem1 2-5 whl (mem1) mem1, whl 2-5 (mem1) whl (4) 8-bit data exchange instruction: xch mnemonic operand bytes operation flags s z ac p/v cy xch r, r' 2/3 r ? r' a, r 1/2 a ? r a, saddr2 2 a ? (saddr2) r, saddr 3 r ? (saddr) r, sfr 3 r ? sfr saddr, saddr' 4 (saddr) ? (saddr') r, !addr16 4 r ? (addr16) r, !!addr24 5 r ? (addr24) a, [saddrp] 2/3 a ? ((saddrp)) a, [%saddrg] 3/4 a ? ((saddrg)) a, mem 2-5 a ? (mem) 578 chapter 29 instruction operation user s manual u13570ej3v0ud (5) 16-bit data exchange instruction: xchw mnemonic operand bytes operation flags s z ac p/v cy xchw rp, rp' 2 rp ? rp' ax, saddrp2 2 ax ? (saddrp2) rp, saddrp 3 rp ? (saddrp) rp, sfrp 3 rp ? sfrp ax, [saddrp] 3/4 ax ? ((saddrp)) ax, [%saddrg] 3/4 ax ? ((saddrg)) ax, !addr16 4 ax ? (addr16) ax, !!addr24 5 ax ? (addr24) saddrp, saddrp' 4 (saddrp) ? (saddrp') ax, mem 2-5 ax ? (mem) (6) 8-bit arithmetic instructions: add, addc, sub, subc, cmp, and, or, xor mnemonic operand bytes operation flags s z ac p/v cy add a, #byte 2 a, cy a + byte v r, #byte 3 r, cy r + byte v saddr, #byte 3/4 (saddr), cy (saddr) + byte v sfr, #byte 4 sfr, cy sfr + byte v r, r' 2/3 r, cy r + r' v a, saddr2 2 a, cy a + (saddr2) v r, saddr 3 r, cy r + (saddr) v saddr, r 3 (saddr), cy (saddr) + r v r, sfr 3 r, cy r + sfr v sfr, r 3 sfr, cy sfr + r v saddr, saddr' 4 (saddr), cy (saddr) + (saddr') v a, [saddrp] 3/4 a, cy a + ((saddrp)) v a, [%saddrg] 3/4 a, cy a + ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a v a, !addr16 4 a, cy a + (addr16) v a, !!addr24 5 a, cy a + (addr24) v !addr16, a 4 (addr16), cy (addr16) + a v !!addr24, a 5 (addr24), cy (addr24) + a v a, mem 2-5 a, cy a + (mem) v mem, a 2-5 (mem), cy (mem) + a v 579 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy addc a, #byte 2 a, cy a + byte + cy v r, #byte 3 r, cy r + byte + cy v saddr, #byte 3/4 (saddr), cy (saddr) + byte + cy v sfr, #byte 4 sfr, cy sfr + byte + cy v r, r' 2/3 r, cy r + r' + cy v a, saddr2 2 a, cy a + (saddr2) + cy v r, saddr 3 r, cy r + (saddr) + cy v saddr, r 3 (saddr), cy (saddr) + r + cy v r, sfr 3 r, cy r + sfr + cy v sfr, r 3 sfr, cy sfr + r + cy v saddr, saddr' 4 (saddr), cy (saddr) + (saddr') + cy v a, [saddrp] 3/4 a, cy a + ((saddrp)) + cy v a, [%saddrg] 3/4 a, cy a + ((saddrg) + cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a + cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrp)) + a + cy v a, !addr16 4 a, cy a + (addr16) + cy v a, !!addr24 5 a, cy a + (addr24) +cy v !addr16, a 4 (addr16), cy (addr16) + a + cy v !!addr24, a 5 (addr24), cy (addr24) + a + cy v a, mem 2-5 a, cy a + (mem) + cy v mem, a 2-5 (mem), cy (mem) + a + cy v 580 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy sub a, #byte 2 a, cy a ?byte v r, #byte 3 r, cy r ?byte v saddr, #byte 3/4 (saddr), cy (saddr) ?byte v sfr, #byte 4 sfr, cy sfr ?byte v r, r' 2/3 r, cy r ?r' v a, saddr2 2 a, cy a ?(saddr2) v r, saddr 3 r, cy r ?(saddr) v saddr, r 3 (saddr), cy (saddr) ?r v r, sfr 3 r, cy r ?sfr v sfr, r 3 sfr, cy sfr ?r v saddr, saddr' 4 (saddr), cy (saddr) ?(saddr') v a, [saddrp] 3/4 a, cy a ?((saddrp)) v a, [%saddrg] 3/4 a, cy a ?((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) ?a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) ?a v a, !addr16 4 a, cy a ?(addr16) v a, !!addr24 5 a, cy a ?(addr24) v !addr16, a 4 (addr16), cy (addr16) ?a v !!addr24, a 5 (addr24), cy (addr24) ?a v a, mem 2-5 a, cy a ?(mem) v mem, a 2-5 (mem), cy (mem) ?a v 581 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy subc a, #byte 2 a, cy a ?byte ?cy v r, #byte 3 r, cy r ?byte ?cy v saddr, #byte 3/4 (saddr), cy (saddr) ?byte ?cy v sfr, #byte 4 sfr, cy sfr ?byte ?cy v r, r' 2/3 r, cy r ?r' ?cy v a, saddr2 2 a, cy a ?(saddr2) ?cy v r, saddr 3 r, cy r ?(saddr) ?cy v saddr, r 3 (saddr), cy (saddr) ?r ?cy v r, sfr 3 r, cy r ?sfr ?cy v sfr, r 3 sfr, cy sfr ?r ?cy v saddr, saddr' 4 (saddr), cy (saddr) ?(saddr') ?cy v a, [saddrp] 3/4 a, cy a ?((saddrp)) ?cy v a, [%saddrg] 3/4 a, cy a ?((saddrg)) ?cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) ?a ?cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) ?a ?cy v a, !addr16 4 a, cy a ?(addr16) ?cy v a, !!addr24 5 a, cy a ?(addr24) ?cy v !addr16, a 4 (addr16), cy (addr16) ?a ?cy v !!addr24, a 5 (addr24), cy (addr24) ?a ?cy v a, mem 2-5 a, cy a ?(mem) ?cy v mem, a 2-5 (mem), cy (mem) ?a ?cy v 582 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy cmp a, #byte 2 a ?byte v r, #byte 3 r ?byte v saddr, #byte 3/4 (saddr) ?byte v sfr, #byte 4 sfr ?byte v r, r' 2/3 r ?r' v a, saddr2 2 a ?(saddr2) v r, saddr 3 r ?(saddr) v saddr, r 3 (saddr) ?r v r, sfr 3 r ?sfr v sfr, r 3 sfr ?r v saddr, saddr' 4 (saddr) ?(saddr') v a, [saddrp] 3/4 a ?((saddrp)) v a, [%saddrg] 3/4 a ?((saddrg)) v [saddrp], a 3/4 ((saddrp)) ?a v [%saddrg], a 3/4 ((saddrg)) ?a v a, !addr16 4 a ?(addr16) v a, !!addr24 5 a ?(addr24) v !addr16, a 4 (addr16) ?a v !!addr24, a 5 (addr24) ?a v a, mem 2-5 a ?(mem) v mem, a 2-5 (mem) ?a v 583 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy and a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r' 2/3 r r r' p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr' 4 (saddr) (saddr) (saddr') p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (aaddr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p 584 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy or a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r' 2/3 r r r' p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr' 4 (saddr) (saddr) (saddr') p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (saddr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (aaddr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p 585 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy xor a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r' 2/3 r r r' p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr' 4 (saddr) (saddr) (saddr') p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (aaddr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p 586 chapter 29 instruction operation user s manual u13570ej3v0ud (7) 16-bit arithmetic instructions: addw, subw, cmpw mnemonic operand bytes operation flags s z ac p/v cy addw ax, #word 3 ax, cy ax + word v rp, #word 4 rp, cy rp + word v rp, rp' 2 rp, cy rp + rp' v ax, saddrp2 2 ax, cy ax + (saddrp2) v rp, saddrp 3 rp, cy rp + (saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) + rp v rp, sfrp 3 rp, cy rp + sfrp v sfrp, rp 3 sfrp, cy sfrp + rp v saddrp, #word 4/5 (saddrp), cy (saddrp) + word v sfrp, #word 5 sfrp, cy sfrp + word v saddrp, saddrp' 4 (saddrp), cy (saddrp) + (saddrp') v subw ax, #word 3 ax, cy ax ?word v rp, #word 4 rp, cy rp ?word v rp, rp' 2 rp, cy rp ?rp' v ax, saddrp2 2 ax, cy ax ?(saddrp2) v rp, saddrp 3 rp, cy rp ?(saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) ?rp v rp, sfrp 3 rp, cy rp ?sfrp v sfrp, rp 3 sfrp, cy sfrp ?rp v saddrp, #word 4/5 (saddrp), cy (saddrp) ?word v sfrp, #word 5 sfrp, cy sfrp ?word v saddrp, saddrp' 4 (saddrp), cy (saddrp) ?(saddrp') v cmpw ax, #word 3 ax ?word v rp, #word 4 rp ?word v rp, rp' 2 rp ?rp' v ax, saddrp2 2 ax ?(saddrp2) v rp, saddrp 3 rp ?(saddrp) v saddrp, rp 3 (saddrp) ?rp v rp, sfrp 3 rp ?sfrp v sfrp, rp 3 sfrp ?rp v saddrp, #word 4/5 (saddrp) ?word v sfrp, #word 5 sfrp ?word v saddrp, saddrp' 4 (saddrp) ?(saddrp') v 587 chapter 29 instruction operation user s manual u13570ej3v0ud (8) 24-bit arithmetic instructions: addg, subg mnemonic operand bytes operation flags s z ac p/v cy addg rg, rg' 2 rg, cy rg + rg' v rg, #imm24 5 rg, cy rg + imm24 v whl, saddrg 3 whl, cy whl + (saddrg) v subg rg, rg' 2 rg, cy rg ?rg' v rg, #imm24 5 rg, cy rg ?imm24 v whl, saddrg 3 whl, cy whl ?(saddrg) v (9) multiply/divide instructions: mulu, muluw, mulw, divuw, divux mnemonic operand bytes operation flags s z ac p/v cy mulu r 2/3 ax axr muluw rp 2 ax (high order), rp (low order) axxrp mulw rp 2 ax (high order), rp (low order) axxrp divuw r 2/3 ax (quotient), r (remainder) ax r note 1 divux rp 2 axde (quotient), rp (remainder) axde rp note 2 notes 1. when r = 0, r x, ax ffffh 2. when rp = 0, rp de, axde ffffffffh (10) special arithmetic instructions: macw, macsw, sacw mnemonic operand bytes operation flags s z ac p/v cy macw byte 3 axde (b) x (c) + axde, b b + 2, v c c + 2, byte byte ?1 end if (byte = 0 or p/v = 1) macsw byte 3 axde (b) x (c) + axde, b b + 2, v c c + 2, byte byte ?1 if byte = 0 then end if p/v = 1 then if overflow axde 7fffffffh, end if underflow axde 80000000h, end sacw [tde+], [whl+] 4 ax | (tde) ?(whl) | + ax, v tde tde + 2, whl whl + 2 c c ?1 end if (c = 0 or cy = 1) 588 chapter 29 instruction operation user s manual u13570ej3v0ud (11) increment and decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operand bytes operation flags s z ac p/v cy inc r 1/2 r r + 1 v saddr 2/3 (saddr) (saddr) + 1 v dec r 1/2 r r ?1 v saddr 2/3 (saddr) (saddr) ?1 v incw rp 2/1 rp rp + 1 saddrp 3/4 (saddrp) (saddrp) + 1 decw rp 2/1 rp rp ?1 saddrp 3/4 (saddrp) (saddrp) ?1 incg rg 2 rg rg + 1 decg rg 2 rg rg ?1 (12) decimal adjust instructions: adjba, adjbs, cvtbw mnemonic operand bytes operation flags s z ac p/v cy adjba 2 decimal adjust accumulator after addition p adjbs 2 decimal adjust accumulator after subtract p cvtbw 1 x a, a 00h if a 7 = 0 x a, a ffh if a 7 = 1 589 chapter 29 instruction operation user s manual u13570ej3v0ud (13) shift and rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operand bytes operation flags s z ac p/v cy ror r, n 2/3 (cy, r 7 r 0 , r m? r m ) n n = 0 to 7 p rol r, n 2/3 (cy, r 0 r 7 , r m+1 r m ) n n = 0 to 7 p rorc r, n 2/3 (cy r 0 , r 7 cy, r m? r m ) n n = 0 to 7 p rolc r, n 2/3 (cy r 7 , r 0 cy, r m+1 r m ) n n = 0 to 7 p shr r, n 2/3 (cy r 0 , r 7 0, r m? r m ) n n = 0 to 7 0p shl r, n 2/3 (cy r 7 , r 0 0, r m+1 r m ) n n = 0 to 7 0p shrw rp, n 2 (cy rp 0 , rp 15 0, rp m? rp m ) n n = 0 to 7 0p shlw rp, n 2 (cy rp 15 , rp 0 0, rp m+1 rp m ) n n = 0 to 7 0p ror4 mem3 2 a 3? (mem3) 3? , (mem3) 7? a 3? , (mem3) 3? (mem3) 7? rol4 mem3 2 a 3? (mem3) 7? , (mem3) 3? a 3? , (mem3) 7? (mem3) 3? (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 mnemonic operand bytes operation flags s z ac p/v cy mov1 cy, saddr.bit 3/4 cy (saddr.bit) cy, sfr.bit 3 cy sfr.bit cy, x.bit 2 cy x.bit cy, a.bit 2 cy a.bit cy, pswl.bit 2 cy psw l .bit cy, pswh.bit 2 cy psw h .bit cy, !addr16.bit 5 cy !addr16.bit cy, !!addr24.bit 2 cy !!addr24.bit cy, mem2.bit 2 cy mem2.bit saddr.bit, cy 3/4 (saddr.bit) cy sfr.bit, cy 3 sfr.bit cy x.bit, cy 2 x.bit cy a.bit, cy 2 a.bit cy pswl.bit, cy 2 psw l .bit cy pswh.bit, cy 2 psw h .bit cy !addr16.bit, cy 5 !addr16.bit cy !!addr24.bit, cy 6 !!addr24.bit cy mem2.bit, cy 2 mem2.bit cy 590 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy and1 cy, saddr.bit 3/4 cy cy (saddr.bit) cy, /saddr.bit 3/4 cy cy (saddr.bit) cy, sfr.bit 3 cy cy sfr.bit cy, /sfr.bit 3 cy cy sfr.bit cy, x.bit 2 cy cy x.bit cy, /x.bit 2 cy cy x.bit cy, a.bit 2 cy cy a.bit cy, /a.bit 2 cy cy a.bit cy, pswl.bit 2 cy cy psw l .bit cy, /pswl.bit 2 cy cy psw l .bit cy, pswh.bit 2 cy cy psw h .bit cy, /pswh.bit 2 cy cy psw h .bit cy, !addr16.bit 5 cy cy !addr16.bit cy, /!addr16.bit 5 cy cy !addr16.bit cy, !!addr24.bit 2 cy cy !!addr24.bit cy, /!!addr24.bit 6 cy cy !!addr24.bit cy, mem2.bit 2 cy cy mem2.bit cy, /mem2.bit 2 cy cy mem2.bit or1 cy, saddr.bit 3/4 cy cy (saddr.bit) cy, /saddr.bit 3/4 cy cy (saddr.bit) cy, sfr.bit 3 cy cy sfr.bit cy, /sfr.bit 3 cy cy sfr.bit cy, x.bit 2 cy cy x.bit cy, /x.bit 2 cy cy x.bit cy, a.bit 2 cy cy a.bit cy, /a.bit 2 cy cy a.bit cy, pswl.bit 2 cy cy psw l .bit cy, /pswl.bit 2 cy cy psw l .bit cy, pswh.bit 2 cy cy psw h .bit cy, /pswh.bit 2 cy cy psw h .bit cy, !addr16.bit 5 cy cy !addr16.bit cy, /!addr16.bit 5 cy cy !addr16.bit cy, !!addr24.bit 2 cy cy !!addr24.bit cy, /!!addr24.bit 6 cy cy !!addr24.bit cy, mem2.bit 2 cy cy mem2.bit cy, /mem2.bit 2 cy cy mem2.bit 591 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy xor1 cy, saddr.bit 3/4 cy cy (saddr.bit) cy, sfr.bit 3 cy cy sfr.bit cy, x.bit 2 cy cy x.bit cy, a.bit 2 cy cy a.bit cy, pswl.bit 2 cy cy psw l .bit cy, pswh.bit 2 cy cy psw h .bit cy, !addr16.bit 5 cy cy !addr16.bit cy, !!addr24.bit 2 cy cy !!addr24.bit cy, mem2.bit 2 cy cy mem2.bit not1 saddr.bit 3/4 (saddr.bit) (saddr.bit) sfr.bit 3 sfr.bit sfr.bit x.bit 2 x.bit x.bit a.bit 2 a.bit a.bit pswl.bit 2 pswl.bit psw l .bit pswh.bit 2 pswh.bit psw h .bit !addr16.bit 5 !addr16.bit !addr16.bit !!addr24.bit 2 !!addr24.bit !!addr24.bit mem2.bit 2 mem2.bit mem2.bit cy 1 cy cy set1 saddr.bit 2/3 (saddr.bit) 1 sfr.bit 3 sfr.bit 1 x.bit 2 x.bit 1 a.bit 2 a.bit 1 pswl.bit 2 psw l .bit 1 pswh.bit 2 psw h .bit 1 !addr16.bit 5 !addr16.bit 1 !!addr24.bit 2 !!addr24.bit 1 mem2.bit 2 mem2.bit 1 cy 1 cy 11 clr1 saddr.bit 2/3 (saddr.bit) 0 sfr.bit 3 sfr.bit 0 x.bit 2 x.bit 0 a.bit 2 a.bit 0 pswl.bit 2 psw l .bit 0 pswh.bit 2 psw h .bit 0 !addr16.bit 5 !addr16.bit 0 !!addr24.bit 2 !!addr24.bit 0 mem2.bit 2 mem2.bit 0 cy 1 cy 00 592 chapter 29 instruction operation user s manual u13570ej3v0ud (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operand bytes operation flags s z ac p/v cy push psw 1 (sp ?2) psw, sp sp ?2 sfrp 3 (sp ?2) sfrp, sp sp ?2 sfr 3 (sp ?1) sfr, sp sp ?1 post 2 {(sp ?2) post, sp sp ?2} m note rg 2 (sp ?3) rg, sp sp ?3 pushu post 2 {(uup ?2) post, uup uup ?2} m note pop psw 1 psw (sp), sp sp + 2 rrrrr sfrp 3 sfrp (sp), sp sp + 2 sfr 3 sfr (sp), sp sp + 1 post 2 {post (sp), sp sp + 2} m note rg 2 rg (sp), sp sp + 3 popu post 2 {post (uup), uup uup + 2} m note movg sp, #imm24 5 sp imm24 sp, whl 2 sp whl whl, sp 2 whl sp addwg sp, #word 4 sp sp + word subwg sp, #word 4 sp sp ?word incg sp 2 sp sp + 1 decg sp 2 sp sp ?1 note m is the number of registers specified by post. 593 chapter 29 instruction operation user s manual u13570ej3v0ud (16) call return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operand bytes operation flags s z ac p/v cy call !addr16 3 (sp ?3) (pc + 3), sp sp ?3, pc hw 0, pc lw addr16 !!addr20 4 (sp ?3) (pc + 4), sp sp ?3, pc addr20 rp 2 (sp ?3) (pc + 2), sp sp ?3, pc hw 0, pc lw rp rg 2 (sp ?3) (pc + 2), sp sp ?3, pc rg [rp] 2 (sp ?3) (pc + 2), sp sp ?3, pc hw 0, pc lw (rp) [rg] 2 (sp ?3) (pc + 2), sp sp ?3, pc (rg) $!addr20 3 (sp ?3) (pc + 3), sp sp ?3, pc pc + 3 + jdisp16 callf !addr11 2 (sp ?3) (pc + 2), sp sp ?3 pc 19?2 0, pc 11 1, pc 10? addr11 callt [addr5] 1 (sp ?3) (pc + 1), sp sp ?3 pc hw 0, pc cw (addr5) brk 1 (sp ?2) psw, (sp ?1) 0? , (pc + 1) hw , (sp ?4) (pc + 1) lw , sp sp ?4 pc hw 0, pc lw (003eh) brkcs rbn 2 pc lw rp2, rp3 psw, rbs2 ?0 n, rss 0, ie 0, rp3 8?1 pc hw , pc hw 0 ret 1 pc (sp), sp sp + 3 reti 1 pc lw (sp), pc hw (sp + 3) 0? , rrrrr psw (sp + 2), sp sp + 4 the flag with the highest priority that is set to 1 in the ispr is cleared to 0. retb 1 pc lw (sp), pc hw (sp + 3) 0? , rrrrr psw (sp + 2), sp sp + 4 retcs !addr16 3 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8?1 the flag with the highest priority that is set to 1 in the ispr is cleared to 0. retcsb !addr16 4 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8?1 594 chapter 29 instruction operation user s manual u13570ej3v0ud (17) unconditional branch instruction: br mnemonic operand bytes operation flags s z ac p/v cy br !addr16 3 pc hw 0, pc lw addr16 !!addr20 4 pc addr20 rp 2 pc hw 0, pc lw rp rg 2 pc rg [rp] 2 pc hw 0, pc lw (rp) [rg] 2 pc (rg) $addr20 2 pc pc + 2 + jdisp8 $!addr20 3 pc pc + 3 + jdisp16 595 chapter 29 instruction operation user s manual u13570ej3v0ud (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz mnemonic operand bytes operation flags s z ac p/v cy bnz $addr20 2 pc pc + 2 + jdisp8 if z = 0 bne bz $addr20 2 pc pc + 2 + jdisp8 if z = 1 be bnc $addr20 2 pc pc + 2 + jdisp8 if cy = 0 bnl bc $addr20 2 pc pc + 2 + jdisp8 if cy = 1 bl bnv $addr20 2 pc pc + 2 + jdisp8 if p/v = 0 bpo bv $addr20 2 pc pc + 2 + jdisp8 if p/v = 1 bpe bp $addr20 2 pc pc + 2 + jdisp8 if s = 0 bn $addr20 2 pc pc + 2 + jdisp8 if s = 1 blt $addr20 3 pc pc + 3 + jdisp8 if p/v s = 1 bge $addr20 3 pc pc + 3 + jidsp8 if p/v s = 0 ble $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 1 bgt $addr20 3 pc pc + 3 + jidsp8 if (p/v s) z = 0 bnh $addr20 3 pc pc + 3 + jdisp8 if z cy = 1 bh $addr20 3 pc pc + 3 + jidsp8 if z cy = 0 bf saddr.bit, $addr20 4/5 pc pc + 4 note + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr20 4 pc pc + 4 + jdisp8 if sfr.bit = 0 x.bit, $addr20 3 pc pc + 3 + jdisp8 if x.bit = 0 a.bit, $addr20 3 pc pc + 3 + jdisp8 if a.bit = 0 pswl.bit, $addr20 3 pc pc + 3 + jdisp8 if psw l .bit = 0 pswh.bit, $addr20 3 pc pc + 3 + jdisp8 if psw h .bit = 0 !addr16.bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16.bit = 0 !!addr24.bit, $addr20 3 pc pc + 3 + jdisp8 if !!addr24.bit = 0 mem2.bit, $addr20 3 pc pc + 3 + jdisp8 if mem2.bit = 0 note this is used when the number of bytes is four. when five, it becomes pc pc + 5 + jdisp8. 596 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy bt saddr.bit, $addr20 3/4 pc pc + 3 note 1 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr20 4 pc pc + 4 + jdisp8 if sfr.bit = 1 x.bit, $addr20 3 pc pc + 3 + jdisp8 if x.bit = 1 a.bit, $addr20 3 pc pc + 3 + jdisp8 if a.bit = 1 pswl.bit, $addr20 3 pc pc + 3 + jdisp8 if psw l .bit = 1 pswh.bit, $addr20 3 pc pc + 3 + jdisp8 if psw h .bit = 1 !addr16.bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16.bit = 1 !!addr24.bit, $addr20 3 pc pc + 3 + jdisp8 if !!addr24.bit = 1 mem2.bit, $addr20 3 pc pc + 3 + jdisp8 if mem2.bit = 1 btclr saddr.bit, $addr20 4/5 {pc pc + 4 note 2 + jdisp8, (saddr.bit) 0} if (saddr.bit = 1) sfr.bit, $addr20 4 {pc pc + 4 + jdisp8, sfr.bit 0} if sfr. bit = 1 x.bit, $addr20 3 {pc pc + 3 + jdisp8, x.bit 0} if x.bit = 1 a.bit, $addr20 3 {pc pc + 3 + jdisp8, a.bit 0} if a.bit = 1 pswl.bit, $addr20 3 {pc pc + 3 + jdisp8, psw l .bit 0} if psw l .bit = 1 pswh.bit, $addr20 3 {pc pc + 3 + jdisp8, psw h .bit 0} if psw h .bit = 1 !addr16.bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16.bit 0} if !addr16.bit = 1 !!addr24.bit, $addr20 3 {pc pc + 3 + jdisp8, !!addr24.bit 0} if !!addr24.bit = 1 mem2.bit, $addr20 3 {pc pc + 3 + jdisp8, mem2.bit 0} if mem2.bit = 1 notes 1. this is used when the number of bytes is three. when four, it becomes pc pc + 4 + jdisp8. 2. this is used when the number of bytes is four. when five, it becomes pc pc + 5 + jdisp8. 597 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy bfset saddr.bit, $addr20 4/5 {pc pc + 4 note 2 + jdisp8, (saddr.bit) 1} if (saddr.bit = 0) sfr.bit, $addr20 4 {pc pc + 4 + jdisp8, sfr.bit 1} if sfr. bit = 0 x.bit, $addr20 3 {pc pc + 3 + jdisp8, x.bit 1} if x.bit = 0 a.bit, $addr20 3 {pc pc + 3 + jdisp8, a.bit 1} if a.bit = 0 pswl.bit, $addr20 3 {pc pc + 3 + jdisp8, psw l .bit 1} if psw l .bit = 0 pswh.bit, $addr20 3 {pc pc + 3 + jdisp8, psw h .bit 1} if psw h .bit = 0 !addr16.bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16.bit 1} if !addr16.bit = 0 !!addr24.bit, $addr20 3 {pc pc + 3 + jdisp8, !!addr24.bit 1} if !!addr24.bit = 0 mem2.bit, $addr20 3 {pc pc + 3 + jdisp8, mem2.bit 1} if mem2.bit = 0 dbnz b, $addr20 2 b b ?1, pc pc + 2 + jdisp8 if b 0 c, $addr20 2 c c ?1, pc pc + 2 + jdisp8 if c 0 saddr, $addr20 3/4 (saddr) (saddr) ?1, pc pc + 3 note 1 + jdisp8 if (saddr) 0 notes 1. this is used when the number of bytes is three. when four, it becomes pc pc + 4 + jdisp8. 2. this is used when the number of bytes is four. when five, it becomes pc pc + 5 + jdisp8. (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operand bytes operation flags s z ac p/v cy mov stbc, #byte 4 stbc byte wdm, #byte 4 wdm byte location locaddr 4 specification of the high-order word of the location address of the sfr and internal data area sel rbn 2 rss 0, rbs2 ?0 n rbn, alt 2 rss 1, rbs2 ?0 n swrs 2 rss rss nop 1 no operation ei 1 ie 1 (enable interrupt) di 1 ie 0 (disable interrupt) 598 chapter 29 instruction operation user s manual u13570ej3v0ud (20) string instructions: movtblw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, cmpbknc mnemonic operand bytes operation flags s z ac p/v cy movtblw !addr8, byte 4 (addr8 + 2) (addr8), byte byte ?1, addr8 addr8 ?2 end if byte = 0 movm [tde+], a 2 (tde) a, tde tde + 1, c c ?1 end if c = 0 [tde?, a 2 (tde) a, tde tde ?1, c c ?1 end if c = 0 xchm [tde+], a 2 (tde) ? a, tde tde + 1, c c ?1 end if c = 0 [tde?, a 2 (tde) ? a, tde tde ?1, c c ?1 end if c = 0 movbk [tde+], [whl+] 2 (tde) (whl), tde tde + 1, whl whl + 1, c c ? end if c = 0 [tde?, [whl? 2 (tde) (whl), tde tde ?1, whl whl ?1, c c ? end if c = 0 xchbk [tde+], [whl+] 2 (tde) ? (whl), tde tde + 1, whl whl + 1, c c ? end if c = 0 [tde?, [whl? 2 (tde) ? (whl), tde tde ?1, whl whl ?1, c c ? end if c = 0 cmpme [tde+], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or z = 0 v [tde?, a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or z = 0 v cmpmne [tde+], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or z = 1 v [tde?, a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or z = 1 v cmpmc [tde+], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or cy = 0 v [tde?, a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or cy = 0 v cmpmnc [tde+], a 2 (tde) ?a, tde tde + 1, c c ?1 end if c = 0 or cy = 1 v [tde?, a 2 (tde) ?a, tde tde ?1, c c ?1 end if c = 0 or cy = 1 v cmpbke [tde+], [whl+] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ? end if c = 0 or z = 0 [tde?, [whl? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ? end if c = 0 or z = 0 599 chapter 29 instruction operation user s manual u13570ej3v0ud mnemonic operand bytes operation flags s z ac p/v cy cmpbkne [tde+], [whl+] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ? end if c = 0 or z = 1 [tde?, [whl? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ? end if c = 0 or z = 1 cmpbkc [tde+], [whl+] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ? end if c = 0 or cy = 0 [tde?, [whl? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ? end if c = 0 or cy = 0 cmpbknc [tde+], [whl+] 2 (tde) ?(whl), tde tde + 1, v whl whl + 1, c c ? end if c = 0 or cy = 1 [tde?, [whl? 2 (tde) ?(whl), tde tde ?1, v whl whl ?1, c c ? end if c = 0 or cy = 1 600 chapter 29 instruction operation user s manual u13570ej3v0ud 29.3 lists of addressing instructions (1) 8-bit instructions (combinations expressed by writing a for r are shown in parentheses) mov, xch, add, addc, sub, subc, and or xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc table 29-1. 8-bit addressing instructions (1/2) 2nd operand r saddr # byte a sfr 1st operand r saddr a (mov) (mov) mov (mov) note 6 mov add note 1 (xch) xch (xch) note 6 (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 r mov (mov) mov mov mov add note 1 (xch) xch xch xch (add) note 1 add note 1 add note 1 add note 1 saddr mov (mov) note 6 mov mov add note 1 (add) note 1 add note 1 xch add note 1 sfr mov mov mov add note 1 (add) note 1 add note 1 !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 r3 mov mov pswl pswh b, c stbc, wdm mov [tde +] (mov) [tde ? (add) note 1 movm note 4 (see the following page for the explanation of note .) 601 chapter 29 instruction operation user s manual u13570ej3v0ud table 29-1. 8-bit addressing instructions (2/2) 2nd operand !addr16 mem r3 [whl +] [saddrp] pswl n none note 2 1st operand !!addr24 [%saddrg] pswh [whl ? a (mov) mov mov (mov) (xch) xch (xch) add note 1 add note 1 (add) note 1 r mov ror note 3 mulu xch divuw inc dec saddr inc dec dbnz sfr push pop !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ror4 rol4 r3 pswl pswh b, c dbnz stbc, wdm [tde +] movbk note 5 [tde ? notes 1. addc, sub, subc, and, or, xor and cmp are the same as add. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. rol, rorc, rolc, shr and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc and cmpbkc are the same as movbk. 6. if saddr is saddr2 in this combination, there is a short code length instruction. 602 chapter 29 instruction operation user s manual u13570ej3v0ud (2) 16-bit instructions (combinations expressed by writing ax for rp are shown in parentheses) movm, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 29-2. 16-bit addressing instructions (1/2) 2nd operand r saddr # word a sfrp 1st operand ax (movw) (movw) (movw) (movw) note 3 movw addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw addw note 1 (xchw) xchw xchw xchw (addw) note 1 addw note 1 addw note 1 addw note 1 saddrp movw (movw) note 3 movw movw addw note 1 (addw) note 1 addw note 1 xchw addw note 1 sfrp movw movw movw addw note 1 (addw) note 1 addw note 1 !addr16 movw (movw) movw !!addr24 mem movw [saddrp] [%saddrg] psw sp addwg subwg post [tde +] (movw) byte (see the following page for the explanation of note .) 603 chapter 29 instruction operation user s manual u13570ej3v0ud table 29-2. 16-bit addressing instructions (2/2) 2nd operand mem !!addr16 [saddrp] [whl +] byte n none note 2 1st operand !!addr24 [%saddrg] ax (movw) movw (movw) xchw xchw (xchw) rp movw shrw mulw note 4 shlw incw decw saddrp incw decw sfrp push pop !addr16 movtblw !!addr24 mem [saddrp] [%saddrg] psw push pop sp post push pop pushu popu [tde +] sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. if saddrp is saddrp2 in this combination, there is a short code length instruction. 4. muluw and divux are the same as mulw. 604 chapter 29 instruction operation user s manual u13570ej3v0ud (3) 24-bit instructions (the values enclosed by parentheses are combined to express whl description as rg.) movg, addg, subg, incg, decg, push, pop table 29-3. 24-bit addressing instructions second #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note operand rg' first operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note there is no second operand, or the second operand is not an operand address. (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 29-4. bit manipulation instruction addressing instructions second operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit !addr16.bit /!addr16.bit first operand !!addr24.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note there is no second operand, or the second operand is not an operand address. 605 chapter 29 instruction operation user s manual u13570ej3v0ud (5) call return instructions and branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 29-5. call return instructions and branch instruction addressing instructions instruction address operand $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none basic instructions bc note call call call call call call call callf callt brkcs brk br br br br br br br br ret retcs reti retcsb retb composite instructions bf bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are identical to bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs 606 user s manual u13570ej3v0ud chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ? 0.3 to +6.5 v av dd ? 0.3 to v dd + 0.3 v av ss ? 0.3 to v ss + 0.3 v av ref0 a/d converter reference voltage input ? 0.3 to v dd + 0.3 v av ref1 d/a converter reference voltage input ? 0.3 to v dd + 0.3 v input voltage v i1 other than p90 to p95 ? 0.3 to v dd + 0.3 v v i2 p90 to p95 n-ch open drain ? 0.3 to +12 v analog input voltage v an analog input pin av ss ? 0.3 to av ref0 + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v output current, low i ol per pin 15 ma total of p2, p4 to p8 75 ma total of p0, p3, p9, p10, p12, p13 75 ma total of all pins 100 ma output current, high i oh per pin ? 10 ma total of all pins ? 50 ma operating ambient t a ? 40 to +85 c temperature storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 607 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud operating conditions ? operating ambient temperature (t a ): ? 40 to +85 c ? power supply voltage and clock cycle time: see figure 30-1 ? power supply voltage with subsystem clock operation: v dd = 1.8 to 5.5 v figure 30-1. power supply voltage and clock cycle time (cpu clock frequency: f cpu ) capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz other than port 9 15 pf unmeasured pins port 9 20 pf output capacitance c o returned to 0 v. other than port 9 15 pf port 9 20 pf i/o capacitance c io other than port 9 15 pf port 9 20 pf 8,000 10,000 500 400 300 320 160 80 200 100 0 0123 1.8 2.7 4.5 5.5 supply voltage [v] 456 clock cycle time t cyk [ns] guaranteed operation range 608 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud main system clock oscillator characteristics (t a = ? ? ? ? ? 40 to +85 c) resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation enmp = 0 4.5 v v dd 5.5 v 4 25 mhz resonator frequency (f x ) 2.7 v v dd < 4.5 v 4 12.5 or crystal 2.0 v v dd < 2.7 v 4 6.25 resonator 1.8 v v dd < 2.0 v 4 4 enmp = 1 4.5 v v dd 5.5 v 2 12.5 mhz 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 1.8 v v dd < 2.0 v 2 2 external x1 input enmp = 0 4.5 v v dd 5.5 v 4 25 mhz clock frequency (f x ) 2.7 v v dd < 4.5 v 4 12.5 2.0 v v dd < 2.7 v 4 6.25 1.8 v v dd < 2.0 v 4 4 enmp = 1 4.5 v v dd 5.5 v 2 12.5 mhz 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 1.8 v v dd < 2.0 v 2 2 x1 input high-/low- 15 250 ns level width (t wxh , t wxl ) x1 input rising/falling 4.5 v v dd 5.5 v 0 5 ns time (t xr , t xf ) 2.7 v v dd < 4.5 v 0 10 2.0 v v dd < 2.7 v 0 20 1.8 v v dd < 2.0 v 0 30 cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? ? keep the wiring length as short as possible. ? ? ? ? ? do not cross the wiring with other signal lines. ? ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. x2 x1 v ss x2 x1 609 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud subsystem clock oscillator characteristics (t a = ? ? ? ? ? 40 to +85 c) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation frequency (f xt )32 32.768 35 khz resonator oscillation stabilization 4.5 v v dd 5.5 v 1.2 2 s time note 1.8 v v dd < 4.5 v 10 external xt1 input frequency (f xt ) 32 35 khz clock xt1 input high-/low-level 14.3 15.6 s width (t xth , t xtl ) note time required to stabilize oscillation after applying the supply voltage (v dd ). cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? ? keep the wiring length as short as possible. ? ? ? ? ? do not cross the wiring with other signal lines. ? ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. v ss xt2 xt1 xt2 xt1 610 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud recommended oscillator constant main system clock: ceramic resonator connection (t a = ? ? ? ? ? 40 to +85 c) (1) pd784214a, 784215a, 784216a, 784214ay, 784215ay, 784216ay manufacturer part number oscillation recommended circuit oscillation voltage oscillation frequency constants range stabilization time f xx (mhz) c1 (pf) c2 (pf) min. (v) max. (v) (max.) t ost (ms) murata mfg. cstls4m00g56-b0 4.0 on-chip on-chip 2.7 5.5 0.40 co., ltd. cstls8m00g53-b0 8.0 on-chip on-chip 4.5 5.5 0.28 cstla12m5t55-b0 12.5 on-chip on-chip 4.5 5.5 0.29 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of each product within the specifications of the dc and ac characteristics. (2) pd784217a, 784218a, 784217ay, 784218ay (1/2) manufacturer part number oscillation recommended circuit oscillation voltage oscillation frequency constants range stabilization time f xx (mhz) c1 (pf) c2 (pf) min. (v) max. (v) (max.) t ost (ms) murata mfg. cstcc2.00mg0h6 2.0 on-chip on-chip 1.9 5.5 0.46 co., ltd. csa2.00mg040 2.0 100 100 2.0 5.5 0.74 cst2.00mg040 2.0 on-chip on-chip 2.0 5.5 0.74 cstcc4.00mg0h6 4.0 on-chip on-chip 2.7 5.5 0.43 cstcc4.00mgu0h6 4.0 on-chip on-chip 2.7 5.5 0.43 csa4.00mg 4.0 30 30 2.7 5.5 0.32 cst4.00mgw 4.0 on-chip on-chip 2.7 5.5 0.32 csa4.00mg093 4.0 30 30 2.7 5.5 0.32 cst4.00mgw093 4.0 on-chip on-chip 2.7 5.5 0.32 cstls4m00g56-b0 4.0 on-chip on-chip 2.7 5.5 0.45 cstls4m00g56093-b0 4.0 on-chip on-chip 2.7 5.5 0.45 cstcc6.00mg0h6 6.0 on-chip on-chip 2.7 5.5 0.45 cstcc6.00mgu0h6 6.0 on-chip on-chip 2.7 5.5 0.45 csa6.00mg 6.0 30 30 2.7 5.5 0.33 cst6.00mgw 6.0 on-chip on-chip 2.7 5.5 0.33 csa6.00mg093 6.0 30 30 2.7 5.5 0.33 cst6.00mgw093 6.0 on-chip on-chip 2.7 5.5 0.33 cstls6m00g56-b0 6.0 on-chip on-chip 2.7 5.5 0.45 cstls6m00g56093-b0 6.0 on-chip on-chip 2.7 5.5 0.45 cstcc8.00mg 8.0 on-chip on-chip 4.5 5.5 0.28 cstcc8.00mg093 8.0 on-chip on-chip 4.5 5.5 0.28 611 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (2) pd784217a, 784218a, 784217ay, 784218ay (2/2) manufacturer part number oscillation recommended circuit oscillation voltage oscillation frequency constants range stabilization time f xx (mhz) c1 (pf) c2 (pf) min. (v) max. (v) (max.) t ost (ms) murata mfg. csa8.00mtz 8.0 30 30 4.5 5.5 0.30 co, ltd. cst8.00mtw 8.0 on-chip on-chip 4.5 5.5 0.30 csa8.00mtz093 8.0 30 30 4.5 5.5 0.30 cst8.00mtw093 8.0 on-chip on-chip 4.5 5.5 0.30 cstls8m00g53-b0 8.0 on-chip on-chip 4.5 5.5 0.27 cstls8m00g53093-b0 8.0 on-chip on-chip 4.5 5.5 0.27 cstcc10.0mg 10.0 on-chip on-chip 4.5 5.5 0.28 cstcc10.0mg093 10.0 on-chip on-chip 4.5 5.5 0.28 csa10.0mtz 10.0 30 30 4.5 5.5 0.32 cst10.0mtw 10.0 on-chip on-chip 4.5 5.5 0.32 csa10.0mtz093 10.0 30 30 4.5 5.5 0.32 cst10.0mtw093 10.0 on-chip on-chip 4.5 5.5 0.32 cstcv12.5mtj0c4 12.5 on-chip on-chip 4.5 5.5 0.26 csa12.5mtz 12.5 30 30 4.5 5.5 0.30 cstla12m5t55-b0 12.5 on-chip on-chip 4.5 5.5 0.30 csa12.5mtz093 12.5 30 30 4.5 5.5 0.30 cstla12m5t55093-b0 12.5 on-chip on-chip 4.5 5.5 0.30 kyocera pbrc2.00ar-a 2.0 68 68 1.9 5.5 0.4 corporation pbrc4.00hr 4.0 on-chip on-chip 2.7 5.5 0.4 pbrc6.00hr 6.0 on-chip on-chip 2.7 5.5 0.2 ssr8.00cr-s24 8.0 on-chip on-chip 4.5 5.5 0.4 ssr12.50cr-s24 12.5 on-chip on-chip 4.5 5.5 0.3 tdk fcr4.0mc5 4.0 on-chip on-chip 2.7 5.5 0.28 fcr6.0mc5 6.0 on-chip on-chip 2.7 5.5 0.28 fcr8.0mc5 8.0 on-chip on-chip 4.5 5.5 0.3 fcr10.0mc5 10.0 on-chip on-chip 4.5 5.5 0.4 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of each product within the specifications of the dc and ac characteristics. 612 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud dc characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit input voltage, low v il1 note 1 2.2 v v dd 5.5 v 0 0.3v dd v 1.8 v v dd < 2.2 v 0 0.2v dd v il2 p00 to p06, p20, p22, p33, p34, 2.2 v v dd 5.5 v 0 0.2v dd v p70, p72, p100 to p103, reset 1.8 v v dd < 2.2 v 0 0.15v dd v il3 p90 to p95 2.2 v v dd 5.5 v 0 0.3v dd v (n-ch open drain) 1.8 v v dd < 2.2 v 0 0.2v dd v il4 p10 to p17, p130, p131 2.2 v v dd 5.5 v 0 0.3v dd v 1.8 v v dd < 2.2 v 0 0.2v dd v il5 x1, x2, xt1, xt2 2.2 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 2.2 v 0 0.1v dd v il6 p25, p27 2.2 v v dd 5.5 v 0 0.3v dd v 1.8 v v dd < 2.2 v 0 0.2v dd input voltage, high v ih1 note 1 2.2 v v dd 5.5 v 0.7v dd v dd v 1.8 v v dd < 2.2 v 0.8v dd v dd v ih2 p00 to p06, p20, p22, p33, p34, 2.2 v v dd 5.5 v 0.8v dd v dd v p70, p72, p100 to p103, reset 1.8 v v dd < 2.2 v 0.85v dd v dd v ih3 p90 to p95 2.2 v v dd 5.5 v 0.7v dd 12 v (n-ch open drain) 1.8 v v dd < 2.2 v 0.8v dd v dd v ih4 p10 to p17, p130, p131 2.2 v v dd 5.5 v 0.7v dd v dd v 1.8 v v dd < 2.2 v 0.8v dd v dd v ih5 x1, x2, xt1, xt2 2.2 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 2.2 v 0.85v dd v dd v ih6 p25, p27 2.2 v v dd 5.5 v 0.7v dd v dd v 1.8 v v dd < 2.2 v 0.8v dd v dd output voltage, low v ol1 for pins other than 4.5 v v dd 5.5 v 0.4 v p40 to p47, p50 to p57, p90 to p95, i ol = 1.6 ma note 2 p40 to p47, p50 to p57 4.5 v v dd 5.5 v 1.0 v i ol = 8 ma note 2 p90 to p95 i ol = 15 ma note 2 4.5 v v dd 5.5 v 0.8 2.0 v v ol2 i ol = 400 a note 2 0.5 v output voltage, high v oh1 i oh = ? 1 ma note 2 4.5 v v dd 5.5 v v dd ? 1.0 v i oh = ? 100 a note 2 1.8 v v dd 5.5 v v dd ? 0.5 v input leakage current, i lil1 v i = 0 v except x1, x2, ? 3 a low xt1, xt2 i lil2 x1, x2, xt1, xt2 ? 20 a notes 1. p21, p23, p24, p26, p30 to p32, p35 to p37, p40 to p47, p50 to p57, p60 to p67, p71, p120 to p127 2. per pin 613 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud dc characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (2/3) parameter symbol conditions min. typ. max. unit input leakage current, i lih1 v i = v dd except x1, x2, 3 a high xt1, xt2 i lih2 x1, x2, xt1, xt2 20 a i lih3 v i = 12 v p90 to p95 20 a (n-ch open drain) output leakage current, low i lol1 v o = 0 v ? 3 a output leakage current, high i loh1 v o = v dd 3 a (1) pd784214a, 784215a, 784216a, 784214ay, 784215ay, 784216ay parameter symbol conditions min. typ. max. unit supply current i dd1 operation f xx = 12.5 mhz, v dd = 5.0 v 10% 11 40 ma mode f xx = 6 mhz, v dd = 3.0 v 10% 3 17 ma f xx = 2 mhz, v dd = 2.0 v 10% 1 8 ma i dd2 halt mode f xx = 12.5 mhz, v dd = 5.0 v 10% 5 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 8 ma f xx = 2 mhz, v dd = 2.0 v 10% 0.3 3.5 ma i dd3 idle mode f xx = 12.5 mhz, v dd = 5.0 v 10% 1 2.5 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.4 1.3 ma f xx = 2 mhz, v dd = 2.0 v 10% 0.2 0.9 ma i dd4 operation f xx = 32 khz, v dd = 5.0 v 10% 80 200 a mode note f xx = 32 khz, v dd = 3.0 v 10% 60 110 a f xx = 32 khz, v dd = 2.0 v 10% 30 100 a i dd5 halt f xx = 32 khz, v dd = 5.0 v 10% 60 160 a mode note f xx = 32 khz, v dd = 3.0 v 10% 20 80 a f xx = 32 khz, v dd = 2.0 v 10% 10 70 a i dd6 idle f xx = 32 khz, v dd = 5.0 v 10% 50 150 a mode note f xx = 32 khz, v dd = 3.0 v 10% 15 70 a f xx = 32 khz, v dd = 2.0 v 10% 5 60 a data retention voltage v dddr halt, idle modes 1.8 5.5 v data retention current i dddr stop mode v dd = 2.0 v 10% 2 10 a v dd = 5.0 v 10% 10 50 a pull-up resistor r l v i = 0 v 10 30 100 k ? note when the main system clock is stopped and subsystem clock is operating. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 614 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud d c characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (3/3) (2) pd784217a, 784218a, 784217ay, 784218ay parameter symbol conditions min. typ. max. unit supply current i dd1 operation f xx = 12.5 mhz, v dd = 5.0 v 10% 11 40 ma mode f xx = 6 mhz, v dd = 3.0 v 10% 4 17 ma f xx = 2 mhz, v dd = 2.0 v 10% 1 8 ma i dd2 halt mode f xx = 12.5 mhz, v dd = 5.0 v 10% 6 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 8 ma f xx = 2 mhz, v dd = 2.0 v 10% 0.4 3.5 ma i dd3 idle mode f xx = 12.5 mhz, v dd = 5.0 v 10% 1 2.5 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.4 1.3 ma f xx = 2 mhz, v dd = 2.0 v 10% 0.2 0.9 ma i dd4 operation f xx = 32 khz, v dd = 5.0 v 10% 80 200 a mode note f xx = 32 khz, v dd = 3.0 v 10% 60 110 a f xx = 32 khz, v dd = 2.0 v 10% 30 100 a i dd5 halt f xx = 32 khz, v dd = 5.0 v 10% 60 160 a mode note f xx = 32 khz, v dd = 3.0 v 10% 20 80 a f xx = 32 khz, v dd = 2.0 v 10% 10 70 a i dd6 idle f xx = 32 khz, v dd = 5.0 v 10% 50 150 a mode note f xx = 32 khz, v dd = 3.0 v 10% 15 70 a f xx = 32 khz, v dd = 2.0 v 10% 5 60 a data retention voltage v dddr halt, idle modes 1.8 5.5 v data retention current i dddr stop mode v dd = 2.0 v 10% 2 10 a v dd = 5.0 v 10% 10 50 a pull-up resistor r l v i = 0 v 10 30 100 k ? note when the main system clock is stopped and subsystem clock is operating. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 615 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud ac characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/3) parameter symbol conditions min. typ. max. unit cycle time t cyk 4.5 v v dd 5.5 v 80 ns 2.7 v v dd < 4.5 v 160 ns 2.0 v v dd < 2.7 v 320 ns 1.8 v v dd < 2.0 v 500 ns address setup time t sast v dd = 5.0 v 10% (0.5 + a) t ? 20 ns (to astb ) v dd = 3.0 v 10% (0.5 + a) t ? 40 ns v dd = 2.0 v 10% (0.5 + a) t ? 80 ns address hold time t hstla v dd = 5.0 v 10% 0.5t ? 19 ns (from astb ) v dd = 3.0 v 10% 0.5t ? 24 ns v dd = 2.0 v 10% 0.5t ? 34 ns astb high-level width t wsth v dd = 5.0 v 10% (0.5 + a) t ? 17 ns v dd = 3.0 v 10% (0.5 + a) t ? 40 ns v dd = 2.0 v 10% (0.5 + a) t ? 110 ns address hold time t hra v dd = 5.0 v 10% 0.5t ? 14 ns (from rd ) v dd = 3.0 v 10% 0.5t ? 14 ns v dd = 2.0 v 10% 0.5t ? 14 ns delay time from address to t dar v dd = 5.0 v 10% (1 + a) t ? 24 ns rd v dd = 3.0 v 10% (1 + a) t ? 35 ns v dd = 2.0 v 10% (1 + a) t ? 80 ns address float time t far v dd = 5.0 v 10% 0 ns (from rd ) v dd = 3.0 v 10% 0 ns v dd = 2.0 v 10% 0 ns data input time from t daid v dd = 5.0 v 10% (2.5 + a + n) t ? 37 ns address v dd = 3.0 v 10% (2.5 + a + n) t ? 52 ns v dd = 2.0 v 10% (2.5 + a + n) t ? 120 ns data input time from astb t dstid v dd = 5.0 v 10% (2 + n) t ? 35 ns v dd = 3.0 v 10% (2 + n) t ? 50 ns v dd = 2.0 v 10% (2 + n) t ? 80 ns data input time from rd t drid v dd = 5.0 v 10% (1.5 + n) t ? 40 ns v dd = 3.0 v 10% (1.5 + n) t ? 50 ns v dd = 2.0 v 10% (1.5 + n) t ? 90 ns delay time from astb to t dstr v dd = 5.0 v 10% 0.5t ? 9ns rd v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 10% 0.5t ? 20 ns data hold time (from rd )t hrid v dd = 5.0 v 10% 0 ns v dd = 3.0 v 10% 0 ns v dd = 2.0 v 10% 0 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) 616 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (1) read/write operation (2/3) parameter symbol conditions min. typ. max. unit address active time from t dra v dd = 5.0 v 10% 0.5t ? 2ns rd v dd = 3.0 v 10% 0.5t ? 12 ns v dd = 2.0 v 10% 0.5t ? 35 ns delay time from rd t drst v dd = 5.0 v 10% 0.5t ? 9ns to astb v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 10% 0.5t ? 40 ns rd low-level width t wrl v dd = 5.0 v 10% (1.5 + n) t ? 25 ns v dd = 3.0 v 10% (1.5 + n) t ? 30 ns v dd = 2.0 v 10% (1.5 + n) t ? 25 ns address active time t dwa v dd = 5.0 v 10% 0.5t ? 2ns from wr v dd = 3.0 v 10% 0.5t ? 12 ns v dd = 2.0 v 10% 0.5t ? 35 ns delay time from t daw v dd = 5.0 v 10% (1 + a) t ? 24 ns address to wr v dd = 3.0 v 10% (1 + a) t ? 34 ns v dd = 2.0 v 10% (1 + a) t ? 70 ns address hold time t hwa v dd = 5.0 v 10% 0.5t ? 14 ns (from wr ) v dd = 3.0 v 10% 0.5t ? 14 ns v dd = 2.0 v 10% 0.5t ? 14 ns delay time from t dstod v dd = 5.0 v 10% 0.5t + 15 ns astb to data output v dd = 3.0 v 10% 0.5t + 30 ns v dd = 2.0 v 10% 0.5t + 240 ns delay time from wr t dwod v dd = 5.0 v 10% 0.5t ? 30 ns to data output v dd = 3.0 v 10% 0.5t ? 30 ns v dd = 2.0 v 10% 0.5t ? 30 ns delay time from astb t dstw v dd = 5.0 v 10% 0.5t ? 9ns to wr v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 10% 0.5t ? 20 ns data setup time (to wr )t sodwr v dd = 5.0 v 10% (1.5 + n) t ? 20 ns v dd = 3.0 v 10% (1.5 + n) t ? 25 ns v dd = 2.0 v 10% (1.5 + n) t ? 70 ns data hold time (from wr )t hwod v dd = 5.0 v 10% 0.5t ? 14 ns v dd = 3.0 v 10% 0.5t ? 14 ns v dd = 2.0 v 10% 0.5t ? 50 ns delay time from wr t dwst v dd = 5.0 v 10% 0.5t ? 9ns to astb v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 10% 0.5t ? 30 ns wr low-level width t wwl v dd = 5.0 v 10% (1.5 + n) t ? 25 ns v dd = 3.0 v 10% (1.5 + n) t ? 30 ns v dd = 2.0 v 10% (1.5 + n) t ? 30 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) 617 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (1) read/write operation (3/3) parameter symbol conditions min. typ. max. unit delay time from address t adexd v dd = 5.0 v 10% 0 ns to exa v dd = 3.0 v 10% 0 ns v dd = 2.0 v 10% 0 ns delay time from exa to t extah v dd = 5.0 v 10% 0.5t ? 20 ns astb v dd = 3.0 v 10% 0.5t ? 30 ns v dd = 2.0 v 10% 0.5t ? 40 ns delay time from rd to t exrds v dd = 5.0 v 10% 0 ns exa v dd = 3.0 v 10% 0 ns v dd = 2.0 v 10% 0 ns delay time from wr to t exwds v dd = 5.0 v 10% t ns exa v dd = 3.0 v 10% t ns v dd = 2.0 v 10% t ns delay time from exa to t exadr v dd = 5.0 v 10% 0.5t ns astb v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 10% 0.5t ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) 618 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (2) external wait timing (1/2) parameter symbol conditions min. typ. max. unit input time from address to t dawt v dd = 5.0 v 10% (2 + a) t ? 40 ns wait v dd = 3.0 v 10% (2 + a) t ? 60 ns v dd = 2.0 v 10% (2 + a) t ? 300 ns input time from astb to t dstwt v dd = 5.0 v 10% 1.5t ? 40 ns wait v dd = 3.0 v 10% 1.5t ? 60 ns v dd = 2.0 v 10% 1.5t ? 260 ns hold time from astb to t hstwt v dd = 5.0 v 10% (0.5 + n) t + 5 ns wait v dd = 3.0 v 10% (0.5 + n) t + 10 ns v dd = 2.0 v 10% (0.5 + n) t + 30 ns delay time from astb to t dstwth v dd = 5.0 v 10% (1.5 + n) t ? 40 ns wait v dd = 3.0 v 10% (1.5 + n) t ? 60 ns v dd = 2.0 v 10% (1.5 + n) t ? 90 ns input time from rd to t drwtl v dd = 5.0 v 10% t ? 40 ns wait v dd = 3.0 v 10% t ? 60 ns v dd = 2.0 v 10% t ? 70 ns hold time from rd to t hrwt v dd = 5.0 v 10% nt + 5 ns wait v dd = 3.0 v 10% nt + 10 ns v dd = 2.0 v 10% nt + 30 ns delay time from rd to t drwth v dd = 5.0 v 10% (1 + n) t ? 40 ns wait v dd = 3.0 v 10% (1 + n) t ? 60 ns v dd = 2.0 v 10% (1 + n) t ? 90 ns data input time from wait t dwtid v dd = 5.0 v 10% 0.5t ? 5ns v dd = 3.0 v 10% 0.5t ? 10 ns v dd = 2.0 v 10% 0.5t ? 30 ns delay time from wait to t dwtr v dd = 5.0 v 10% 0.5t ns rd v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 10% 0.5t + 5 ns delay time from wait to t dwtw v dd = 5.0 v 10% 0.5t ns wr v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 10% 0.5t + 5 ns input time from wr to t dwwtl v dd = 5.0 v 10% t ? 40 ns wait v dd = 3.0 v 10% t ? 60 ns v dd = 2.0 v 10% t ? 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) 619 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (2) external wait timing (2/2) parameter symbol conditions min. typ. max. unit hold time from wr to t hwwt v dd = 5.0 v 10% nt + 5 ns wait v dd = 3.0 v 10% nt + 10 ns v dd = 2.0 v 10% nt + 30 ns delay time from wr to t dwwth v dd = 5.0 v 10% (1 + n) t ? 40 ns wait v dd = 3.0 v 10% (1 + n) t ? 60 ns v dd = 2.0 v 10% (1 + n) t ? 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) n: number of wait states (n 0) 620 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (3) serial operation (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (1/2) (a) 3-wire serial i/o mode (sck: internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 4.5 v v dd 5.5 v 640 ns 2.7 v v dd < 4.5 v 1,280 ns 2.0 v v dd < 2.7 v 2,560 ns 1.8 v v dd < 2.0 v 4,000 ns sck high-/low-level t kh1 , 4.5 v v dd 5.5 v 270 ns width t kl1 2.7 v v dd < 4.5 v 590 ns 2.0 v v dd < 2.7 v 1,180 ns 1.8 v v dd < 2.0 v 1,900 ns si setup time (to sck )t sik1 2.7 v v dd 5.5 v 10 ns 1.8 v v dd < 2.7 v 30 ns si hold time (from sck ) t hik1 40 ns delay time from sck t dso1 30 ns to so output hold time from sck t hso1 t kcy1 /2 ?50 ns to so output (b) 3-wire serial i/o mode (sck: external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 4.5 v v dd 5.5 v 640 ns 2.7 v v dd < 4.5 v 1,280 ns 2.0 v v dd < 2.7 v 2,560 ns 1.8 v v dd < 2.0 v 4,000 ns sck high-/low-level t kh2 , 4.5 v v dd 5.5 v 320 ns width t kl2 2.7 v v dd < 4.5 v 640 ns 2.0 v v dd < 2.7 v 1,280 ns 1.8 v v dd < 2.0 v 2,000 ns si setup time (to sck )t sik2 2.7 v v dd 5.5 v 10 ns 1.8 v v dd < 2.7 v 30 ns si hold time (from sck ) t hik2 40 ns delay time from sck t dso2 30 ns to so output hold time from sck t hso2 t kcy2 /2 ?50 ns to so output (c) uart mode parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 4.5 v v dd 5.5 v 417 ns 2.7 v v dd < 4.5 v 833 ns 1.8 v v dd < 2.7 v 1,667 ns asck high-/low-level t kh3 , 4.5 v v dd 5.5 v 208 ns width t kl3 2.7 v v dd < 4.5 v 416 ns 1.8 v v dd < 2.7 v 833 ns 621 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (3) serial operation (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (2/2) (d) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus free time (between stop t buf 4.7 ? 1.3 ? s and start conditions) hold time note 1 t hd : sta 4.0 ? 0.6 ? s low-level width of scl0 t low 4.7 ? 1.3 ? s clock high-level width of scl0 t high 4.0 ? 0.6 ? s clock setup time of start/restart t su : sta 4.7 ? 0.6 ? s conditions data hold when using t hd : dat 5.0 ??? s time cbus-compatible master when using i 2 c0 note 2 ? 0 note 2 0.9 note 3 s bus data setup time t su : dat 250 ? 100 note 4 ? ns rising time of sda0 and t r ? 1,000 20 + 0.1cb note 5 300 ns scl0 signals falling time of sda0 and t f ? 300 20 + 0.1cb note 5 300 ns scl0 signals setup time of stop condition t su : sto 4.0 ? 0.6 ? s pulse width of spike t sp ?? 050ns restricted by input filter load capacitance of each cb ? 400 ? 400 pf bus line notes 1. for the start condition, the first clock pulse is generated after the hold time. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to provide an internal sda0 signal (on v ihmin. ) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low-level hold time (t low ), only the maximum data hold time t hd : dat needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in a standard mode i 2 c bus system. in this case, the conditions described below must be satisfied. ? if the device does not extend the scl0 signal low-level hold time t su : dat 250 ns ? if the device extends the scl0 signal low-level hold time be sure to transmit the data bit to the sda0 line before the scl0 line is released (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns by standard mode i 2 c bus specification) 5. cb: total capacitance per bus line (unit: pf) 622 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (4) clock output operation (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit pcl cycle time t cycl 4.5 v v dd 5.5 v, nt 80 31,250 ns pcl high-/low-level t cll , 4.5 v v dd 5.5 v, 0.5t ? 10 30 15,615 ns width t clh pcl rise/fall time t clr , 4.5 v v dd 5.5 v 5 ns t clf 2.7 v v dd < 4.5 v 10 ns 1.8 v v dd < 2.7 v 20 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) n: divided frequency ratio set by software in the cpu ? when using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 ? when using the subsystem clock: n = 1 (5) other operations (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit nmi high-/low-level t wnil ,10 s width t wnih intp input high-/low- t witl , intp0 to intp6 100 ns level width t with reset high-/low-level t wrsl ,10 s width t wrsh 623 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud a/d converter characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error notes 1, 2 2.7 v v dd 5.5 v, 1.2 %fsr 2.2 v av ref0 v dd , av dd = v dd 1.8 v v dd < 2.7 v, 1.6 %fsr 1.8 v av ref0 v dd , av dd = v dd conversion time t conv 14 144 s sampling time t samp 24/f xx s analog input voltage v ian av ss av ref0 v reference voltage av ref0 1.8 av dd v resistance between r avref0 when not a/d converting 40 k ? av ref0 and av ss notes 1. quantization error ( 1/2 lsb) is not included. 2. overall error is indicated as a ratio to the full-scale value (%fsr). remark f xx : main system clock frequency d/a converter characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error notes 1, 2 r = 10 m ? , 2.0 v av ref1 v dd , 0.6 %fsr 2.0 v v dd 5.5 v, av dd = v dd r = 10 m ? , 1.8 v av ref1 v dd , 1.2 %fsr 1.8 v v dd 2.0 v, av dd = v dd settling time load conditions: 4.5 v av ref1 5.5 v 10 s c = 30 pf 2.7 v av ref1 < 4.5 v 15 s 1.8 v av ref1 < 2.7 v 20 s output resistance r o dacs0, 1 = 55h 8 k ? reference voltage av ref1 1.8 v dd v av ref1 current ai ref1 for only 1 channel 2.5 ma notes 1. quantization error ( 1/2 lsb) is not included. 2. overall error is indicated as a ratio to the full-scale value (%fsr). 624 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud data retention characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.8 5.5 v data retention current i dddr v dddr = 5.0 v 10% 10 50 a v dddr = 2.0 v 10% 2 10 a v dd rise time t rvd 200 s v dd fall time t fvd 200 s v dd hold time (from t hvd 0ms stop mode setting) stop release signal t drel 0ms input time oscillation stabilization t wait crystal resonator 30 ms wait time ceramic resonator 5 ms low-level input voltage v il reset, p00/intp0 to p06/intp6 0 0.1v dddr v high-level input voltage v ih 0.9v dddr v dddr v ac timing test points 0.8v dd or 1.8 v 0.8 v 0.8v dd or 1.8 v 0.8 v points of test v dd 1 v 0.45 v 625 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud timing waveforms (1) read operations remark the signal is output from pins a0 to a7 when p80 to p87 are unused. wait (input) (clk) a8 to a19 (output) astb (output) rd (output) exa ad0 to ad7 (i/o) t cyk higher address hi-z hi-z hi-z higher address a0 to a7 (output) lower address lower address data (input) lower address (output) lower address (output) t daid t hra t sast t wsth t dstr t drst t dar t drid t wrl t drwth t dstwt t dstwth t hstwt t hrwt t dawt t dwtr t hstla t far t dwtid t drwtl t hrid t dra t dstid t extah t exadr t exrds t adexd 626 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud (2) write operation remark the signal is output from pins a0 to a7 when p80 to p87 are unused. wait (input) wr (output) (clk) a8 to a19 (output) astb (output) ad0 to ad7 (output) t cyk higher address higher address a0 to a7 (output) lower address lower address data (output) lower address (output) lower address (output) t daid t hwa t sast t wsth t dstw t dwst t daw t dwod t wwl t dwwth t dstwt t dstwth t hstwt t hwwt t dawt t dwtw t hstla t far t dwtid t dwwtl t hwod t dwa t dstod t sodwr hi-z hi-z hi-z exa t extah t exadr t exwds t adexd 627 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud serial operation (1) 3-wire serial i/o mode (2) uart mode (3) i 2 c bus mode ( pd784216ay, 784218ay subseries only) sck so si output data input data t kcy1, 2 t kh1, 2 t kl1, 2 t hso1, 2 t sik1, 2 t dso1, 2 t hik1, 2 asck t kcy3 t kh3 t kl3 scl0 sda0 t hd : sta t buf t hd : dat t high t f t su : dat t su : sta t hd : sta t sp t su : sto t r stop condition start condition stop condition restart condition 628 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud clock output timing interrupt input timing reset input timing clkout t clh t cll t cycl t clf t clr nmi intp0 to intp6 t wnih t wnil t with t witl reset t wrsh t wrsl 629 chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) user s manual u13570ej3v0ud clock timing data retention characteristics xt1 t xth t xtl 1/f xt x1 t wxh t wxl 1/f x t xf t xr v dd reset nmi (cleared by falling edge) nmi (cleared by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait 630 user s manual u13570ej3v0ud chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ? 0.3 to +6.5 v v pp note ? 0.3 to +10.5 v av dd ? 0.3 to v dd + 0.3 v av ss ? 0.3 to v ss + 0.3 v av ref0 a/d converter reference voltage input ? 0.3 to v dd + 0.3 v av ref1 d/a converter reference voltage input ? 0.3 to v dd + 0.3 v input voltage v i1 other than p90 to p95 ? 0.3 to v dd + 0.3 v v i2 p90 to p95 n-ch open drain ? 0.3 to +12 v v i3 v dd pin during programing ? 0.3 to +10.5 v analog input voltage v an analog input pin av ss ? 0.3 to av ref0 + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v output current, low i ol per pin 15 ma total of p2, p4 to p8 75 ma total of p0, p3, p9, p10, p12, p13 75 ma total of all pins 100 ma output current, high i oh per pin ? 10 ma total of all pins ? 50 ma operating ambient t a during normal operation ? 40 to +85 c temperature during flash memory programming + 10 to +40 c storage temperature t stg ? 65 to +150 c (the notes are explained on the following page.) cautions 1. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2. the operating ambient temperature of the pd78f4216a and 78f4218a rank k is t a = ? ? ? ? ? 10 to +60 c, and the storage temperature is t stg = ? ? ? ? ? 10 to +80 c. 631 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud note make sure that the following conditions of the vpp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.9 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.9 v) of the operating voltage range of v dd (see b in the figure below). 1.9 v v dd 0 v 0 v v pp 1.9 v a b 632 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud operating conditions ? operating ambient temperature (t a ): ? 40 to +85 c ? power supply voltage and clock cycle time: see figure 31-1 ? power supply voltage with subsystem clock operation: v dd = 1.9 to 5.5 v figure 31-1. power supply voltage and clock cycle time (cpu clock frequency: f cpu ) caution the operating voltage of the pd78f4216a and 78f4216ay rank k, e is 2.7 v v dd 5.5 v. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz other than port 9 15 pf unmeasured pins port 9 20 pf output capacitance c o returned to 0 v. other than port 9 15 pf port 9 20 pf i/o capacitance c io other than port 9 15 pf port 9 20 pf 8,000 10,000 500 400 300 320 160 80 200 100 0 0123 1.9 2.7 4.5 5.5 supply voltage [v] 456 clock cycle time t cyk [ns] guaranteed operating range 633 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud main system clock oscillator characteristics (t a = ? ? ? ? ? 40 to +85 c) resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation enmp = 0 4.5 v v dd 5.5 v 4 25 mhz resonator frequency (f x ) 2.7 v v dd < 4.5 v 4 12.5 or crystal 2.0 v v dd < 2.7 v 4 6.25 resonator 1.9 v v dd < 2.0 v 4 4 enmp = 1 4.5 v v dd 5.5 v 2 12.5 mhz 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 1.9 v v dd < 2.0 v 2 2 external x1 input enmp = 0 4.5 v v dd 5.5 v 4 25 mhz clock frequency (f x ) 2.7 v v dd < 4.5 v 4 12.5 2.0 v v dd < 2.7 v 4 6.25 1.9 v v dd < 2.0 v 4 4 enmp = 1 4.5 v v dd 5.5 v 2 12.5 mhz 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 1.9 v v dd < 2.0 v 2 2 x1 input high-/low- 15 250 ns level width (t wxh , t wxl ) x1 input rising/falling 4.5 v v dd 5.5 v 0 5 ns time (t xr , t xf ) 2.7 v v dd < 4.5 v 0 10 2.0 v v dd < 2.7 v 0 20 1.9 v v dd < 2.0 v 0 30 cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? ? keep the wiring length as short as possible. ? ? ? ? ? do not cross the wiring with other signal lines. ? ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched back to the main system clock after the oscillation stabilization time is secured by the program. x2 x1 v ss x2 x1 634 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud subsystem clock oscillator characteristics (t a = ? ? ? ? ? 40 to +85 c) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation frequency (f xt )32 32.768 35 khz resonator oscillation stabilization 4.5 v v dd 5.5 v 1.2 2 s time note 1.9 v v dd < 4.5 v 10 external xt1 input frequency (f xt ) 32 35 khz clock xt1 input high-/low-level 14.3 15.6 s width (t xth , t xtl ) note time required to stabilize oscillation after applying the supply voltage (v dd ). cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? ? keep the wiring length as short as possible. ? ? ? ? ? do not cross the wiring with other signal lines. ? ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. v ss xt2 xt1 xt2 xt1 635 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud recommended oscillator constant main system clock: ceramic resonator connection (t a = ? ? ? ? ? 40 to +85 c) (1) pd78f4216a, 78f4216ay manufacturer part number oscillation recommended circuit oscillation voltage oscillation frequency constants range stabilization time f xx (mhz) c1 (pf) c2 (pf) min. (v) max. (v) (max.) t ost (ms) murata mfg. csts0200mg06 2.0 on-chip on-chip 1.9 5.5 0.46 co., ltd. cstcc2.00mg0h6 2.0 on-chip on-chip 1.9 5.5 0.44 csts0400mg06 4.0 on-chip on-chip 2.7 5.5 0.44 cstcc4.00mg0h6 4.0 on-chip on-chip 2.7 5.5 0.40 csts0600mg03 6.0 on-chip on-chip 2.7 5.5 0.25 cstcc6.00mg 6.0 on-chip on-chip 2.7 5.5 0.25 csts0800mg03 8.0 on-chip on-chip 4.5 5.5 0.24 cstcc8.00mg 8.0 on-chip on-chip 4.5 5.5 0.24 cst10.0mtw 10.0 on-chip on-chip 4.5 5.5 0.30 cst10.0mtw093 10.0 on-chip on-chip 4.5 5.5 0.30 cstcc10.0mg 10.0 on-chip on-chip 4.5 5.5 0.25 cstcc10.0mg93 10.0 on-chip on-chip 4.5 5.5 0.25 cst12.5mtw 12.5 on-chip on-chip 4.5 5.5 0.30 cst12.5mtw093 12.5 on-chip on-chip 4.5 5.5 0.30 cstcv12.5mtj0c4 12.5 on-chip on-chip 4.5 5.5 0.25 kyocera pbrc4.00hr 4.0 on-chip on-chip 2.7 5.5 0.3 corporation pbrc4.00gr 4.0 33 33 2.7 5.5 0.3 kbr-4.0mkc 4.0 on-chip on-chip 2.7 5.5 0.3 kbr-4.0msb 4.0 33 33 2.7 5.5 0.3 pbrc8.00hr 8.0 on-chip on-chip 4.5 5.5 0.3 pbrc8.00gr 8.0 33 33 4.5 5.5 0.3 kbr-8.0mkc 8.0 on-chip on-chip 4.5 5.5 0.3 kbr-8.0msb 8.0 33 33 4.5 5.5 0.3 pbrc10.00br-a 10.0 on-chip on-chip 4.5 5.5 0.2 pbrc12.50br-a 12.5 on-chip on-chip 4.5 5.5 0.2 tdk fcr4.0mc5 4.0 on-chip on-chip 2.7 5.5 0.17 fcr6.0mc5 6.0 on-chip on-chip 2.7 5.5 0.15 fcr8.0mc5 8.0 on-chip on-chip 4.5 5.5 0.15 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of each product within the specifications of the dc and ac characteristics. 636 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (2) pd78f4218a, 78f4218ay manufacturer part number oscillation recommended circuit oscillation voltage oscillation frequency constants range stabilization time f xx (mhz) c1 (pf) c2 (pf) min. (v) max. (v) (max.) t ost (ms) murata mfg. csts2.00mg040 2.0 on-chip on-chip 1.9 5.5 0.72 co., ltd. cstls2m00g56-b0 2.0 on-chip on-chip 1.9 5.5 0.48 cstcc2m00g56-r0 2.0 on-chip on-chip 1.9 5.5 0.50 cstls4m00g56-b0 4.0 on-chip on-chip 2.7 5.5 0.47 cstcr4m00g55-r0 4.0 on-chip on-chip 2.7 5.5 0.45 cstls6m00g56-b0 6.0 on-chip on-chip 2.7 5.5 0.48 cstcr6m00g55-r0 6.0 on-chip on-chip 2.7 5.5 0.45 cstls8m00g53-b0 8.0 on-chip on-chip 4.5 5.5 0.30 cstcc8m00g53-r0 8.0 on-chip on-chip 4.5 5.5 0.28 cstls10m0g53-b0 10.0 on-chip on-chip 4.5 5.5 0.29 cstcc10m0g53-r0 10.0 on-chip on-chip 4.5 5.5 0.30 cstla12m5t55-b0 12.5 on-chip on-chip 4.5 5.5 0.33 cstcv12m5t54j-r0 12.5 on-chip on-chip 4.5 5.5 0.30 kyocera pbrc2.00ar-a 2.0 68 68 1.9 5.5 0.4 corporation pbrc4.00hr 4.0 on-chip on-chip 2.7 5.5 0.3 pbrc6.00hr 6.0 on-chip on-chip 2.7 5.5 0.2 ssr8.00cr-s24 8.0 on-chip on-chip 4.5 5.5 0.3 ssr12.50cr-s24 12.5 on-chip on-chip 4.5 5.5 0.3 tdk fcr4.0mc5 4.0 on-chip on-chip 2.7 5.5 0.30 fcr6.0mc5 6.0 on-chip on-chip 2.7 5.5 0.22 fcr8.0mc5 8.0 on-chip on-chip 4.5 5.5 0.3 fcr10.0mc5 10.0 on-chip on-chip 4.5 5.5 0.20 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of each product within the specifications of the dc and ac characteristics. 637 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud dc characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit input voltage, low v il1 note 1 2.2 v v dd 5.5 v 0 0.3v dd v 1.9 v v dd < 2.2 v 0 0.2v dd v il2 p00 to p06, p20, p22, p33, p34, 2.2 v v dd 5.5 v 0 0.2v dd v p70, p72, p100 to p103, reset 1.9 v v dd < 2.2 v 0 0.15v dd v il3 p90 to p95 2.2 v v dd 5.5 v 0 0.3v dd v (n-ch open drain) 1.9 v v dd < 2.2 v 0 0.2v dd v il4 p10 to p17, p130, p131 2.2 v v dd 5.5 v 0 0.3v dd v 1.9 v v dd < 2.2 v 0 0.2v dd v il5 x1, x2, xt1, xt2 2.2 v v dd 5.5 v 0 0.2v dd v 1.9 v v dd < 2.2 v 0 0.1v dd v il6 p25, p27 2.2 v v dd 5.5 v 0 0.3v dd v 1.9 v v dd < 2.2 v 0 0.2v dd input voltage, high v ih1 note 1 2.2 v v dd 5.5 v 0.7v dd v dd v 1.9 v v dd < 2.2 v 0.8v dd v dd v ih2 p00 to p06, p20, p22, p33, p34, 2.2 v v dd 5.5 v 0.8v dd v dd v p70, p72, p100 to p103, reset 1.9 v v dd < 2.2 v 0.85v dd v dd v ih3 p90 to p95 2.2 v v dd 5.5 v 0.7v dd 12 v (n-ch open drain) 1.9 v v dd < 2.2 v 0.8v dd v dd v ih4 p10 to p17, p130, p131 2.2 v v dd 5.5 v 0.7v dd v dd v 1.9 v v dd < 2.2 v 0.8v dd v dd v ih5 x1, x2, xt1, xt2 2.2 v v dd 5.5 v 0.8v dd v dd v 1.9 v v dd < 2.2 v 0.85v dd v dd v ih6 p25, p27 2.2 v v dd 5.5 v 0.7v dd v dd v 1.9 v v dd < 2.2 v 0.8v dd v dd output voltage, low v ol1 for pins other than 4.5 v v dd 5.5 v 0.4 v p40 to p47, p50 to p57, p90 to p95, i ol = 1.6 ma note 2 p40 to p47, p50 to p57 4.5 v v dd 5.5 v 1.0 v i ol = 8 ma note 2 p90 to p95 i ol = 15 ma note 2 4.5 v v dd 5.5 v 0.8 2.0 v v ol2 i ol = 400 a note 2 0.5 v output voltage, high v oh1 i oh = ? 1 ma note 2 4.5 v v dd 5.5 v v dd ? 1.0 v i oh = ? 100 a note 2 1.9 v v dd 5.5 v v dd ? 0.5 v input leakage current, i lil1 v i = 0 v except x1, x2, ? 3 a low xt1, xt2 i lil2 x1, x2, xt1, xt2 ? 20 a notes 1. p21, p23, p24, p26, p30 to p32, p35 to p37, p40 to p47, p50 to p57, p60 to p67, p71, p120 to p127 2. per pin 638 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud dc characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (2/3) parameter symbol conditions min. typ. max. unit input leakage current, i lih1 v i = v dd except x1, x2, 3 a high xt1, xt2 i lih2 x1, x2, xt1, xt2 20 a i lih3 v i = 12 v p90 to p95 20 a (n-ch open drain) output leakage current, low i lol1 v o = 0 v ? 3 a output leakage current, high i loh1 v o = v dd 3 a (1) pd78f4216a, 78f4216ay parameter symbol conditions min. typ. max. unit supply current i dd1 operation f xx = 12.5 mhz, v dd = 5.0 v 10% 17 40 ma mode f xx = 6 mhz, v dd = 3.0 v 10% 5 17 ma f xx = 2 mhz, v dd = 2.0 v 5% 2 10 ma i dd2 halt mode f xx = 12.5 mhz, v dd = 5.0 v 10% 6 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 10 ma f xx = 2 mhz, v dd = 2.0 v 5% 0.4 7 ma i dd3 idle mode f xx = 12.5 mhz, v dd = 5.0 v 10% 1 3 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.5 1.3 ma f xx = 2 mhz, v dd = 2.0 v 5% 0.3 0.9 ma i dd4 operation f xx = 32 khz, v dd = 5.0 v 10% 130 500 a mode note f xx = 32 khz, v dd = 3.0 v 10% 90 350 a f xx = 32 khz, 2.0 v v dd 2.7 v 80 300 a f xx = 32 khz, 1.9 v v dd < 2.0 v 70 250 a i dd5 halt f xx = 32 khz, v dd = 5.0 v 10% 60 200 a mode note f xx = 32 khz, v dd = 3.0 v 10% 20 160 a f xx = 32 khz, 2.0 v v dd 2.7 v 15 120 a f xx = 32 khz, 1.9 v v dd < 2.0 v 10 100 a i dd6 idle f xx = 32 khz, v dd = 5.0 v 10% 50 190 a mode note f xx = 32 khz, v dd = 3.0 v 10% 15 150 a f xx = 32 khz, 2.0 v v dd 2.7 v 12 110 a f xx = 32 khz, 1.9 v v dd < 2.0 v 7 90 a data retention voltage v dddr halt, idle modes 1.9 5.5 v data retention current i dddr stop mode v dd = 2.0 v 5% 2 10 a v dd = 5.0 v 10% 10 50 a pull-up resistor r l v i = 0 v 10 30 100 k ? note when the main system clock is stopped and subsystem clock is operating. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 639 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud d c characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (3/3) (2) pd78f4218a, 78f4218ay parameter symbol conditions min. typ. max. unit supply current i dd1 operation f xx = 12.5 mhz, v dd = 5.0 v 10% 19 40 ma mode f xx = 6 mhz, v dd = 3.0 v 10% 6 17 ma f xx = 3 mhz, v dd = 2.0 v 5% 2 10 ma i dd2 halt mode f xx = 12.5 mhz, v dd = 5.0 v 10% 7 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 10 ma f xx = 3 mhz, v dd = 2.0 v 5% 0.5 7 ma i dd3 idle mode f xx = 12.5 mhz, v dd = 5.0 v 10% 1 3 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.5 1.3 ma f xx = 3 mhz, v dd = 2.0 v 5% 0.3 0.9 ma i dd4 operation f xx = 32 khz, v dd = 5.0 v 10% 140 500 a mode note f xx = 32 khz, v dd = 3.0 v 10% 100 350 a f xx = 32 khz, 2.0 v v dd 2.7 v 90 300 a f xx = 32 khz, 1.9 v v dd < 2.0 v 80 250 a i dd5 halt f xx = 32 khz, v dd = 5.0 v 10% 60 200 a mode note f xx = 32 khz, v dd = 3.0 v 10% 20 160 a f xx = 32 khz, 2.0 v v dd 2.7 v 15 120 a f xx = 32 khz, 1.9 v v dd < 2.0 v 10 100 a i dd6 idle f xx = 32 khz, v dd = 5.0 v 10% 50 190 a mode note f xx = 32 khz, v dd = 3.0 v 10% 15 150 a f xx = 32 khz, 2.0 v v dd 2.7 v 12 110 a f xx = 32 khz, 1.9 v v dd < 2.0 v 7 90 a data retention voltage v dddr halt, idle modes 1.9 5.5 v data retention current i dddr stop mode v dd = 2.0 v 5% 2 10 a v dd = 5.0 v 10% 10 50 a pull-up resistor r l v i = 0 v 10 30 100 k ? note when the main system clock is stopped and subsystem clock is operating. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 640 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud ac characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/3) parameter symbol conditions min. typ. max. unit cycle time t cyk 4.5 v v dd 5.5 v 80 ns 2.7 v v dd < 4.5 v 160 ns 2.0 v v dd < 2.7 v 320 ns 1.9 v v dd < 2.0 v 500 ns address setup time t sast v dd = 5.0 v 10% (0.5 + a) t ? 20 ns (to astb ) v dd = 3.0 v 10% (0.5 + a) t ? 40 ns v dd = 2.0 v 5% (0.5 + a) t ? 80 ns address hold time t hstla v dd = 5.0 v 10% 0.5t ? 19 ns (from astb ) v dd = 3.0 v 10% 0.5t ? 24 ns v dd = 2.0 v 5% 0.5t ? 34 ns astb high-level width t wsth v dd = 5.0 v 10% (0.5 + a) t ? 17 ns v dd = 3.0 v 10% (0.5 + a) t ? 40 ns v dd = 2.0 v 5% (0.5 + a) t ? 110 ns address hold time t hra v dd = 5.0 v 10% 0.5t ? 14 ns (from rd ) v dd = 3.0 v 10% 0.5t ? 14 ns v dd = 2.0 v 5% 0.5t ? 14 ns delay time from address to t dar v dd = 5.0 v 10% (1 + a) t ? 24 ns rd v dd = 3.0 v 10% (1 + a) t ? 35 ns v dd = 2.0 v 5% (1 + a) t ? 80 ns address float time t far v dd = 5.0 v 10% 0 ns (from rd ) v dd = 3.0 v 10% 0 ns v dd = 2.0 v 5% 0 ns data input time from t daid v dd = 5.0 v 10% (2.5 + a + n) t ? 37 ns address v dd = 3.0 v 10% (2.5 + a + n) t ? 52 ns v dd = 2.0 v 5% (2.5 + a + n) t ? 120 ns data input time from astb t dstid v dd = 5.0 v 10% (2 + n) t ? 35 ns v dd = 3.0 v 10% (2 + n) t ? 50 ns v dd = 2.0 v 5% (2 + n) t ? 80 ns data input time from rd t drid v dd = 5.0 v 10% (1.5 + n) t ? 40 ns v dd = 3.0 v 10% (1.5 + n) t ? 50 ns v dd = 2.0 v 5% (1.5 + n) t ? 90 ns delay time from astb to t dstr v dd = 5.0 v 10% 0.5t ? 9ns rd v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 5% 0.5t ? 20 ns data hold time (from rd )t hrid v dd = 5.0 v 10% 0 ns v dd = 3.0 v 10% 0 ns v dd = 2.0 v 5% 0 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) 641 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (1) read/write operation (2/3) parameter symbol conditions min. typ. max. unit address active time from t dra v dd = 5.0 v 10% 0.5t ? 2ns rd v dd = 3.0 v 10% 0.5t ? 12 ns v dd = 2.0 v 5% 0.5t ? 35 ns delay time from rd t drst v dd = 5.0 v 10% 0.5t ? 9ns to astb v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 5% 0.5t ? 40 ns rd low-level width t wrl v dd = 5.0 v 10% (1.5 + n) t ? 25 ns v dd = 3.0 v 10% (1.5 + n) t ? 30 ns v dd = 2.0 v 5% (1.5 + n) t ? 25 ns address active time t dwa v dd = 5.0 v 10% 0.5t ? 2ns from wr v dd = 3.0 v 10% 0.5t ? 12 ns v dd = 2.0 v 5% 0.5t ? 35 ns delay time from t daw v dd = 5.0 v 10% (1 + a) t ? 24 ns address to wr v dd = 3.0 v 10% (1 + a) t ? 34 ns v dd = 2.0 v 5% (1 + a) t ? 70 ns address hold time t hwa v dd = 5.0 v 10% 0.5t ? 14 ns (from wr ) v dd = 3.0 v 10% 0.5t ? 14 ns v dd = 2.0 v 5% 0.5t ? 14 ns delay time from t dstod v dd = 5.0 v 10% 0.5t + 15 ns astb to data output v dd = 3.0 v 10% 0.5t + 30 ns v dd = 2.0 v 5% 0.5t + 240 ns delay time from wr t dwod v dd = 5.0 v 10% 0.5t ? 30 ns to data output v dd = 3.0 v 10% 0.5t ? 30 ns v dd = 2.0 v 5% 0.5t ? 30 ns delay time from astb t dstw v dd = 5.0 v 10% 0.5t ? 9ns to wr v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 5% 0.5t ? 20 ns data setup time (to wr )t sodwr v dd = 5.0 v 10% (1.5 + n) t ? 20 ns v dd = 3.0 v 10% (1.5 + n) t ? 25 ns v dd = 2.0 v 5% (1.5 + n) t ? 70 ns data hold time (from wr )t hwod v dd = 5.0 v 10% 0.5t ? 14 ns v dd = 3.0 v 10% 0.5t ? 14 ns v dd = 2.0 v 5% 0.5t ? 50 ns delay time from wr t dwst v dd = 5.0 v 10% 0.5t ? 9ns to astb v dd = 3.0 v 10% 0.5t ? 9ns v dd = 2.0 v 5% 0.5t ? 30 ns wr low-level width t wwl v dd = 5.0 v 10% (1.5 + n) t ? 25 ns v dd = 3.0 v 10% (1.5 + n) t ? 30 ns v dd = 2.0 v 5% (1.5 + n) t ? 30 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) 642 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (1) read/write operation (3/3) parameter symbol conditions min. typ. max. unit delay time from address t adexd v dd = 5.0 v 10% 0 ns to exa v dd = 3.0 v 10% 0 ns v dd = 2.0 v 5% 0 ns delay time from exa to t extah v dd = 5.0 v 10% 0.5t ? 20 ns astb v dd = 3.0 v 10% 0.5t ? 30 ns v dd = 2.0 v 5% 0.5t ? 40 ns delay time from rd to t exrds v dd = 5.0 v 10% 0 ns exa v dd = 3.0 v 10% 0 ns v dd = 2.0 v 5% 0 ns delay time from wr to t exwds v dd = 5.0 v 10% t ns exa v dd = 3.0 v 10% t ns v dd = 2.0 v 5% t ns delay time from exa to t exadr v dd = 5.0 v 10% 0.5t ns astb v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 5% 0.5t ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) 643 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (2) external wait timing (1/2) parameter symbol conditions min. typ. max. unit input time from address to t dawt v dd = 5.0 v 10% (2 + a) t ? 40 ns wait v dd = 3.0 v 10% (2 + a) t ? 60 ns v dd = 2.0 v 5% (2 + a) t ? 300 ns input time from astb to t dstwt v dd = 5.0 v 10% 1.5t ? 40 ns wait v dd = 3.0 v 10% 1.5t ? 60 ns v dd = 2.0 v 5% 1.5t ? 260 ns hold time from astb to t hstwt v dd = 5.0 v 10% (0.5 + n) t + 5 ns wait v dd = 3.0 v 10% (0.5 + n) t + 10 ns v dd = 2.0 v 5% (0.5 + n) t + 30 ns delay time from astb to t dstwth v dd = 5.0 v 10% (1.5 + n) t ? 40 ns wait v dd = 3.0 v 10% (1.5 + n) t ? 60 ns v dd = 2.0 v 5% (1.5 + n) t ? 90 ns input time from rd to t drwtl v dd = 5.0 v 10% t ? 40 ns wait v dd = 3.0 v 10% t ? 60 ns v dd = 2.0 v 5% t ? 70 ns hold time from rd to t hrwt v dd = 5.0 v 10% nt + 5 ns wait v dd = 3.0 v 10% nt + 10 ns v dd = 2.0 v 5% nt + 30 ns delay time from rd to t drwth v dd = 5.0 v 10% (1 + n) t ? 40 ns wait v dd = 3.0 v 10% (1 + n) t ? 60 ns v dd = 2.0 v 5% (1 + n) t ? 90 ns data input time from wait t dwtid v dd = 5.0 v 10% 0.5t ? 5ns v dd = 3.0 v 10% 0.5t ? 10 ns v dd = 2.0 v 5% 0.5t ? 30 ns delay time from wait to t dwtr v dd = 5.0 v 10% 0.5t ns rd v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 5% 0.5t + 5 ns delay time from wait to t dwtw v dd = 5.0 v 10% 0.5t ns wr v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 5% 0.5t + 5 ns input time from wr to t dwwtl v dd = 5.0 v 10% t ? 40 ns wait v dd = 3.0 v 10% t ? 60 ns v dd = 2.0 v 5% t ? 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) 644 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (2) external wait timing (2/2) parameter symbol conditions min. typ. max. unit hold time from wr to t hwwt v dd = 5.0 v 10% nt + 5 ns wait v dd = 3.0 v 10% nt + 10 ns v dd = 2.0 v 5% nt + 30 ns delay time from wr to t dwwth v dd = 5.0 v 10% (1 + n) t ? 40 ns wait v dd = 3.0 v 10% (1 + n) t ? 60 ns v dd = 2.0 v 5% (1 + n) t ? 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) n: number of wait states (n 0) 645 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (3) serial operation (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (1/2) (a) 3-wire serial i/o mode (sck: internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 4.5 v v dd 5.5 v 640 ns 2.7 v v dd < 4.5 v 1,280 ns 2.0 v v dd < 2.7 v 2,560 ns 1.9 v v dd < 2.0 v 4,000 ns sck high-/low-level t kh1 , 4.5 v v dd 5.5 v 270 ns width t kl1 2.7 v v dd < 4.5 v 590 ns 2.0 v v dd < 2.7 v 1,180 ns 1.9 v v dd < 2.0 v 1,900 ns si setup time (to sck )t sik1 2.7 v v dd 5.5 v 10 ns 1.9 v v dd < 2.7 v 30 ns si hold time (from sck ) t hik1 40 ns delay time from sck t dso1 30 ns to so output hold time from sck t hso1 t kcy1 /2 50 ns to so output (b) 3-wire serial i/o mode (sck: external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 4.5 v v dd 5.5 v 640 ns 2.7 v v dd < 4.5 v 1,280 ns 2.0 v v dd < 2.7 v 2,560 ns 1.9 v v dd < 2.0 v 4,000 ns sck high-/low-level t kh2 , 4.5 v v dd 5.5 v 320 ns width t kl2 2.7 v v dd < 4.5 v 640 ns 2.0 v v dd < 2.7 v 1,280 ns 1.9 v v dd < 2.0 v 2,000 ns si setup time (to sck )t sik2 2.7 v v dd 5.5 v 10 ns 1.9 v v dd < 2.7 v 30 ns si hold time (from sck ) t hik2 40 ns delay time from sck t dso2 30 ns to so output hold time from sck t hso2 t kcy2 /2 50 ns to so output (c) uart mode parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 4.5 v v dd 5.5 v 417 ns 2.7 v v dd < 4.5 v 833 ns 1.9 v v dd < 2.7 v 1,667 ns asck high-/low-level t kh3 , 4.5 v v dd 5.5 v 208 ns width t kl3 2.7 v v dd < 4.5 v 416 ns 1.9 v v dd < 2.7 v 833 ns 646 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (3) serial operation (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) (2/2) (d) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus free time (between stop t buf 4.7 ? 1.3 ? s and start conditions) hold time note 1 t hd : sta 4.0 ? 0.6 ? s low-level width of scl0 t low 4.7 ? 1.3 ? s clock high-level width of scl0 t high 4.0 ? 0.6 ? s clock setup time of start/restart t su : sta 4.7 ? 0.6 ? s conditions data hold when using t hd : dat 5.0 ??? s time cbus-compatible master when using i 2 c0 note 2 ? 0 note 2 0.9 note 3 s bus data setup time t su : dat 250 ? 100 note 4 ? ns rising time of sda0 and t r ? 1,000 20 + 0.1cb note 5 300 ns scl0 signals falling time of sda0 and t f ? 300 20 + 0.1cb note 5 300 ns scl0 signals setup time of stop condition t su : sto 4.0 ? 0.6 ? s pulse width of spike t sp ?? 050ns restricted by input filter load capacitance of each cb ? 400 ? 400 pf bus line notes 1. for the start condition, the first clock pulse is generated after the hold time. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to provide an internal sda0 signal (on v ihmin. ) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low-level hold time (t low ), only the maximum data hold time t hd : dat needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in a standard mode i 2 c bus system. in this case, the conditions described below must be satisfied. ? if the device does not extend the scl0 signal low-level hold time t su : dat 250 ns ? if the device extends the scl0 signal low-level hold time be sure to transmit the data bit to the sda0 line before the scl0 line is released (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns by standard mode i 2 c bus specification) 5. cb: total capacitance per bus line (unit: pf) 647 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (4) clock output operation (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit pcl cycle time t cycl 4.5 v v dd 5.5 v, nt 80 31,250 ns pcl high-/low-level t cll , 4.5 v v dd 5.5 v, 0.5t ? 10 30 15,615 ns width t clh pcl rise/fall time t clr , 4.5 v v dd 5.5 v 5 ns t clf 2.7 v v dd < 4.5 v 10 ns 1.9 v v dd < 2.7 v 20 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) n: divided frequency ratio set by software in the cpu ? when using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 ? when using the subsystem clock: n = 1 (5) other operations (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit nmi high-/low-level t wnil ,10 s width t wnih intp input high-/low- t witl , intp0 to intp6 100 ns level width t with reset high-/low-level t wrsl ,10 s width t wrsh 648 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud a/d converter characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error notes 1, 2 2.7 v v dd 5.5 v, 1.2 %fsr 2.2 v av ref0 v dd , av dd = v dd 1.9 v v dd < 2.7 v, 1.6 %fsr 1.9 v av ref0 v dd , av dd = v dd conversion time t conv 14 144 s sampling time t samp 24/f xx s analog input voltage v ian av ss av ref0 v reference voltage av ref0 1.9 av dd v resistance between r avref0 when not a/d converting 40 k ? av ref0 and av ss notes 1. quantization error ( 1/2 lsb) is not included. 2. overall error is indicated as a ratio to the full-scale value (%fsr). remark f xx : main system clock frequency d/a converter characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error notes 1, 2 r = 10 m ? , 2.0 v av ref1 v dd , 0.6 %fsr 2.0 v v dd 5.5 v, av dd = v dd r = 10 m ? , 1.9 v av ref1 v dd , 1.2 %fsr 1.9 v v dd 2.0 v, av dd = v dd settling time load conditions: 4.5 v av ref1 5.5 v 10 s c = 30 pf 2.7 v av ref1 < 4.5 v 15 s 1.9 v av ref1 < 2.7 v 20 s output resistance r o dacs0, 1 = 55h 8 k ? reference voltage av ref1 1.9 v dd v av ref1 current ai ref1 for only 1 channel 2.5 ma notes 1. quantization error ( 1/2 lsb) is not included. 2. overall error is indicated as a ratio to the full-scale value (%fsr). 649 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud flash memory programming characteristics (t a = 10 to 40 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit operating frequency f xx 4.5 v v dd 5.5 v 2 12.5 mhz 2.7 v v dd < 4.5 v 2 6.25 mhz 2.0 v v dd < 2.7 v 2 3.125 mhz 1.9 v v dd < 2.0 v 2 2 2 mhz oscillation f x 4.5 v v dd 5.5 v 4 25 mhz frequency note 1 2.7 v v dd < 4.5 v 4 12.5 mhz 2.0 v v dd < 2.7 v 4 6.25 mhz 1.9 v v dd < 2.0 v 4 4 4 mhz supply voltage note 2 v dd 1.9 5.5 v v ppl when detecting v pp low level 0 0.2v dd v v pp when detecting v pp high level 0.9v dd 1.1v dd v v pph when detecting v pp high voltage 9.7 10 10.3 v write time c wrt 20 note 3 times operating temperature note 4 t a 40 85 c storage temperature note 5 t stg 65 125 c programming t prg 10 40 c temperature notes 1. when rewriting without using handshake mode 2. pd78f4216a, 78f4216ay rank k: 2.7 v v dd 5.5 v, v pp = 10.3 0.3 v rank e: 2.7 v v dd 5.5 v, v pp = 10.0 0.3 v 3. operation cannot be guaranteed when the number of rewrites exceeds 20. in the case of k rank of the pd78f4216a and 78f4216ay, operation cannot be guaranteed when the number of rewrites exceeds 5. 4. pd78f4216a, 78f4216ay rank k: t a = ? 10 to +60 c 5. pd78f4216a, 78f4216ay rank k: t a = ? 10 to +80 c cautions 1. if writing is not successful in the initial write operation, execute the program command again, and then execute the verify command to confirm that the write operation has been completed normally (k, e, and p ranks of the pd78f4216a and 78f4216ay). 2. handshake mode is supported by products as shown below. ? pd78f4216a, 78f4216ay: products with other than rank k, e ? pd78f4218a, 78f4218ay: products with any rank remarks 1. the fifth letter from the left in the lot number indicates the standard of the product. 2. after executing the program command, execute the verify command to confirm that the write operation has been completed normally. 3. handshake mode is the csi write mode that uses p24. handshake mode can be used with the pg- fr3 and fl-pr3. 4. rank i only applies to es (engineering sample) products. because these products are engineering samples, their operation cannot be guaranteed. 650 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (2) write erase characteristics parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xx = 12.5 mhz 40 ma v pp supply current i pp when v pp = v pp2 100 ma step erase time t er note 1 0.2 s overall erase time per t era when step erase time = 0.2 s note 2 20 s/area area write-back time t wb note 3 50 ms number of write-backs c wb when write-back time = 50 ms note 4 60 times/ per write-back command write- back command number of erase/ c erwb 16 times write-backs step write time t wr note 5 50 s overall write time per t wrw when step write time = 50 s 50 500 s/ word (1 word = 1 byte) note 6 word number of rewrites per c erwr 1 erase + 1 write after erase = 1 rewrite note 7 20 times/ area area notes 1. the recommended setting value for the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (write-back time) is not included. 3. the recommended setting value for the write-back time is 50 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the retry times must be the maximum value minus the number of commands issued. 5. the recommended step write time setting value is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. the range of the operating clock during flash memory programming is the same as the range during normal operation. 2. when using the pg-fp3, the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. unless otherwise directed, do not change the set values. 651 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud data retention characteristics (t a = ? ? ? ? ? 40 to +85 c, v dd = av dd = 1.9 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.9 5.5 v data retention current i dddr v dddr = 5.0 v 10% 10 50 a v dddr = 2.0 v 5% 2 10 a v dd rise time t rvd 200 s v dd fall time t fvd 200 s v dd hold time (from t hvd 0ms stop mode setting) stop release signal t drel 0ms input time oscillation stabilization t wait crystal resonator 30 ms wait time ceramic resonator 5 ms low-level input voltage v il reset, p00/intp0 to p06/intp6 0 0.1v dddr v high-level input voltage v ih 0.9v dddr v dddr v ac timing test points 0.8v dd or 1.9 v 0.8 v 0.8v dd or 1.9 v 0.8 v points of test v dd 1 v 0.45 v 652 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud timing waveforms (1) read operations remark the signal is output from pins a0 to a7 when p80 to p87 are unused. wait (input) (clk) a8 to a19 (output) astb (output) rd (output) exa ad0 to ad7 (i/o) t cyk higher address hi-z hi-z hi-z higher address a0 to a7 (output) lower address lower address data (input) lower address (output) lower address (output) t daid t hra t sast t wsth t dstr t drst t dar t drid t wrl t drwth t dstwt t dstwth t hstwt t hrwt t dawt t dwtr t hstla t far t dwtid t drwtl t hrid t dra t dstid t extah t exadr t exrds t adexd 653 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud (2) write operation remark the signal is output from pins a0 to a7 when p80 to p87 are unused. wait (input) wr (output) (clk) a8 to a19 (output) astb (output) ad0 to ad7 (output) t cyk higher address higher address a0 to a7 (output) lower address lower address data (output) lower address (output) lower address (output) t daid t hwa t sast t wsth t dstw t dwst t daw t dwod t wwl t dwwth t dstwt t dstwth t hstwt t hwwt t dawt t dwtw t hstla t far t dwtid t dwwtl t hwod t dwa t dstod t sodwr hi-z hi-z hi-z exa t extah t exadr t exwds t adexd 654 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud serial operation (1) 3-wire serial i/o mode (2) uart mode (3) i 2 c bus mode ( pd78f4216ay, 78f4218ay subseries only) sck so si output data input data t kcy1, 2 t kh1, 2 t kl1, 2 t hso1, 2 t sik1, 2 t dso1, 2 t hik1, 2 asck t kcy3 t kh3 t kl3 scl0 sda0 t hd : sta t buf t hd : dat t high t f t su : dat t su : sta t hd : sta t sp t su : sto t r stop condition start condition stop condition restart condition 655 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud clock output timing interrupt input timing reset input timing clkout t clh t cll t cycl t clf t clr nmi intp0 to intp6 t wnih t wnil t with t witl reset t wrsh t wrsl 656 chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) user s manual u13570ej3v0ud xt1 t xth t xtl 1/f xt x1 t wxh t wxl 1/f x t xf t xr v dd reset nmi (cleared by falling edge) nmi (cleared by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait clock timing data retention characteristics 657 user s manual u13570ej3v0ud chapter 32 package drawings remark the external dimensions and material of the es version are the same as those of the mass-produced version. 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 32 package drawings 658 user s manual u13570ej3v0ud 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m 0.15 + 0.10 ? 0.05 c d a b s remark the external dimensions and material of the es version are the same as those of the mass-produced version. 659 user? manual u13570ej3v0ud chapter 33 recommended soldering conditions the pd784218a subseries products should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 33-1. surface mounting type soldering conditions (1/2) (1) pd784214agc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784215agc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784216agc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784214aygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784215aygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784216aygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (2) pd784217agc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784218agc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784217aygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd784218aygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd78f4216agc-8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd78f4218agc-8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd78f4216aygc-8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) pd78f4218aygc-8eu: 100-pin plastic lqfp (fine pitch) (14 x 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). chapter 33 recommended soldering conditions 660 user? manual u13570ej3v0ud table 33-1. surface mounting type soldering conditions (2/2) (3) pd784214agf- -3ba: 100-pin plastic qfp (14 x 20) pd784215agf- -3ba: 100-pin plastic qfp (14 x 20) pd784216agf- -3ba: 100-pin plastic qfp (14 x 20) pd784217agf- -3ba: 100-pin plastic qfp (14 x 20) pd784218agf- -3ba: 100-pin plastic qfp (14 x 20) pd784214aygf- -3ba: 100-pin plastic qfp (14 x 20) pd784215aygf- -3ba: 100-pin plastic qfp (14 x 20) pd784216aygf- -3ba: 100-pin plastic qfp (14 x 20) pd784217aygf- -3ba: 100-pin plastic qfp (14 x 20) pd784218aygf- -3ba: 100-pin plastic qfp (14 x 20) pd78f4216agf-3ba: 100-pin plastic qfp (14 x 20) pd78f4216aygf-3ba: 100-pin plastic qfp (14 x 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (4) pd78f4218agf-3ba: 100-pin plastic qfp (14 x 20) pd78f4218aygf-3ba: 100-pin plastic qfp (14 x 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-207-2 (at 210 c or higher), count: two times or less, expose limit: 7 days note (after that, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-207-2 (at 200 c or higher), count: two times or less, expose limit: 7 days note (after that, prebake at 125 c for 20 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-207-1 preheating temperature: 120 c max. (package surface temperature), expose limit: 7 days note (after that, prebake at 125 c for 20 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark the label on the dry pack was correct originally. 661 user s manual u13570ej3v0ud appendix a major differences from pd78078y subseries item cpu minimum instruction execution time memory space i/o port pins with added functions note timer/counters serial interface interrupts standby function package pd784218ay subseries 16-bit cpu 160 ns (at 12.5 mhz operation) 61 s (at 32.768-khz operation) 1 mb 86 8 72 6 70 22 6 16-bit timer/counter 1 unit 8-bit timer/counter 6 units ? uart/ioe (3-wire serial i/o) 2 channels ? csi (3-wire serial i/o, multi- master compatible i 2 c bus) 1 channel yes yes yes 4 levels halt/stop/idle mode in low power consumption mode: halt or idle mode ? 100-pin plastic lqfp (fine pitch) (14 14) ? 100-pin plastic qfp (14 20) pd78078y subseries 8-bit cpu 400 ns (at 5.0 mhz operation) 122 s (at 32.768-khz operation) 64 kb 88 2 78 8 86 16 8 16-bit timer/counter 1 unit 8-bit timer/counter 4 units uart/ioe (3-wire serial i/o) 1 channel ? csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus) 1 channel csi (3-wire serial i/o, 3-wire serial i/o with automatic communication function) 1 channel no no no no halt/stop mode ? 100-pin plastic lqfp (fine pitch) (14 14) ? 100-pin plastic qfp (14 20) 100-pin ceramic wqfn (14 20) (only pd78p078y) series name when the main system clock is selected when the subsystem clock is selected total cmos inputs cmos i/o n-channel open drain i/o pins with pull-up resistors led direct drive outputs medium voltage pins nmi pin macro service context switching programmable priority note the pins with added functions are included in the i/o pins. 662 user s manual u13570ej3v0ud appendix b development tools the following development tools are available for the development of systems that employ pd784218a subseries products. ? for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatible machines can be used for the pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatible machines. for windows unless otherwise specified, ?indows?indicates the following oss. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt ver. 4.0 663 appendix b development tools user s manual u13570ej3v0ud figure b-1. development tool configuration (1/2) (1) when using the in-circuit emulator ie-78k4-ns system simulator integrated debugger device file embedded software real-time os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator power supply unit emulation probe conversion socket or conversion adapter target system host machine (pc) interface adapter, pc card interface, etc. emulation board on-chip flash memory version flash memory write environment flash programmer 664 appendix b development tools user s manual u13570ej3v0ud figure b-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-784000-r remark items in broken line boxes differ according to the development environment. refer to b.3.1 hardware . system simulator integrated debugger device file embedded software real-time os debugging tool assembler package c compiler package c library source file device file language processing software flash memory write adapter in-circuit emulator emulation probe conversion socket or conversion adapter target system host machine (pc or ews) interface board interface adapter emulation board i/o emulation board probe board emulation probe conversion board on-chip flash memory version flash memory write environment flash programmer 665 appendix b development tools user s manual u13570ej3v0ud b.1 language processing software sp78k4 78k/iv series software package ra78k4 assembler package cc78k4 c compiler package df784218 note device file cc78k4-l c library source file note the df784218 can be used in common with the ra78k4, cc78k4, sm78k4, id78k4-ns, and id78k4. development tools (software) common to the 78k/iv series are combined in this package. part number: s sp78k4 this assembler converts programs written in mnemonics into object code executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optional device file (df784218). 666 appendix b development tools user s manual u13570ej3v0ud remark the part number differs depending on the host machine and operating system used. s sp78k4 host machine os supply medium ab17 pc-9800 series, japanese windows cd-rom bb17 ibm pc/at compatibles english windows s ra78k4 s cc78k4 host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at compatibles english windows ab17 japanese windows cd-rom bb17 english windows 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df784218 s cc78k4-l host machine os supply medium ab13 pc-9800 series, japanese windows 3.5-inch 2hd fd bb13 ibm pc/at compatibles english windows 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt b.2 flash memory writing tools flashpro iii (type fl-pr3, pg-fp3) flash programmer fa-100gc fa-100gf flash memory writing adapter remark fl-pr2, fl-pr3, fa-100gc, and fa-100gf are products of naito densei machida mfg. co., ltd. phone: +81-45-475-4191 naito densei machida mfg. co., ltd. flash programmer dedicated to microcontrollers with on-chip flash memory. flash memory writing adapter used connected to the flashpro iii. fa-100gc: 100-pin plastic lqfp (fine pitch) (gc-8eu type) fa-100gf: 100-pin plastic qfp (gf-3ba type) 667 appendix b development tools user s manual u13570ej3v0ud b.3 debugging tools b.3.1 hardware (1/2) (1) when using the in-circuit emulator ie-78k4-ns ie-78k4-ns in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if interface adapter ie-784225-ns-em1 emulation board np-100gc np-h100gc-tq emulation tgc-100sdw conversion probe adapter (refer to figures b-3 and b-4 ) np-100gf-tq np-h100gf-tq emulation tgf-100rbp probe conversion adapter (refer to figures b-5 and b-6 ) remarks 1. np-100gc, np-h100gc-tq, np-100gf-tq, and np-h100gf-tq are products of naito densei machida mfg. co., ltd. phone: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgc-100sdw and tgf-100rbp are products of tokyo eletech corporation. phone: +81-3-3820-7112 tokyo electronics department +81-6-6244-6672 osaka electronics department 3. tgc-100sdw and tgf-100rbp are sold in one units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/iv series product. it corresponds to integrated debugger (id78k4-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this adapter is used for supplying power from a receptacle of 100-v to 240-v ac. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78k4-ns host machine (c bus supported). this pc card and interface cable is required when using a notebook-type computer as the ie-78k4-ns host machine (pcmcia socket supported). this adapter is required when using the ibm pc/at compatible computers as the ie- 78k4-ns host machine (isa bus supported). this adapter is required when using a computer that incorporates a pci bus as the ie-78k4-ns host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic lqfp (fine pitch) (gc-8eu type). this conversion adapter connects the np-100gc or np-h100gc-tq to the target system board designed to mount a 100-pin plastic lqfp (fine pitch) (gc-8eu type). this probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic qfp (gf-3ba type). this conversion adapter connects the np-100gf-tq or np-h100gf-tq to the target system board designed to mount a 100-pin plastic qfp (gf-3ba type). 668 appendix b development tools user s manual u13570ej3v0ud b.3.1 hardware (2/2) (2) when using the in-circuit emulator ie-784000-r ie-784000-r in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-70000-pci-if interface adapter ie-78000-r-sv3 interface adapter ie-784000-r-em ie-784225-ns-em1 ie-784218-r-em1 emulation board ie-78k4-r-ex3 emulation probe conversion board ep-78064gc-r emulation probe tgc-100sdw conversion adapter (refer to figure b-9 ) ep-784218gf-r emulation probe ev-9200gf-100 conversion socket (refer to figures b-7 and b-8 ) remarks 1. tgc-100sdw is a product of tokyo eletech corporation. phone: +81-3-3820-7112 tokyo electronics department +81-6-6244-6672 osaka electronics department 2. ev-9200gf-100 is sold in five units. 3. tgc-100sdw is sold in one units. ie-784000-r is an in-circuit emulator that can be used with the 78k/iv series. ie- 784000-r can be used with the optional ie-784000-r-em, ie-784225-ns-em1, or ie- 784218-r-em1 emulation boards, that are sold separately. the host machine is connected in order to debug. the integrated debugger (id78k4) and the device files that are sold separately are required. by using this in-circuit emulator in combination with them, debugging is possible at the source program levels of the c language and the structured assembly language. debugging and program inspection have better efficiency than the c0 coverage function. ie-784000-r can be connected to the host machine by ethernet or a dedicated bus. a separately sold interface adapter is required. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-784000-r host machine (c bus supported). this adapter is required when using an ibm pc/at or compatible computer as the ie-784000-r host machine (isa bus supported). this adapter is required when using a computer that incorporates a pci bus as the ie-784000-r host machine. this adapter and cable is required when using an ews computer as the ie-784000- r host machine, and is used connected to the board in the ie-784000-r. 10base-5 is supported for ethernet. for other methods, a conversion adapter commercially available is required. this emulation board is used with the 78k/iv series. this board emulates the operations of the peripheral hardware peculiar to a device. this conversion board for 100-pin is required when using the ie-784225-ns-em1 on the ie-784000-r. it is not required when using the conventional ie-784218-r-em1. this probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic lqfp (fine pitch) (gc-8eu type). this conversion adapter connects the ep-78064gc-r to the target system board designed to mount a 100-pin plastic lqfp (fine pitch) (gc-8eu type). this probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic qfp (gf-3ba type). this conversion socket connects the ep-784218gf-r to the target system board designed to mount a 100-pin plastic qfp (gf-3ba type). 669 appendix b development tools user s manual u13570ej3v0ud b.3.2 software sm78k4 this system simulator is used to perform debugging at c source level or assembler system simulator level while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k4 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. the sm78k4 should be used in combination with an optional device file (df784218). part number: s sm78k4 id78k4-ns this debugger is a control program to debug 78k/iv series integrated debugger microcontrollers. (supporting in-circuit emulator it adopts a graphical user interface, which is equivalent visually and operationally to ie-78k4-ns) windows. it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-language level by using the window integration function which links a trace result with its source program, id78k4 disassembled display, and memory display. in addition, by incorporating function integrated debugger modules such as task debugger and system performance analyzer, the efficiency of (supporting in-circuit emulator debugging programs, which run on real-time oss can be improved. ie-784000-r) it should be used in combination with the optional device file (df784218). part number: s id78k4-ns, s id78k4 remark in the part number differs depending on the host machine and os used. s sm78k4 s id78k4-ns s id78k4 host machine os supply medium ab13 ibm pc/at compatible japanese windows 3.5-inch 2hc fd bb13 english windows ab17 japanese windows cd-rom bb17 english windows 670 appendix b development tools user s manual u13570ej3v0ud b.4 cautions on designing target system the following shows the conditions when connecting the emulation probe to the conversion adapter. follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. among the products described in this appendix, np-100gc, np-h100gc-tq, np-100gf-tq, and np-h100gf-tq are products of naito densei machida mfg. co., ltd., and tgc-100sdw and tgf-100rbp are products of tokyo eletech corporation. table b-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-100gc tgc-100sdw 170 mm np-h100gc-tq 370 mm np-100gf-tq tgf-100rbp 170 mm np-h100gf-tq 370 mm figure b-2. distance between ie system and conversion adapter note distance when the np-100gc or np-100gf-tq is used. when the np-h100gc-tq or np-h100gf-tq is used, the distance is 370 mm. 170 mm note in-circuit emulator ie-78k4-ns emulation board ie-784225-ns-em1 conversion adapter: tgc-100sdw tgf-100rbp target system cn2 emulation probe np-100gc, np-h100gc-tq, np-100gf-tq, np-h100gf-tq cn1 671 appendix b development tools user s manual u13570ej3v0ud figure b-3. connection conditions of target system (when np-100gc is used) figure b-4. connection conditions of target system (when np-h100gc-tq is used) emulation probe np-100gc 23 mm 25 mm 40 mm 34 mm target system connection adapter tgc-100sdw 21.55 mm pin 1 11 mm emulation board ie-784225-ns-em1 21.55 mm emulation probe np-h100gc-tq emulation board ie-784225-ns-em1 23 mm 42 mm 45 mm target system 11 mm conversion adapter tgc-100sdw 25 mm 21.55 mm pin 1 21.55 mm 672 appendix b development tools user s manual u13570ej3v0ud figure b-5. connection conditions of target system (when np-100gf-tq is used) figure b-6. connection conditions of target system (when np-h100gf-tq is used) emulation probe np-100gf-tq 40 mm 34 mm target system connection adapter tgf-100rbp 27.5 mm pin 1 11 mm emulation board ie-784225-ns-em1 21 mm emulation probe np-h100gf-tq emulation board ie-784225-ns-em1 42 mm 45 mm target system 11 mm conversion adapter tgc-100rbp 27.5 mm pin 1 21 mm 673 appendix b development tools user s manual u13570ej3v0ud b.5 conversion socket (ev-9200gf-100) and conversion adapter (tgc-100sdw) (1) package drawing of the conversion socket (ev-9200gf-100) and recommended footprint ep-784218gf-r is mounted together on the board. figure b-7. package drawing of ev-9200gf-100 (reference) ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0e item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014 0.091 0.059 674 appendix b development tools user s manual u13570ej3v0ud figure b-8. recommended footprint of ev-9200gf-100 (reference) f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p1e item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 +0.001 ?.002 g caution dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mount manual" website (http://www.necel.com/pkg/en/mount/index.html). 675 appendix b development tools user s manual u13570ej3v0ud item millimeters inches b 1.850.25 0.0730.010 c 3.5 0.138 a 14.45 0.569 d 2.0 0.079 h 16.0 0.630 i 1.1250.3 0.0440.012 j 0~5 0.000~0.197 e 3.9 0.154 f0.25 g 4.5 0.177 tgc-100sdw-g1e 0.010 k 5.9 0.232 l 0.8 0.031 m 2.4 0.094 n 2.7 0.106 item millimeters inches b 0.5x24=12 0.020x0.945=0.472 c 0.5 0.020 a 21.55 0.848 d 0.5x24=12 0.020x0.945=0.472 h 10.9 0.429 i 13.3 0.524 j 15.7 0.618 e 15.0 0.591 f 21.55 g 3.55 0.140 0.848 k 18.1 0.713 l 13.75 0.541 m 0.5x24=12.0 0.020x0.945=0.472 q 10.0 0.394 r 11.3 0.445 s 18.1 0.713 n 1.1250.3 0.0440.012 o 1.1250.2 p 7.5 0.295 0.0440.008 w 1.8 0.071 x c 2.0 c 0.079 y 0.9 0.035 t 5.0 0.197 u5.0 v 4- 1.3 4- 0.051 0.197 z 0.3 0.012 ? ? h a b c i j k g f e d n o l m x p q r s u protrusion height w v k i m n z j g i h a e d c b y f x t note : product by tokyo eletech corporation. (2) package drawing of the conversion adapter (tgc-100sdw) np-100gc, np-h100gc-tq, or ep-78064gc-r is mounted together on the board. figure b-9. package drawing of tgc-100sdw (reference) 676 user s manual u13570ej3v0ud appendix c embedded software for efficient development and maintenance of the pd784218a subseries, the following embedded products are available. rx78k4 rx78k4 is a real-time os conforming to the itron specifications. real-time os tool (configurator) for generating nucleus of rx78k4 and plural information tables is supplied. used in combination with an optional assembler package (ra78k4) and device file (df784218). 677 user s manual u13570ej3v0ud appendix d register index d.1 register index (alphabetical order) [symbols] 16-bit capture/compare register 00 (cr00) ............................................................................................................. 162 16-bit capture/compare register 01 (cr01) ............................................................................................................. 163 16-bit timer counter 0 (tm0) ............................................................................................................................... ...... 161 16-bit timer mode control register (tmc0) .............................................................................................................. 164 16-bit timer output control register (toc0) ............................................................................................................. 167 8-bit compare register 10 (cr10) ............................................................................................................................ 195 8-bit compare register 20 (cr20) ............................................................................................................................ 195 8-bit compare register 50 (cr50) ............................................................................................................................ 216 8-bit compare register 60 (cr60) ............................................................................................................................ 216 8-bit compare register 70 (cr70) ............................................................................................................................ 237 8-bit compare register 80 (cr80) ............................................................................................................................ 237 8-bit timer counter 1 (tm1) ............................................................................................................................... ........ 195 8-bit timer counter 2 (tm2) ............................................................................................................................... ........ 195 8-bit timer counter 5 (tm5) ............................................................................................................................... ........ 216 8-bit timer counter 6 (tm6) ............................................................................................................................... ........ 216 8-bit timer counter 7 (tm7) ............................................................................................................................... ........ 237 8-bit timer counter 8 (tm8) ............................................................................................................................... ........ 237 8-bit timer mode control register 1 (tmc1) ............................................................................................................. 196 8-bit timer mode control register 2 (tmc2) ............................................................................................................. 196 8-bit timer mode control register 5 (tmc5) ............................................................................................................. 217 8-bit timer mode control register 6 (tmc6) ............................................................................................................. 217 8-bit timer mode control register 7 (tmc7) ............................................................................................................. 238 8-bit timer mode control register 8 (tmc8) ............................................................................................................. 238 [a] a/d conversion result register (adcr) .................................................................................................................... 268 a/d converter input selection register (adis) ......................................................................................................... 271 a/d converter mode register (adm) ........................................................................................................................ 269 asynchronous serial interface mode register 1 (asim1) ............................................................................... 296, 303 asynchronous serial interface mode register 2 (asim2) ............................................................................... 296, 303 asynchronous serial interface status register 1 (asis1) ............................................................................... 298, 304 asynchronous serial interface status register 2 (asis2) ............................................................................... 298, 304 [b] baud rate generator control register 1 (brgc1) ............................................................................................ 299, 305 baud rate generator control register 2 (brgc2) ............................................................................................ 299, 305 [c] capture/compare control register 0 (crc0) ............................................................................................................ 167 clock output control register (cks) ................................................................................................................ 390, 393 clock status register (pcs) ............................................................................................................................... ....... 108 678 appendix d register index user s manual u13570ej3v0ud [d] d/a conversion setting register 0 (dacs0) ............................................................................................................. 284 d/a conversion setting register 1 (dacs1) ............................................................................................................. 284 d/a converter mode register 0 (dam0) ................................................................................................................... 285 d/a converter mode register 1 (dam1) ................................................................................................................... 285 [e] external access status enable register (exae) ...................................................................................................... 510 external bus type selection register (ebts) ........................................................................................................... 478 external interrupt falling edge enable register (egn0) ........................................................................................... 395 external interrupt rising edge enable register (egp0) ............................................................................................ 395 [i] i 2 c bus control register (iicc0) ............................................................................................................................... . 334 i 2 c bus status register (iics0) ............................................................................................................................... .. 339 in-service priority register (ispr) ............................................................................................................................. 41 0 internal memory size switching register (ims) .......................................................................................................... 78 interrupt mask register 0h (mk0h) .......................................................................................................................... 408 interrupt mask register 0l (mk0l) ........................................................................................................................... 408 interrupt mask register 1h (mk1h) .......................................................................................................................... 408 interrupt mask register 1l (mk1l) ........................................................................................................................... 408 interrupt mode control register (imc) ...................................................................................................................... 411 interrupt selection control register (snmi) ............................................................................................................... 413 [m] macro service mode register ............................................................................................................................... ..... 440 memory expansion mode register (mm) .................................................................................................................. 477 [o] oscillation mode selection register (cc) ................................................................................................................. 107 oscillation stabilization time specification register (osts) ........................................................................... 109, 520 [p] port 0 (p0) ............................................................................................................................... .................................. 120 port 0 mode register (pm0) ............................................................................................................................... ....... 142 port 1 (p1) ............................................................................................................................... .................................. 122 port 10 (p10) ............................................................................................................................... .............................. 139 port 10 mode register (pm10) ............................................................................................................................... ... 142 port 12 (p12) ............................................................................................................................... .............................. 140 port 12 mode register (pm12) ............................................................................................................................... ... 142 port 13 (p13) ............................................................................................................................... .............................. 141 port 13 mode register (pm13) ............................................................................................................................... ... 142 port 2 (p2) ............................................................................................................................... .................................. 123 port 2 mode register (pm2) ..................................................................................................................... 142, 391, 394 port 3 (p3) ............................................................................................................................... .................................. 127 port 3 mode register (pm3) ............................................................................................................................... ....... 142 port 4 (p4) ............................................................................................................................... .................................. 129 port 4 mode register (pm4) ............................................................................................................................... ....... 142 679 appendix d register index user s manual u13570ej3v0ud port 5 (p5) ............................................................................................................................... .................................. 130 port 5 mode register (pm5) ............................................................................................................................... ....... 142 port 6 (p6) ............................................................................................................................... .................................. 131 port 6 mode register (pm6) ............................................................................................................................... ....... 142 port 7 (p7) ............................................................................................................................... .................................. 134 port 7 mode register (pm7) ............................................................................................................................... ....... 142 port 8 (p8) ............................................................................................................................... .................................. 137 port 8 mode register (pm8) ............................................................................................................................... ....... 142 port 9 (p9) ............................................................................................................................... .................................. 138 port 9 mode register (pm9) ............................................................................................................................... ....... 142 port function control register (pf2) .......................................................................................................................... 147 prescaler mode register 0 (prm0) .......................................................................................................................... 169 prescaler mode register 1 (prm1) .......................................................................................................................... 199 prescaler mode register 2 (prm2) .......................................................................................................................... 199 prescaler mode register 5 (prm5) .......................................................................................................................... 220 prescaler mode register 6 (prm6) .......................................................................................................................... 220 prescaler mode register 7 (prm7) .......................................................................................................................... 241 prescaler mode register 8 (prm8) .......................................................................................................................... 241 prescaler mode register for serial clock (sprm0) .................................................................................................. 342 program status word (psw) .............................................................................................................................. 8 0, 414 programmable wait control register 1 (pwc1) ........................................................................................................ 478 pull-up resistor option register 0 (pu0) ................................................................................................................... 145 pull-up resistor option register 10 (pu10) ............................................................................................................... 145 pull-up resistor option register 12 (pu12) ............................................................................................................... 145 pull-up resistor option register 2 (pu2) ................................................................................................................... 145 pull-up resistor option register 3 (pu3) ................................................................................................................... 145 pull-up resistor option register 7 (pu7) ................................................................................................................... 145 pull-up resistor option register 8 (pu8) ................................................................................................................... 145 pull-up resistor option register (puo) ...................................................................................................................... 145 [r] real-time output buffer register h (rtbh) .............................................................................................................. 151 real-time output buffer register l (rtbl) ............................................................................................................... 151 real-time output port control register (rtpc) ......................................................................................................... 153 real-time output port mode register (rtpm) .......................................................................................................... 152 receive buffer register 1 (rxb1) ............................................................................................................................. 29 5 receive buffer register 2 (rxb2) ............................................................................................................................. 29 5 receive shift register 1 (rx1) ............................................................................................................................... ... 295 receive shift register 2 (rx2) ............................................................................................................................... ... 295 rom correction address register h (corah) ........................................................................................................ 563 rom correction address register l (coral) .......................................................................................................... 563 rom correction control register (corc) ................................................................................................................. 563 [s] serial i/o shift register 0 (sio0) .............................................................................................................................. 3 24 serial i/o shift register 1 (sio1) .............................................................................................................................. 3 18 serial i/o shift register 2 (sio2) .............................................................................................................................. 3 18 serial operation mode register 0 (csim0) .............................................................................................. 325, 327, 328 680 appendix d register index user s manual u13570ej3v0ud serial operation mode register 1 (csim1) .............................................................................................. 319, 320, 321 serial operation mode register 2 (csim2) .............................................................................................. 319, 320, 321 serial shift register (iic0) ............................................................................................................................... . 333, 344 slave address register (sva0) ........................................................................................................................ 333, 344 standby control register (stbc) ..................................................................................................................... 105, 517 [t] transmit shift register 1 (txs1) ............................................................................................................................... 295 transmit shift register 2 (txs2) ............................................................................................................................... 295 [w] watch timer mode control register (wtm) .............................................................................................................. 257 watchdog timer mode register (wdm) ........................................................................................................... 262, 412 681 appendix d register index user s manual u13570ej3v0ud d.2 register index (symbols) [a] adcr: a/d conversion result register ................................................................................................................. 268 adic: interrupt control register .......................................................................................................................... 407 adis: a/d converter input selection register ..................................................................................................... 271 adm: a/d converter mode register ................................................................................................................... 269 asim1: asynchronous serial interface mode register 1 ............................................................................. 296, 303 asim2: asynchronous serial interface mode register 2 ............................................................................. 296, 303 asis1: asynchronous serial interface status register 1 ............................................................................ 298, 304 asis2: asynchronous serial interface status register 2 ............................................................................ 298, 304 [b] brgc1: baud rate generator control register 1 ............................................................................................ 299, 305 brgc2: baud rate generator control register 2 ............................................................................................ 299, 305 [c] cc: oscillation mode selection register ......................................................................................................... 107 cks: clock output control register .......................................................................................................... 390, 393 corah: rom correction address register h ........................................................................................................ 563 coral: rom correction address register l ......................................................................................................... 563 corc: rom correction control register .............................................................................................................. 563 cr00: 16-bit capture/compare register 00 ......................................................................................................... 162 cr01: 16-bit capture/compare register 01 ......................................................................................................... 163 cr10: 8-bit compare register 10 ........................................................................................................................ 195 cr20: 8-bit compare register 20 ........................................................................................................................ 195 cr50: 8-bit compare register 50 ........................................................................................................................ 216 cr60: 8-bit compare register 60 ........................................................................................................................ 216 cr70: 8-bit compare register 70 ........................................................................................................................ 237 cr80: 8-bit compare register 80 ........................................................................................................................ 237 crc0: capture/compare control register 0 ........................................................................................................ 167 csiic0: interrupt control register .......................................................................................................................... 405 csim0: serial operation mode register 0 ............................................................................................ 325, 327, 328 csim1: serial operation mode register 1 ............................................................................................ 319, 320, 321 csim2: serial operation mode register 2 ............................................................................................ 319, 320, 321 [d] dacs0: d/a conversion setting register 0 ............................................................................................................ 284 dacs1: d/a conversion setting register 1 ............................................................................................................ 284 dam0: d/a converter mode register 0 ................................................................................................................ 285 dam1: d/a converter mode register 1 ................................................................................................................ 285 [e] ebts: external bus type selection register ........................................................................................................ 478 egn0: external interrupt falling edge enable register ....................................................................................... 395 egp0: external interrupt rising edge enable register ........................................................................................ 395 exae: external access status enable register ................................................................................................... 510 682 appendix d register index user s manual u13570ej3v0ud [i] iic0: serial shift register .......................................................................................................................... 333, 344 iicc0: i 2 c bus control register ............................................................................................................................ 334 iics0: i 2 c bus status register ............................................................................................................................. 33 9 imc: interrupt mode control register ................................................................................................................ 411 ims: internal memory size switching register ................................................................................................... 78 ispr: in-service priority register ........................................................................................................................ 410 [k] kric: interrupt control register .......................................................................................................................... 407 [m] mk0h: interrupt mask register 0h ....................................................................................................................... 408 mk0l: interrupt mask register 0l ....................................................................................................................... 408 mk1h: interrupt mask register 1h ....................................................................................................................... 408 mk1l: interrupt mask register 1l ....................................................................................................................... 408 mm: memory expansion mode register ........................................................................................................... 477 [o] osts: oscillation stabilization time specification register ......................................................................... 109, 520 [p] p0: port 0 ............................................................................................................................... ......................... 120 p1: port 1 ............................................................................................................................... ......................... 122 p10: port 10 ............................................................................................................................... ....................... 139 p12: port 12 ............................................................................................................................... ....................... 140 p13: port 13 ............................................................................................................................... ....................... 141 p2: port 2 ............................................................................................................................... ......................... 123 p3: port 3 ............................................................................................................................... ......................... 127 p4: port 4 ............................................................................................................................... ......................... 129 p5: port 5 ............................................................................................................................... ......................... 130 p6: port 6 ............................................................................................................................... ......................... 131 p7: port 7 ............................................................................................................................... ......................... 133 p8: port 8 ............................................................................................................................... ......................... 137 p9: port 9 ............................................................................................................................... ......................... 138 pcs: clock status register ....................................................................................................................... 108, 518 pf2: port function control register ................................................................................................................... 147 pic0: interrupt control register .......................................................................................................................... 405 pic1: interrupt control register .......................................................................................................................... 405 pic2: interrupt control register .......................................................................................................................... 405 pic3: interrupt control register .......................................................................................................................... 405 pic4: interrupt control register .......................................................................................................................... 405 pic5: interrupt control register .......................................................................................................................... 405 pic6: interrupt control register .......................................................................................................................... 405 pm0: port 0 mode register ............................................................................................................................... . 142 pm10: port 10 mode register .............................................................................................................................. 1 42 pm12: port 12 mode register .............................................................................................................................. 1 42 pm13: port 13 mode register .............................................................................................................................. 1 42 683 appendix d register index user s manual u13570ej3v0ud pm2: port 2 mode register .............................................................................................................. 142, 391, 394 pm3: port 3 mode register ............................................................................................................................... . 142 pm4: port 4 mode register ............................................................................................................................... . 142 pm5: port 5 mode register ............................................................................................................................... . 142 pm6: port 6 mode register ............................................................................................................................... . 142 pm7: port 7 mode register ............................................................................................................................... . 142 pm8: port 8 mode register ............................................................................................................................... . 142 pm9: port 9 mode register ............................................................................................................................... . 142 prm0: prescaler mode register 0 ....................................................................................................................... 169 prm1: prescaler mode register 1 ....................................................................................................................... 199 prm2: prescaler mode register 2 ....................................................................................................................... 199 prm5: prescaler mode register 5 ....................................................................................................................... 220 prm6: prescaler mode register 6 ....................................................................................................................... 220 prm7: prescaler mode register 7 ....................................................................................................................... 241 prm8: prescaler mode register 8 ....................................................................................................................... 241 psw: program status word ......................................................................................................................... 80, 414 pu0: pull-up resistor option register 0 ............................................................................................................. 145 pu10: pull-up resistor option register 10 ........................................................................................................... 145 pu12: pull-up resistor option register 12 ........................................................................................................... 145 pu2: pull-up resistor option register 2 ............................................................................................................. 145 pu3: pull-up resistor option register 3 ............................................................................................................. 145 pu7: pull-up resistor option register 7 ............................................................................................................. 145 pu8: pull-up resistor option register 8 ............................................................................................................. 145 puo: pull-up resistor option register ............................................................................................................... 145 pwc1: programmable wait control register 1 ..................................................................................................... 478 [r] rtbh: real-time output buffer register h ........................................................................................................... 151 rtbl: real-time output buffer register l ........................................................................................................... 151 rtpc: real-time output port control register ..................................................................................................... 153 rtpm: real-time output port mode register ....................................................................................................... 152 rx1: receive shift register 1 ............................................................................................................................ 295 rx2: receive shift register 2 ............................................................................................................................ 295 rxb1: receive buffer register 1 ......................................................................................................................... 295 rxb2: receive buffer register 2 ......................................................................................................................... 295 [s] seric1: interrupt control register .......................................................................................................................... 406 seric2: interrupt control register .......................................................................................................................... 406 sio0: serial i/o shift register 0 .......................................................................................................................... 324 sio1: serial i/o shift register 1 .......................................................................................................................... 318 sio2: serial i/o shift register 2 .......................................................................................................................... 318 snmi: interrupt selection control register .......................................................................................................... 413 sprm0: prescaler mode register for serial clock ................................................................................................. 342 sric1: interrupt control register .......................................................................................................................... 406 sric2: interrupt control register .......................................................................................................................... 406 stbc: standby control register ................................................................................................................... 105, 412 stic1: interrupt control register .......................................................................................................................... 406 stic2: interrupt control register .......................................................................................................................... 406 sva0: slave address register .................................................................................................................... 333, 344 684 appendix d register index user s manual u13570ej3v0ud [t] tm0: 16-bit timer counter 0 ............................................................................................................................... 161 tm1: 8-bit timer counter 1 ............................................................................................................................... .. 195 tm2: 8-bit timer counter 2 ............................................................................................................................... .. 195 tm5: 8-bit timer counter 5 ............................................................................................................................... .. 216 tm6: 8-bit timer counter 6 ............................................................................................................................... .. 216 tm7: 8-bit timer counter 7 ............................................................................................................................... .. 237 tm8: 8-bit timer counter 8 ............................................................................................................................... .. 237 tmc0: 16-bit timer mode control register ........................................................................................................... 164 tmc1: 8-bit timer mode control register 1 .......................................................................................................... 196 tmc2: 8-bit timer mode control register 2 .......................................................................................................... 196 tmc5: 8-bit timer mode control register 5 .......................................................................................................... 217 tmc6: 8-bit timer mode control register 6 .......................................................................................................... 217 tmc7: 8-bit timer mode control register 7 .......................................................................................................... 238 tmc8: 8-bit timer mode control register 8 .......................................................................................................... 238 tmic00: interrupt control register .......................................................................................................................... 406 tmic01: interrupt control register .......................................................................................................................... 406 tmic1: interrupt control register .......................................................................................................................... 407 tmic2: interrupt control register .......................................................................................................................... 407 tmic3: interrupt control register .......................................................................................................................... 406 tmic5: interrupt control register .......................................................................................................................... 407 tmic6: interrupt control register .......................................................................................................................... 407 tmic7: interrupt control register .......................................................................................................................... 407 tmic8: interrupt control register .......................................................................................................................... 407 toc0: 16-bit timer output control register .......................................................................................................... 167 txs1: transmit shift register 1 ........................................................................................................................... 295 txs2: transmit shift register 2 ........................................................................................................................... 295 [w] wdm: watchdog timer mode register ....................................................................................................... 262, 412 wdtic: interrupt control register .......................................................................................................................... 405 wtic: interrupt control register .......................................................................................................................... 407 wtm: watch timer mode control register .......................................................................................................... 257 685 user s manual u13570ej3v0ud appendix e revision history (1/7) edition major revised contents from previous version location 2nd edition combination of manuals of pd784216a/784216ay subseries and throughout pd784218a/784218ay subseries with following part numbers changed: before change: pd784217, 784218, 784217y, 784218y, 78f4218, 78f4218y after change: pd784217a, 784218a, 784217ay, 784218ay, 78f4218a, 78f4218ay products covered pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay, 78f4216a, 78f4218a, 78f4216ay, 784218ay change of power supply voltage chapter 1 overview mask version: v dd = 2.2 v to 5.5 v v dd = 1.8 v to 5.5 v flash memory: v dd = 2.7 v to 5.5 v v dd = 1.9 v to 5.5 v modification of table 2-1 i/o circuit type for each pin and chapter 2 pin functions handling unused pins modification of figure 2-1 pin i/o circuit modification of figure 3-7 internal memory size switching chapter 3 cpu architecture register (ims) format modification of table 3-7 special function register (sfr) list modification of text in (1) main system clock oscillator chapter 4 clock generator modification of figure 4-1 block diagram of clock generator modification of figure 4-2 standby control register (stbc) format modification of figure 4-4 clock status register (pcs) format change of caution in 5.2.1 port 0 chapter 5 port functions modification of figure 5-2 block diagram of p00 to p06 modification of figure 5-3 block diagram of p10 to p17 modification of figures 5-4 to 5-7 block diagrams of p20 to p27 modification of figures 5-8 and 5-9 block diagrams of p30 to p37 modification of figure 5-10 block diagram of p40 to p47 modification of figure 5-11 block diagram of p50 to p57 modification of figures 5-12 to 5-14 block diagrams of p60 to p67 modification of figures 5-15 to 5-17 block diagrams of p70 to p72 modification of figure 5-22 block diagram of p120 to p127 modification of figure 5-23 block diagram of p130 and p131 addition of caution to figure 5-25 pull-up resistor option register format addition of caution to figure 6-4 real-time output port control chapter 6 real-time output register (rtpc) format functions modification of text in 6.5 usage 686 appendix e revision history user s manual u13570ej3v0ud (2/7) edition major revised contents from previous version location 2nd edition addition of table 8-4 valid edge of ti00 pin and capture chapter 8 16-bit timer/event trigger of cr01 counter modification of figure 8-4 format of 16-bit timer output control register (toc0) modification of caution of figure 8-5 format of prescaler mode register 0 (prm0) addition of caution to figure 8-12 timing of pulse width measurement with free-running counter and one capture register (with both edges specified) addition of caution to figure 8-15 timing of pulse width measurement with free-running counter (with both edges specified) addition of caution to figure 8-17 timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) addition of caution to figure 8-19 timing of pulse width measurement by restarting (with rising edge specified) modification of text in 8.4.4 operation as external event counter addition of caution 2 to 8.4.6 operation as one-shot pulse output addition of c aution 2 to figure 8-26 timing of one-shot pulse output operation with software trigger modification of caution in (3) one-shot pulse output with external trigger addition of caution 2 to figure 8-28 timing of one-shot pulse output operation with external trigger (with rising edge specified) addition of (6) cautions on edge detection addition of (7) trigger for one-shot pulse change of figure 9-1 block diagram of 8-bit timer/event chapter 9 8-bit timer/event counter 1, 2 counter 1, 2 modification of caution in (1) 8-bit timer counter 1, 2 (tm1, tm2) modification of caution in (2) 8-it compare register 1, 2 (cr10, cr20) modification of text in (1) 8-bit timer mode control register 1, 2 (tmc1, tmc2) change of figure 9-2 format of 8-bit timer mode control register 1 (tmc1) change of figure 9-3 format of 8-bit timer mode control register 2 (tmc2) addition of caution 3 to figure 9-4 format of prescaler mode register 1 (prm1) addition of caution 3 to figure 9-5 format of prescaler mode register 2 (prm2) modification of setting method in 9.4.3 operation as square wave output (8-bit resolution) modification of setting method in 9.4.4 operation as 8-bit pwm output 687 appendix e revision history user s manual u13570ej3v0ud (3/7) edition major revised contents from previous version location 2nd edition change of figure 9-8 timing of pwm output chapter 9 8-bit timer/event modification of caution 4 in 9.4.5 operation as internal timer counter 1, 2 (16-bit operation) modification of text in (3) tm1, tm2 read out during timer operation in 9.5 cautions change of figure 10-1 block diagram of 8-bit timer/event chapter 10 8-bit timer/event counter 5, 6 counter 5, 6 modification of caution in (1) 8-bit timer counter 5, 6 (tm5, tm6) modification of caution in (2) 8-bit compare register 5, 6 (cr50, cr60) modification of text in (1) 8-bit timer mode control register 5, 6 (tmc5, tmc6) change of figure 10-2 format of 8-bit timer mode control register 5 (tmc5) change of figure 10-3 format of 8-bit timer mode control register 6 (tmc6) addition of caution 3 to figure 10-4 format of prescaler mode register 5 (prm5) addition of caution 3 to figure 10-5 format of prescaler mode register 6 (prm6) modification of setting method in 10.4.3 operation as square wave output (8-bit resolution) modification of setting method in 10.4.4 operation as 8-bit pwm output change of figure 10-8 timing of pwm output modification of caution 4 in 10.4.5 operation as internal timer (16-bit operation) modification of text in (3) tm5, tm6 read out during timer operation in 10.5 cautions changer of figure 11-1 block diagram of 8-bit timer/event chapter 11 8-bit timer/event counter 7, 8 counter 7, 8 modification of caution in (1) 8-bit timer counter 7, 8 (tm7, tm8) modification of caution in (2) 8-bit compare register 7, 8 (cr70, cr80) modification of text in (1) 8-bit timer mode control register 7, 8 (tmc7, tmc8) change of figure 11-2 format of 8-bit timer mode control register 7 (tmc7) change of figure 11-3 format of 8-bit timer mode control register 8 (tmc8) addition of caution 3 to figure 11-4 format of prescaler mode register 7 (prm7) addition of caution 3 to figure 11-5 format of prescaler mode register 8 (prm8) modification of setting method in 11.4.3 operation as square wave output (8-bit resolution) 688 appendix e revision history user s manual u13570ej3v0ud (4/7) edition major revised contents from previous version location 2nd edition modification of setting method in 11.4.4 operation as 8-bit pwm chapter 11 8-bit timer/event output counter 7, 8 change of figure 11-8 timing of pwm output modification of caution 4 in 11.4.5 operation as interval timer (16-bit operation) modification of text in (3) tm7, tm8 read out during timer operation in 11.5 cautions addition of figure 12-1 block diagram of watch timer chapter 12 watch timer addition of caution to figure 12-2 format of watch timer mode control register (wtm) addition of caution to table 12-3 interval time of interval timer modification of figure 12-3 operation timing of watch timer/ interval timer modification of figure 13-1 watchdog timer block diagram chapter 13 watchdog timer modification of text in 13.3.2 interrupt priority order modification of figure 14-1 a/d converter block diagram chapter 14 a/d converter modification of figure 14-2 a/d converter mode register (adm) format addition of caution to 14.4.1 basic operation of a/d converter addition of note to figure 14-6 a/d conversion operation by hardware start (with falling edge specified) addition of note to figure 14-7 a/d conversion operation by software start change of figure 14-8 method to reduce current consumption in standby mode addition of note to figure 14-10 a/d conversion end interrupt generation timing addition of an item (14) to 14.5 cautions addition of figure 14-15 internal equivalence circuit of ani0 to ani7 pins addition of table 14-2 resistance and capacitance values for equivalence circuits (reference values) addition of figure 14-16 example of circuit when signal source impedance is high addition of table 17-2 serial interface operation mode settings chapter 17 asynchronous modification of figure 17-2 block diagram in asynchronous serial interface/3-wire serial serial interface mode i/o addition of caution 2 to figure 17-5 baud rate generator control registers 1, 2 (brgc1, brgc2) format modification of equation of baud rate modification of table 17-4 relationship between main system clock and baud rate modification of caution of the procedure in the case of uart transmission 689 appendix e revision history user s manual u13570ej3v0ud (5/7) edition major revised contents from previous version location 2nd edition modification of note of table 17-6 bit rate and pulse width chapter 17 asynchronous values serial interface/3-wire serial addition of note 2 to figure 17-13 serial operation mode i/o registers 1, 2 (csim1, csim2) format addition of note 2 to figure 17-15 serial operation mode registers 1, 2 (csim1, csim2) format modification of figure 18-1 block diagram of clocked serial chapter 18 3-wire serial i/o interface (in 3-wire serial i/o mode) mode addition of caution to figure 18-2 serial operation mode register 0 (csim0) format addition of caution to figure 18-4 serial operation mode register 0 (csim0) format modification of figure 19-1 serial bus configuration example chapter 19 i 2 c bus mode in i 2 c bus mode ( pd784216ay, 784218ay subseries modification of figure 19-3 i 2 c bus control register (iicc0) only) format modification of figure 19-5 format of prescaler mode register for serial clock (sprm0) change of values of table 19-2 intic0 generation timing and wait control change of values of table 19-5 wait times addition of figure 22-2 block diagram of p00 to p06 pins chapter 22 edge detection function addition of remark 3 to table 23-2 interrupt request sources chapter 23 interrupt modification of figure 23-32 stepping motor open loop control functions by real-time output port modification of figure 23-33 data transfer control timing modification of figure 23-36 automatic addition control + ring control block diagram 1 (when output timing varies with 1-2- phase excitation) modification of figure 23-37 automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) modification of figure 23-38 automatic addition control + ring control block diagram 2 (1-2-phase excitation constant- velocity operation) modification of figure 23-39 automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant- velocity operation) modification of 23.13 cautions modification of programmable wait control register 2 (pwc2) of in- chapter 24 local bus interface circuit emulator functions addition of figure 24-4 memory map of pd784214a addition of figure 24-5 memory map of pd784215a addition of figure 24-6 memory map of pd784216a 690 appendix e revision history user s manual u13570ej3v0ud (6/7) edition major revised contents from previous version location 2nd edition modification of figure 24-12 read modify write timing for chapter 24 local bus interface external memory in multiplexed bus mode functions modification of figure 24-16 read modify write timing for external memory in separate bus mode modification of figure 24-17 read/write timing by address wait function modification of table 24-5 p37/exa pin status during each mode modification of table 25-2 operating states in halt mode chapter 25 standby function modification of (5) of figure 25-5 operation after halt mode release modification of caution in 25.4.1 settings and operating states of stop mode modification of figure 25-12 setting timing for subsystem clock operation modification of figure 25-6 operation after stop mode release modification of figure 25-7 releasing stop mode by nmi input modification of figure 25-8 example of releasing stop mode by intp0 to intp6 inputs modification of table 25-7 operating states in idle mode addition of (5) to figure 25-9 operation after idle mode release modification of address of figure 25-11 flow for setting subsystem clock operation modification of address of figure 25-12 setting timing for subsystem clock operation modification of address of figure 25-13 flow to restore main system clock operation modification of address figure 25-14 timing for restoring main system clock operation modification of table 25-9 operating states in halt mode modification of table 25-10 operating states in idle mode modification of figure 26-1 oscillation of main system clock in chapter 26 reset function reset period modification of figure 26-2 accepting reset signal addition of chapter chapter 27 rom correction ( pd784218a, 784218ay subseries only) modification of table 28-1 communication protocols chapter 28 flash memory modification of figure 28-1 communication protocol selection format modification of table 28-2 major functions in flash memory programming addition of figure 28-2 connection of flashpro iii in 3-wire serial i/o mode (when using 3-wire serial i/o 0) 691 appendix e revision history user s manual u13570ej3v0ud (7/7) edition major revised contents from previous version location 2nd edition addition of f igure 28-3 connection of flashpro iii in 3-wire chapter 28 flash memory serial i/o mode (when using handshake) programming addition of figure 28-4 connection of flashpro iii in uart mode (when using uart) 3rd edition update of 78k/iv product lineup chapter 1 general modification of figure 4-4 clock status register (pcs) format chapter 4 clock generator modification of tmic00 bit name in figure 23-1 interrupt control chapter 23 interrupt functions register ( icn) modification of figure 25-1 standby function state transitions chapter 25 standby function modification of table 25-5 operating states in stop mode modification of description in 25.4.2 (3) releasing the stop mode by reset input modification of description in 25.5.2 (3) releasing the idle mode by reset input modification of description in 25.6 (5) a/d converter modification of description in 25.7.3 (1) (b) (iii) releasing the halt mode by reset input modification of description in 25.7.3 (2) (a) setting the idle mode and the operating states modification of description in 25.7.3 (2) (b) (iii) releasing the idle mode by reset input addition of chapter chapter 30 electrical specifications ( pd784214a, 784215a, 784216a, 784217a, 784218a, 784214ay, 784215ay, 784216ay, 784217ay, 784218ay) addition of chapter chapter 31 electrical specifications ( pd78f4216a, 78f4218a, 78f4216ay, 78f4218ay) addition of chapter chapter 32 package drawings addition of chapter chapter 33 recommended soldering conditions addition of sp78k4 to b.1 language processing software , appendix b development tools modification of description in remark addition and modification of description in b.3.1 hardware modification of description in remark in b.3.2 software addition of b.4 cautions on designing target system modification of description appendix c embedded software |
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